Setting up the TTBR0 and TTBR1 register for thread stack protection in ARMv7-A MMU

[Utkarsh Rai]

Hello,

Section B3.3.3 of the ARMv7-A Reference manual
<https://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf>
says that we can have TTBR0 and 1 split up the address space into two
parts, where each register has the address of the translation table base
of the divided address space.
One of the ways to simplify the implementation of thread-stack protection
in ARMv7-A MMU can be, to have the global statically allocated sections
being pointed by the TTBR1 register and the work-space area being pointed
out by the TTBR0 register. This way during context switch we would only
have to change the TTBR0 register, this would also simplify the
implementation as we won't have to worry about addresses of different page
sizes being pointed by the same translation-table base.
In the current implementation, TTB is put in TTBR0, and TTBR1 is not used.
Is the above-suggested implementation feasible?

Regards,
Utkarsh
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