RISCV-SIS: Different busy cycles per tick for primary and secondary cores

[Jan.Sommer at dlr.de]

Hello,

We noticed a bit strange behavior while doing some measurements with the riscv bsps running on SIS.
If we run "T_get_one_clock_tick_busy" to get a base reference for busy cycles, the values between cpu0 and other secondary cores differ by a constant value.
For example for a 200us tick time:
cpu0:  4460 cycles per tick
cpu1:  4848 cycles per tick
cpu2:  4848 cycles per tick

Results for multiple calls on the same core only differ in a few ticks.
For a 500us tick time it yields:
cpu0:  11957 cycles per tick
cpu1:  12350 cycles per tick
cpu2:  12348 cycles per tick

So, in both cases there is a constant difference of approx. 390 cyples per tick between core0 and all other cores.
We ran the test application with "riscv-rtems6-sis -m 4 bin/test-busy-loop.elf -freq 100 -d 25 -r"
Is this something to be expected and what could be the reason for this (e.g. in rtems or in the SIS)?

Best regards,

    Jan

Deutsches Zentrum für Luft- und Raumfahrt e. V. (DLR)
German Aerospace Center
Institute for Software Technology | Software for Space Systems and Interactive Visualization | Lilienthalplatz 7 | 38108 Braunschweig | Germany