[PATCH 2/4] bsp/riscv: Add NOEL-V BSP
Daniel Hellstrom
daniel at gaisler.com
Mon Feb 8 19:44:13 UTC 2021
From: Martin Aberg <maberg at gaisler.com>
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user'manuals and quick-start guides:
- NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU)
Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.
Update #4225.
---
bsps/riscv/noel/console/console-config.c | 182 +++++++++++++++++++++++++++++++
bsps/riscv/noel/include/bsp.h | 76 +++++++++++++
bsps/riscv/noel/include/bsp/irq.h | 75 +++++++++++++
bsps/riscv/noel/include/tm27.h | 1 +
bsps/riscv/noel/start/bsp_fatal_halt.c | 36 ++++++
5 files changed, 370 insertions(+)
create mode 100644 bsps/riscv/noel/console/console-config.c
create mode 100644 bsps/riscv/noel/include/bsp.h
create mode 100644 bsps/riscv/noel/include/bsp/irq.h
create mode 100644 bsps/riscv/noel/include/tm27.h
create mode 100644 bsps/riscv/noel/start/bsp_fatal_halt.c
diff --git a/bsps/riscv/noel/console/console-config.c b/bsps/riscv/noel/console/console-config.c
new file mode 100644
index 0000000..11ee6d6
--- /dev/null
+++ b/bsps/riscv/noel/console/console-config.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2021 Cobham Gaisler AB.
+ *
+ * Copyright (c) 2018 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/bspIo.h>
+#include <rtems/console.h>
+#include <rtems/sysinit.h>
+#include <rtems/termiostypes.h>
+
+#include <bsp/fatal.h>
+#include <bsp/fdt.h>
+#include <bsp/irq.h>
+#include <bsp/riscv.h>
+
+#include <libfdt.h>
+
+#define RISCV_CONSOLE_MAX_APBUART_DEVICES 4
+
+#include <grlib/apbuart.h>
+#include <grlib/apbuart_termios.h>
+static struct apbuart_context apbuarts[RISCV_CONSOLE_MAX_APBUART_DEVICES];
+static size_t apbuart_devices = 0;
+
+static struct {
+ rtems_termios_device_context *context;
+ void (*putchar)(rtems_termios_device_context *base, char c);
+ int (*getchar)(rtems_termios_device_context *base);
+} riscv_console;
+
+static void riscv_output_char(char c)
+{
+ (*riscv_console.putchar)(riscv_console.context, c);
+}
+
+static void apbuart_putchar(rtems_termios_device_context *base, char c)
+{
+ struct apbuart_context *ctx = (struct apbuart_context *) base;
+ apbuart_outbyte_polled(ctx->regs, c, 0, 1);
+}
+
+static int apbuart_getchar(rtems_termios_device_context *base)
+{
+ struct apbuart_context *ctx = (struct apbuart_context *) base;
+ return apbuart_inbyte_nonblocking(ctx->regs);
+}
+
+#define RISCV_CONSOLE_IS_COMPATIBLE(actual, actual_len, desired) \
+ (actual_len == sizeof(desired) \
+ && memcmp(actual, desired, sizeof(desired) - 1) == 0)
+
+static uint32_t get_core_frequency(void)
+{
+ uint32_t node;
+ const char *fdt;
+ int len;
+ const fdt32_t *val;
+
+ fdt = bsp_fdt_get();
+ node = fdt_node_offset_by_compatible(fdt, -1, "fixed-clock");
+
+ val = fdt_getprop(fdt, node, "clock-frequency", &len);
+ if (val != NULL && len == 4) {
+ return fdt32_to_cpu(*val);
+ }
+ return 0;
+}
+
+static void riscv_console_probe(void)
+{
+ const void *fdt;
+ int node;
+
+ fdt = bsp_fdt_get();
+
+ node = fdt_next_node(fdt, -1, NULL);
+
+ while (node >= 0) {
+ const char *compat;
+ int compat_len;
+
+ compat = fdt_getprop(fdt, node, "compatible", &compat_len);
+ if (compat == NULL) {
+ compat_len = 0;
+ }
+
+ if (
+ RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "gaisler,apbuart")
+ && (apbuart_devices < RISCV_CONSOLE_MAX_APBUART_DEVICES)
+ ) {
+ struct apbuart_context *ctx;
+ fdt32_t *val;
+ int len;
+
+ ctx = &apbuarts[apbuart_devices];
+
+ ctx->regs = riscv_fdt_get_address(fdt, node);
+ if (ctx->regs == NULL) {
+ bsp_fatal(RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE);
+ }
+
+ ctx->freq_hz = get_core_frequency();
+
+ val = (fdt32_t *) fdt_getprop(fdt, node, "interrupts", &len);
+ if (val == NULL || len != 4) {
+ bsp_fatal(RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE);
+ }
+ ctx->irq = RISCV_INTERRUPT_VECTOR_EXTERNAL(fdt32_to_cpu(val[0]));
+
+ if (apbuart_devices == 0) {
+ riscv_console.context = &ctx->base;
+ riscv_console.putchar = apbuart_putchar;
+ riscv_console.getchar = apbuart_getchar;
+ }
+
+ rtems_termios_device_context_initialize(&ctx->base, "APBUART");
+
+ apbuart_devices++;
+ };
+
+ node = fdt_next_node(fdt, node, NULL);
+ }
+
+ BSP_output_char = riscv_output_char;
+}
+
+static void riscv_output_char_init(char c)
+{
+ riscv_console_probe();
+ riscv_output_char(c);
+}
+
+BSP_output_char_function_type BSP_output_char = riscv_output_char_init;
+
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
+
+rtems_status_code console_initialize(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ char path[] = "/dev/ttyS?";
+
+ rtems_termios_initialize();
+
+ const rtems_termios_device_handler *handler = &apbuart_handler_polled;
+
+ if (CONSOLE_USE_INTERRUPTS) {
+ handler = &apbuart_handler_interrupt;
+ }
+ for (size_t i = 0; i < apbuart_devices; ++i) {
+ struct apbuart_context *ctx;
+
+ ctx = &apbuarts[i];
+ path[sizeof(path) - 2] = (char) ('0' + i);
+ rtems_termios_device_install(path, handler, NULL, &ctx->base);
+
+ if (&ctx->base == riscv_console.context) {
+ link(path, CONSOLE_DEVICE_NAME);
+ }
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
+
+RTEMS_SYSINIT_ITEM(
+ riscv_console_probe,
+ RTEMS_SYSINIT_BSP_START,
+ RTEMS_SYSINIT_ORDER_LAST_BUT_5
+);
diff --git a/bsps/riscv/noel/include/bsp.h b/bsps/riscv/noel/include/bsp.h
new file mode 100644
index 0000000..1b6686a
--- /dev/null
+++ b/bsps/riscv/noel/include/bsp.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsRISCVNOEL
+ *
+ * @brief Global BSP definitions.
+ */
+
+/*
+ * Copyright (c) 2021 Cobham Gaisler AB.
+ *
+ * Copyright (c) 2015 University of York.
+ * Hesham Almatary <hesham at alumni.york.ac.uk>
+ *
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_RISCV_NOEL_H
+#define LIBBSP_RISCV_NOEL_H
+
+/**
+ * @defgroup RTEMSBSPsRISCVNOEL NOEL-V
+ *
+ * @ingroup RTEMSBSPsRISCV
+ *
+ * @brief NOEL-V RISC-V Board Support Package.
+ *
+ * @{
+ */
+
+#include <rtems.h>
+#include <rtems/clockdrv.h>
+#include <rtems/console.h>
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems/devnull.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#define BSP_FDT_IS_SUPPORTED
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* LIBBSP_RISCV_NOEL_H */
diff --git a/bsps/riscv/noel/include/bsp/irq.h b/bsps/riscv/noel/include/bsp/irq.h
new file mode 100644
index 0000000..95cbe55
--- /dev/null
+++ b/bsps/riscv/noel/include/bsp/irq.h
@@ -0,0 +1,75 @@
+/**
+ * @file
+ *
+ * @ingroup RISCV_IRQ
+ *
+ * @brief Interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2021 Cobham Gaisler AB.
+ *
+ * Copyright (c) 2018 embedded brains GmbH
+ *
+ * Copyright (c) 2015 University of York.
+ * Hesham Almatary <hesham at alumni.york.ac.uk>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_RISCV_NOEL_IRQ_H
+#define LIBBSP_RISCV_NOEL_IRQ_H
+
+#ifndef ASM
+
+#include <bsp.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+#include <rtems/score/processormask.h>
+
+#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
+
+#define RISCV_INTERRUPT_VECTOR_TIMER 1
+
+#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
+
+#define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2)
+
+#define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2)
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
+
+void bsp_interrupt_set_affinity(
+ rtems_vector_number vector,
+ const Processor_mask *affinity
+);
+
+void bsp_interrupt_get_affinity(
+ rtems_vector_number vector,
+ Processor_mask *affinity
+);
+
+#endif /* ASM */
+
+#endif /* LIBBSP_RISCV_NOEL_IRQ_H */
diff --git a/bsps/riscv/noel/include/tm27.h b/bsps/riscv/noel/include/tm27.h
new file mode 100644
index 0000000..0dfa7bf
--- /dev/null
+++ b/bsps/riscv/noel/include/tm27.h
@@ -0,0 +1 @@
+#include <rtems/tm27-default.h>
diff --git a/bsps/riscv/noel/start/bsp_fatal_halt.c b/bsps/riscv/noel/start/bsp_fatal_halt.c
new file mode 100644
index 0000000..8dca449
--- /dev/null
+++ b/bsps/riscv/noel/start/bsp_fatal_halt.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Cobham Gaisler AB
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/riscv.h>
+
+void _CPU_Fatal_halt(uint32_t source, uint32_t error)
+{
+ __asm__ volatile ("ebreak");
+ while (true) {
+ ;
+ }
+}
--
2.7.4
More information about the devel
mailing list