[PATCH 1/6] nios2: Fix ISR dispatch variants

[Sebastian Huber]

The thread dispatch disabled level moved to _Per_CPU_Information some
time ago.
---
 cpukit/score/cpu/nios2/nios2-eic-il-low-level.S   | 7 +++----
 cpukit/score/cpu/nios2/nios2-eic-rsie-low-level.S | 9 ++++-----
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
index 61eaa8cde6..a8045d74df 100644
--- a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
+++ b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
@@ -41,7 +41,6 @@
 	.section	.text
 
 	.extern	_Per_CPU_Information
-	.extern	_Thread_Dispatch_disable_level
 	.extern	_Nios2_Thread_dispatch_disabled
 	.extern	_Nios2_ISR_Status_interrupts_disabled
 
@@ -50,7 +49,7 @@
 _Nios2_ISR_Dispatch_with_shadow_non_preemptive:
 
 	/* Load thread dispatch disable level */
-	ldw	r16, %gprel(_Thread_Dispatch_disable_level)(gp)
+	ldw	r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 
 	/* Load high level handler address and argument */
 	ldw	r8, 4(et)
@@ -58,7 +57,7 @@ _Nios2_ISR_Dispatch_with_shadow_non_preemptive:
 
 	/* Increment and store thread dispatch disable level */
 	addi	r9, r16, 1
-	stw	r9, %gprel(_Thread_Dispatch_disable_level)(gp)
+	stw	r9, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 
 	/* Call high level handler with argument */
 	callr	r8
@@ -81,7 +80,7 @@ _Nios2_ISR_Dispatch_with_shadow_non_preemptive:
 	 * problems if someone deletes or restarts the interrupted thread while
 	 * we are in the thread dispatch helper.
 	 */
-	stw	r16, %gprel(_Thread_Dispatch_disable_level)(gp)
+	stw	r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 
 	/* Is thread dispatch allowed? */
 	bne	r16, zero, no_thread_dispatch
diff --git a/cpukit/score/cpu/nios2/nios2-eic-rsie-low-level.S b/cpukit/score/cpu/nios2/nios2-eic-rsie-low-level.S
index fc11d335eb..4dd3749c45 100644
--- a/cpukit/score/cpu/nios2/nios2-eic-rsie-low-level.S
+++ b/cpukit/score/cpu/nios2/nios2-eic-rsie-low-level.S
@@ -40,7 +40,6 @@
 	.section	.text
 
 	.extern	_Per_CPU_Information
-	.extern	_Thread_Dispatch_disable_level
 
 	.globl	_Nios2_ISR_Dispatch_with_shadow_preemptive
 
@@ -81,11 +80,11 @@ _Nios2_ISR_Dispatch_with_shadow_preemptive:
 
 	/* Increment ISR nest level and thread dispatch disable level */
 	ldw	r9, %gprel(_Per_CPU_Information + PER_CPU_ISR_NEST_LEVEL)(gp)
-	ldw	r10, %gprel(_Thread_Dispatch_disable_level)(gp)
+	ldw	r10, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 	addi	r11, r9, 1
 	addi	r10, r10, 1
 	stw	r11, %gprel(_Per_CPU_Information + PER_CPU_ISR_NEST_LEVEL)(gp)
-	stw	r10, %gprel(_Thread_Dispatch_disable_level)(gp)
+	stw	r10, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 
 	/* Switch to interrupt stack if necessary */
 	bne	r9, zero, switch_to_interrupt_stack_done
@@ -114,11 +113,11 @@ switch_to_interrupt_stack_done:
 
 	/* Decrement ISR nest level and thread dispatch disable level */
 	ldw	r9, %gprel(_Per_CPU_Information + PER_CPU_ISR_NEST_LEVEL)(gp)
-	ldw	r10, %gprel(_Thread_Dispatch_disable_level)(gp)
+	ldw	r10, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 	subi	r9, r9, 1
 	subi	r10, r10, 1
 	stw	r9, %gprel(_Per_CPU_Information + PER_CPU_ISR_NEST_LEVEL)(gp)
-	stw	r10, %gprel(_Thread_Dispatch_disable_level)(gp)
+	stw	r10, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp)
 
 	/*
 	 * Restore stack pointer.  If the ISR nest level is greater than one,
-- 
2.26.2