[PATCH v1] bsps/riscv: Give enough time for clock driver initialization

[Gedare Bloom]

On Mon, Jun 7, 2021 at 9:47 AM Jan Sommer <jan.sommer at dlr.de> wrote:
>
> - Clock driver initialization for secondary cores had to take less than
> one tick
> - If tick time is small (i.e. <= 1ms) setting up all cores could take
> too long and a fatal error is thrown.
> - Give at least 10 ms time for clock initialization to avoid this error

Is there a reason to pick 10?

I assume this blocks/idles the system until the interval elapses, so
it would be good to minimize waste (subject to Joel's noted rant about
premature optimization).

> ---
>  bsps/riscv/riscv/clock/clockdrv.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c
> index 3afe86576f..102137aeab 100644
> --- a/bsps/riscv/riscv/clock/clockdrv.c
> +++ b/bsps/riscv/riscv/clock/clockdrv.c
> @@ -211,7 +211,13 @@ static void riscv_clock_initialize(void)
>    tc->interval = interval;
>
>    cmpval = riscv_clock_read_mtime(&clint->mtime);
> -  cmpval += interval;
> +  /*
> +   * For very short intervals the time of 1 tick is not enough to
> +   * set up the timer on all cores in SMP systems.
> +   * Give the CPU at least 10 ms.
> +   */
> +  interval = (10000 / us_per_tick) * interval;
> +  cmpval += interval;
>
>    riscv_clock_clint_init(clint, cmpval, 0);
>    riscv_clock_secondary_initialization(clint, cmpval, interval);
> --
> 2.17.1
>
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