Project Ideas - Basic RTEMS BSP for Cortex-R5 on Qemu
mbenson at windhoverlabs.com
mbenson at windhoverlabs.com
Tue Apr 19 15:03:39 UTC 2022
I’ve received a few emails about our RTEMS on R5 work. Sorry I haven’t responded yet. I made a quick and dirty BSP about 6 months ago just to prove to myself that this was a viable effort. I got it running in the Xilinx Qemu in about a day. I would be happy to mentor anybody wanting to take this on. Sadly, a hard drive failure caused me to lose all my work before I could commit it. One of my new employees has taken up the task. I can introduce you.
Our goal is to port RTEMS to the R5 on the Zynq Ultrascale+ first, and a custom FMC with an R5 that we designed in house second. The first iteration of the R5 board is complete and printed but we haven’t had time to assemble and test it yet. The port to the R5 on the Zynq Ultrascale+ is low lying fruit and should be the easiest by far to complete, since it’s booting from Linux on the A53s. The FSBL runs on the A53, which loads the FPGA and configures the hard cores. Until isolation mode is enabled, the RTEMS/R5 basically piggy backs on Linux/A53. Linux sets up the MMU, the Global Interrupt Controller, and the console UART (if shared). RTEMS just has to setup the timer, and map the console to the correct UART. No uboot. Linux loads the R5 reserved memory and signals the PMU to enable power to the R5. The BSP is trivial. All the work is in the drivers. However, if you use our Zynq Ultrascale+ avionics board (should be publicly available next year), driver development is simplified for designs that follow the commonly used rate monotonic design pattern. Driver code actually runs partitioned in a separate CPU, independent of RTEMS, relieving the R5 from non-deterministic interrupts.
Our second board has a dedicated R5 device. No Zynq. It’s an FPGA Mezzanine Card (FMC), so it follows a form factor common among FPGA boards. You can use it as an expansion to a main board, but it it does not require a main board. It will also work just as well as a stand-alone board. Just give it power and ground. This platform will take a bit more work to add RTEMS support since you have no A53 doing all the heavy lifting. In its current prototype iteration, it has no attached memory, only internal memory. It also has a UART chip to give us additional UARTs. The next iterations will include additional memory and line drivers for RS-422 support. This board will require driver development.
I am most interested in getting RTEMS running on the R5 FMC.
Sent from my iPhone
> On Apr 17, 2022, at 10:20, Joel Sherrill <joel at rtems.org> wrote:
>
> On Sun, Apr 17, 2022, 5:17 AM Pavel Pisa <ppisa4lists at pikron.com> wrote:
>
>> Dear Kamlesh,
>>
>>> On Sunday 17 of April 2022 10:19:01 Kamlesh Bharodiya wrote:
>>> Thanks for your mail. I have not worked on ZCU102. Though, I'm working
>> with
>>> R4F currently. Shall I go ahead with the GSoC application? Or should I
>> wait
>>> for any other mentor to reply ?
>>
>> I do not feel competent to be main mentor for this project
>> and some feedback from people working on RTEMS core
>> would be helpfull. But I expect that most are on Easters
>> now so the time to submission deadline is relatively tight.
>>
>
> The R5 basic BSP is needed by the RTEMS community. If you get through that,
> you could look at the Xilinx code for interacting with it.
>
>
>
>
>
>> I am not sure if somebody else see potential to use RTEMS or Cortex-R5
>> integrated into ZCU102. I see it in general but do not see any
>> such project on my horizon university work nor company projects
>> horizon. I have actually neither project with TMS570LC4357,
>> but I have at least HW and it could be nice platform to test
>> RTEMS CAN support if it is updated during this year another GSoC
>> and interesting platform for LwIP testing... But there is no
>> QEMU support and I do not suggest to change your project to this
>> direction.
>>
>> As I have checked, it seems that it is possible to use ZCU102 R5
>> somehow with local UART and timer so it makes project initial
>> phases as feasible in the GSoC frame. Do you plan project as
>> the longer or shorter GSoC variant?
>>
>> I suggest to apply before submission deadline even if the
>> project is not fully clarified before deadline. It will
>> be discussed by RTEMS mentors and can be slightly adjusted,
>> extended before coding phase to match core team vision.
>> Other option is to select another open topic which is on
>> the RTEMS project interest list
>>
>> https://devel.rtems.org/wiki/Developer/OpenProjects
>>
>> But if you have already some experience with Cortex-R4
>> and see some real application use for your work then
>> the goal has reason.
>>
>> You wrote in your proposal
>>
>> Testing R4 BSP on Qemu - but I think that there is no such
>> available target for now
>>
>> As for the timeline, I suggest to move testing and familiarization
>> with RTEMS and QEMU ecosystem into bonding period and start real
>> coding with start of GSoC coding period to have something to
>> to evaluate and running in the middle
>>
>> Testing R4 BSP on Qemu, and few other BSPs on Qemu like STM32 BSP
>> to get familiarize myself with machines on Qemu
>>
>> Because if you finish work only after the second half then there
>> is not enough time for review, clean up, documentation and adjustment
>> for mainline submission. Expect two or three round for it and
>> this should be real goal of GSoC and real evaluation.
>> So I suggest move more coding to the first half and some reserve
>> and documention and review process to the second half.
>>
>> Best wishes,
>>
>> Pavel
>>
>>> On Sat, 16 Apr, 2022, 7:41 pm Pavel Pisa, <ppisa4lists at pikron.com>
>> wrote:
>>>> Dear Kamlesh,
>>>>
>>>> On Friday 15 of April 2022 06:50:44 Kamlesh Bharodiya wrote:
>>>>> I am looking for mentors for my project. How can I connect to
>>>>> interested mentors? I have uploaded the draft proposal on GSoC
>> tracking
>>>>> page.
>>>>
>>>> I have long time interrest in RTEMS running on TMS570LC4357
>>>> which is Arm Cortex-R5F based. I have TMDX570LC43HDK at home
>>>> and some smaller boards are at Elktroline.cz.
>>>>
>>>> As I know, the Cortex-R5 core is already supported
>>>> by RTEMS and our TMS570LS3137 BSP has been used
>>>> with TMS570LC4357 chips by Frankfurt University
>>>>
>>>> https://www.rz.uni-frankfurt.de/65100666/dcs
>>>>
>>>> Relevant repository
>>>>
>>>> https://github.com/jalmito/rtems
>>>>
>>>> It would worth to get mainline TMS570 BSP compatible with
>>>> both chips.
>>>>
>>>> But back to your project, possibility to run RTEMS on Cortex-R5
>>>> architecture in QEMU would be usesfull for testing. My search through
>>>> actual QEMU sources confirms Cortex-R support and only in Cortex-R5
>>>> and Cortex-R52 variants and only integration on ZCU102.
>>>> But support of Cortex-R5 comprocessor on "big" Xilinx platforms
>>>> can be usesfull. I have helped with bought of these boards
>>>> years ago but for the team which moved away. But I probably
>>>> can find even somebody with HW who could test the code.
>>>>
>>>> The minimal set of the peripherals supported to make port
>>>> usable and living needs to include GIC (generic interrupt controller),
>>>> TTC (system timer) and UART (serial port).
>>>> Other option is some mailbox based exchange with main Cortex-A CPU.
>>>>
>>>> Have you some experience with ZCU102?
>>>> I have no much idea how difficult the project is...
>>>>
>>>> I can help as co-mentor, I cannot offer main mentor role
>>>> because I have too many running projects.
>>>>
>>>> I CC to Sebastian Huber, because if I remember well they
>>>> have provided support for some Cortex-R5 platform already.
>>>>
>>>> Best wishes,
>>>>
>>>> Pavel Pisa
>>>> phone: +420 603531357
>>>> e-mail: pisa at cmp.felk.cvut.cz
>>>> Department of Control Engineering FEE CVUT
>>>> Karlovo namesti 13, 121 35, Prague 2
>>>> university: http://control.fel.cvut.cz/
>>>> company: https://www.pikron.com/
>>>> personal: http://cmp.felk.cvut.cz/~pisa
>>>> projects: https://www.openhub.net/accounts/ppisa
>>>> CAN related:http://canbus.pages.fel.cvut.cz/
>>>> Open Technologies Research Education and Exchange Services
>>>> https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home
>>
>>
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