New RISC-V BSP variant (Kendryte K210)

[Alan Cudmore]

Hi,
I have been working on a basic BSP for the Kendryte K210 RISC-V CPU,
and I was wondering if the community members would like me to submit
it.
The Kendryte K210 is a dual core 64 bit RISC-V processor with a wealth
of peripheral I/O, a built-in AI NPU, and 8 Megabytes of on-chip SRAM.
I like it because it is one of the lowest cost RISC-V CPUs available,
and it appears to run RTEMS well.
In addition, my BSP works on the K210 model on the renode.io
simulator. I believe it would work on QEMU, but it is very close to
the rv64imafdc_medany riscv BSP variant.
The changes consist of:
- A new riscv/riscv variant and associated build option files
- A new DTB header, since the DTB is included in the BSP similar to
the polarfire BSP
- Some code to detect the frequency in bspstart.c
- A new header file for the k210
Because the console uses the same sifive uart as the frdme310arty BSP,
I factored that out so the Sifive UART can be used in multiple BSP
variants. It is able to use the existing timer and interrupt code.

In addition to the renode.io simulator, I have run it on the following boards:
- Sipeed MAIX Bit
- Sipeed MAIXduino (arduino form factor board with ESP32)
- Sipeed Grove AI hat for Raspberry Pi

Potential negatives:
- I do not have a BSD licensed device tree source, I created the
device tree binary from the u-boot distribution. Is it OK to just
include the device tree binary (similar to the microblaze)?
- The availability of these boards has not been as good for the last
year or so, but you can still find them at a relatively low cost. The
Sipeed company seems to be focusing on another low cost RISC-V SoC,
which is very interesting as well: The Bouffalo Lab BL808 (example
here:
https://wiki.pine64.org/wiki/Ox64)

Is this worth submitting? I don't want to clutter up the tree with
devices that may become obsolete - we could focus on the upcoming
round of low cost RISC-V SoCs like the BL808.
I don't have a specific application I am using it for, but I used it
as a very inexpensive way to learn RISC-V on a real board. It may be
of some value to integrate additional peripheral support including the
AI NPU.

If anyone is interested, I can submit the patches or even provide a
branch on github.

Thanks,
Alan