[PATCH v2 1/2] microblaze: Add support for libbsd.
Alex White
alex.white at oarcorp.com
Thu Jan 6 21:03:34 UTC 2022
From: Jennifer Averett <jennifer.averett at oarcorp.com>
---
.../microblaze_fpga/dts/microblaze-dtb.c | 962 ++++++++++++++++++
.../microblaze/microblaze_fpga/dts/system.dts | 452 ++++++++
bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c | 21 +
bsps/microblaze/microblaze_fpga/include/bsp.h | 4 +
.../bsps/microblaze/microblaze_fpga/obj.yml | 2 +
5 files changed, 1441 insertions(+)
create mode 100644 bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
create mode 100644 bsps/microblaze/microblaze_fpga/dts/system.dts
create mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
diff --git a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
new file mode 100644
index 0000000000..ad72fac0b8
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
@@ -0,0 +1,962 @@
+/*
+ * Declarations for C structure representing binary file system.dtb
+ *
+ * WARNING: Automatically generated -- do not edit!
+ */
+
+#include <sys/types.h>
+
+const unsigned char system_dtb[] = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5,
+ 0x00, 0x00, 0x1c, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1b,
+ 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c,
+ 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12,
+ 0x00, 0x00, 0x00, 0x26, 0x58, 0x69, 0x6c, 0x69, 0x6e, 0x78, 0x20, 0x4d,
+ 0x69, 0x63, 0x72, 0x6f, 0x42, 0x6c, 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73, 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
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+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x1b,
+ 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c,
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+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x65, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03,
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+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb2,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
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+ 0x70, 0x6f, 0x72, 0x74, 0x2d, 0x6e, 0x75, 0x6d, 0x62, 0x65, 0x72, 0x00,
+ 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x62, 0x61, 0x75, 0x64, 0x72, 0x61, 0x74,
+ 0x65, 0x00, 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x64, 0x61, 0x74, 0x61, 0x2d,
+ 0x62, 0x69, 0x74, 0x73, 0x00, 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6f, 0x64,
+ 0x64, 0x2d, 0x70, 0x61, 0x72, 0x69, 0x74, 0x79, 0x00, 0x78, 0x6c, 0x6e,
+ 0x78, 0x2c, 0x73, 0x2d, 0x61, 0x78, 0x69, 0x2d, 0x61, 0x63, 0x6c, 0x6b,
+ 0x2d, 0x66, 0x72, 0x65, 0x71, 0x2d, 0x68, 0x7a, 0x2d, 0x64, 0x00, 0x78,
+ 0x6c, 0x6e, 0x78, 0x2c, 0x75, 0x73, 0x65, 0x2d, 0x70, 0x61, 0x72, 0x69,
+ 0x74, 0x79, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70,
+ 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65,
+ 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f,
+ 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6b, 0x69,
+ 0x6e, 0x64, 0x2d, 0x6f, 0x66, 0x2d, 0x69, 0x6e, 0x74, 0x72, 0x00, 0x78,
+ 0x6c, 0x6e, 0x78, 0x2c, 0x6e, 0x75, 0x6d, 0x2d, 0x69, 0x6e, 0x74, 0x72,
+ 0x2d, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x73, 0x00, 0x62, 0x6f, 0x6f, 0x74,
+ 0x61, 0x72, 0x67, 0x73, 0x00, 0x73, 0x74, 0x64, 0x6f, 0x75, 0x74, 0x2d,
+ 0x70, 0x61, 0x74, 0x68, 0x00, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65,
+ 0x74, 0x30, 0x00, 0x69, 0x32, 0x63, 0x30, 0x00, 0x73, 0x65, 0x72, 0x69,
+ 0x61, 0x6c, 0x30, 0x00, 0x73, 0x70, 0x69, 0x30, 0x00,
+};
+
+const size_t system_dtb_size = sizeof(system_dtb);
diff --git a/bsps/microblaze/microblaze_fpga/dts/system.dts b/bsps/microblaze/microblaze_fpga/dts/system.dts
new file mode 100644
index 0000000000..587d569f03
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/dts/system.dts
@@ -0,0 +1,452 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "xlnx,microblaze";
+ model = "Xilinx MicroBlaze";
+
+ cpus {
+ #address-cells = <0x1>;
+ #cpus = <0x1>;
+ #size-cells = <0x0>;
+
+ cpu at 0 {
+ bus-handle = <0x1>;
+ clock-frequency = <0x5f5e100>;
+ clocks = <0x2>;
+ compatible = "xlnx,microblaze-11.0";
+ d-cache-baseaddr = <0x80000000>;
+ d-cache-highaddr = <0xffffffff>;
+ d-cache-line-size = <0x10>;
+ d-cache-size = <0x8000>;
+ device_type = "cpu";
+ i-cache-baseaddr = <0x80000000>;
+ i-cache-highaddr = <0xffffffff>;
+ i-cache-line-size = <0x20>;
+ i-cache-size = <0x8000>;
+ interrupt-handle = <0x3>;
+ model = "microblaze,11.0";
+ reg = <0x0>;
+ timebase-frequency = <0x5f5e100>;
+ xlnx,addr-size = <0x20>;
+ xlnx,addr-tag-bits = <0x10>;
+ xlnx,allow-dcache-wr = <0x1>;
+ xlnx,allow-icache-wr = <0x1>;
+ xlnx,area-optimized = <0x0>;
+ xlnx,async-interrupt = <0x1>;
+ xlnx,async-wakeup = <0x3>;
+ xlnx,avoid-primitives = <0x0>;
+ xlnx,base-vectors = <0x0 0x0>;
+ xlnx,branch-target-cache-size = <0x0>;
+ xlnx,cache-byte-size = <0x8000>;
+ xlnx,d-axi = <0x1>;
+ xlnx,d-lmb = <0x1>;
+ xlnx,d-lmb-mon = <0x0>;
+ xlnx,d-lmb-protocol = <0x0>;
+ xlnx,daddr-size = <0x20>;
+ xlnx,data-size = <0x20>;
+ xlnx,dc-axi-mon = <0x0>;
+ xlnx,dcache-addr-tag = <0x10>;
+ xlnx,dcache-always-used = <0x1>;
+ xlnx,dcache-byte-size = <0x8000>;
+ xlnx,dcache-data-width = <0x0>;
+ xlnx,dcache-force-tag-lutram = <0x0>;
+ xlnx,dcache-line-len = <0x4>;
+ xlnx,dcache-use-writeback = <0x0>;
+ xlnx,dcache-victims = <0x0>;
+ xlnx,debug-counter-width = <0x20>;
+ xlnx,debug-enabled = <0x1>;
+ xlnx,debug-event-counters = <0x5>;
+ xlnx,debug-external-trace = <0x0>;
+ xlnx,debug-interface = <0x0>;
+ xlnx,debug-latency-counters = <0x1>;
+ xlnx,debug-profile-size = <0x0>;
+ xlnx,debug-trace-async-reset = <0x0>;
+ xlnx,debug-trace-size = <0x2000>;
+ xlnx,div-zero-exception = <0x1>;
+ xlnx,dp-axi-mon = <0x0>;
+ xlnx,dynamic-bus-sizing = <0x0>;
+ xlnx,ecc-use-ce-exception = <0x0>;
+ xlnx,edge-is-positive = <0x1>;
+ xlnx,enable-discrete-ports = <0x0>;
+ xlnx,endianness = <0x1>;
+ xlnx,fault-tolerant = <0x0>;
+ xlnx,fpu-exception = <0x1>;
+ xlnx,freq = <0x5f5e100>;
+ xlnx,fsl-exception = <0x0>;
+ xlnx,fsl-links = <0x0>;
+ xlnx,i-axi = <0x0>;
+ xlnx,i-lmb = <0x1>;
+ xlnx,i-lmb-mon = <0x0>;
+ xlnx,i-lmb-protocol = <0x0>;
+ xlnx,iaddr-size = <0x20>;
+ xlnx,ic-axi-mon = <0x0>;
+ xlnx,icache-always-used = <0x1>;
+ xlnx,icache-data-width = <0x0>;
+ xlnx,icache-force-tag-lutram = <0x0>;
+ xlnx,icache-line-len = <0x8>;
+ xlnx,icache-streams = <0x1>;
+ xlnx,icache-victims = <0x8>;
+ xlnx,ill-opcode-exception = <0x1>;
+ xlnx,imprecise-exceptions = <0x0>;
+ xlnx,instr-size = <0x20>;
+ xlnx,interconnect = <0x2>;
+ xlnx,interrupt-is-edge = <0x0>;
+ xlnx,interrupt-mon = <0x0>;
+ xlnx,ip-axi-mon = <0x0>;
+ xlnx,lmb-data-size = <0x20>;
+ xlnx,lockstep-master = <0x0>;
+ xlnx,lockstep-select = <0x0>;
+ xlnx,lockstep-slave = <0x0>;
+ xlnx,mmu-dtlb-size = <0x4>;
+ xlnx,mmu-itlb-size = <0x2>;
+ xlnx,mmu-privileged-instr = <0x0>;
+ xlnx,mmu-tlb-access = <0x3>;
+ xlnx,mmu-zones = <0x2>;
+ xlnx,num-sync-ff-clk = <0x2>;
+ xlnx,num-sync-ff-clk-debug = <0x2>;
+ xlnx,num-sync-ff-clk-irq = <0x1>;
+ xlnx,num-sync-ff-dbg-clk = <0x1>;
+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
+ xlnx,number-of-pc-brk = <0x2>;
+ xlnx,number-of-rd-addr-brk = <0x1>;
+ xlnx,number-of-wr-addr-brk = <0x1>;
+ xlnx,opcode-0x0-illegal = <0x1>;
+ xlnx,optimization = <0x0>;
+ xlnx,pc-width = <0x20>;
+ xlnx,piaddr-size = <0x20>;
+ xlnx,pvr = <0x2>;
+ xlnx,pvr-user1 = <0x0>;
+ xlnx,pvr-user2 = <0x0>;
+ xlnx,reset-msr = <0x0>;
+ xlnx,reset-msr-bip = <0x0>;
+ xlnx,reset-msr-dce = <0x0>;
+ xlnx,reset-msr-ee = <0x0>;
+ xlnx,reset-msr-eip = <0x0>;
+ xlnx,reset-msr-ice = <0x0>;
+ xlnx,reset-msr-ie = <0x0>;
+ xlnx,sco = <0x0>;
+ xlnx,trace = <0x0>;
+ xlnx,unaligned-exceptions = <0x1>;
+ xlnx,use-barrel = <0x1>;
+ xlnx,use-branch-target-cache = <0x0>;
+ xlnx,use-config-reset = <0x0>;
+ xlnx,use-dcache = <0x1>;
+ xlnx,use-div = <0x1>;
+ xlnx,use-ext-brk = <0x0>;
+ xlnx,use-ext-nm-brk = <0x0>;
+ xlnx,use-extended-fsl-instr = <0x0>;
+ xlnx,use-fpu = <0x1>;
+ xlnx,use-hw-mul = <0x2>;
+ xlnx,use-icache = <0x1>;
+ xlnx,use-interrupt = <0x2>;
+ xlnx,use-mmu = <0x3>;
+ xlnx,use-msr-instr = <0x1>;
+ xlnx,use-non-secure = <0x0>;
+ xlnx,use-pcmp-instr = <0x1>;
+ xlnx,use-reorder-instr = <0x1>;
+ xlnx,use-stack-protection = <0x0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ clk_cpu at 0 {
+ #clock-cells = <0x0>;
+ clock-frequency = <0x5f5e100>;
+ clock-output-names = "clk_cpu";
+ compatible = "fixed-clock";
+ reg = <0x0>;
+ phandle = <0x2>;
+ };
+
+ clk_bus_0 at 1 {
+ #clock-cells = <0x0>;
+ clock-frequency = <0x5f5e100>;
+ clock-output-names = "clk_bus_0";
+ compatible = "fixed-clock";
+ reg = <0x1>;
+ phandle = <0x7>;
+ };
+ };
+
+ amba_pl {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "simple-bus";
+ ranges;
+ phandle = <0x1>;
+
+ ethernet at 40c00000 {
+ axistream-connected = <0x4>;
+ axistream-control-connected = <0x4>;
+ clock-frequency = <0x5f5e100>;
+ compatible = "xlnx,axi-ethernet-7.2", "xlnx,axi-ethernet-1.00.a";
+ device_type = "network";
+ interrupt-names = "mac_irq", "interrupt";
+ interrupt-parent = <0x3>;
+ interrupts = <0x4 0x0 0x5 0x2>;
+ local-mac-address = [00 0a 35 00 22 01];
+ phy-handle = <0x5>;
+ phy-mode = "sgmii";
+ reg = <0x40c00000 0x40000>;
+ xlnx = <0x0>;
+ xlnx,axiliteclkrate = <0x0>;
+ xlnx,axisclkrate = <0x0>;
+ xlnx,channel-ids = <0x1>;
+ xlnx,clockselection = <0x0>;
+ xlnx,enableasyncsgmii = <0x0>;
+ xlnx,gt-type = <0x0>;
+ xlnx,gtinex = <0x0>;
+ xlnx,gtlocation = <0x0>;
+ xlnx,gtrefclksrc = <0x0>;
+ xlnx,include-dre;
+ xlnx,instantiatebitslice0 = <0x0>;
+ xlnx,num-queues = [00 01];
+ xlnx,phy-type = <0x4>;
+ xlnx,phyaddr = <0x1>;
+ xlnx,phyrst-board-interface-dummy-port = <0x0>;
+ xlnx,rable = <0x0>;
+ xlnx,rxcsum = <0x0>;
+ xlnx,rxlane0-placement = <0x0>;
+ xlnx,rxlane1-placement = <0x0>;
+ xlnx,rxmem = <0x1000>;
+ xlnx,rxnibblebitslice0used = <0x0>;
+ xlnx,tx-in-upper-nibble = <0x1>;
+ xlnx,txcsum = <0x0>;
+ xlnx,txlane0-placement = <0x0>;
+ xlnx,txlane1-placement = <0x0>;
+ phandle = <0x6>;
+ dmas = <&dma 0
+ &dma 1>;
+ dma-names = "rx", "tx";
+ memory-region = <&dma_reserved>;
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ phy at 1 {
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ phandle = <0x5>;
+ };
+ };
+ };
+
+ dma: dma at 41e00000 {
+ #dma-cells = <0x1>;
+ axistream-connected = <0x6>;
+ axistream-control-connected = <0x6>;
+ clock-frequency = <0x5f5e100>;
+ clock-names = "s_axi_lite_aclk";
+ clocks = <0x7>;
+ compatible = "xlnx,eth-dma";
+ interrupt-names = "mm2s_introut", "s2mm_introut";
+ interrupt-parent = <0x3>;
+ interrupts = <0x6 0x2 0x7 0x2>;
+ reg = <0x41e00000 0x10000>;
+ xlnx,addrwidth = [20];
+ xlnx,include-dre;
+ xlnx,num-queues = [00 01];
+ phandle = <0x4>;
+ };
+
+ gpio at 40000000 {
+ #gpio-cells = <0x3>;
+ clock-frequency = <0x5f5e100>;
+ clock-names = "s_axi_aclk";
+ clocks = <0x7>;
+ compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
+ gpio-controller;
+ reg = <0x40000000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x1>;
+ xlnx,dout-default = <0x0>;
+ xlnx,dout-default-2 = <0x0>;
+ xlnx,gpio-width = <0x4>;
+ xlnx,gpio2-width = <0x8>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x1>;
+ xlnx,tri-default = <0xffffffff>;
+ xlnx,tri-default-2 = <0xffffffff>;
+ };
+
+ gpio at 40010000 {
+ #gpio-cells = <0x3>;
+ clock-frequency = <0x5f5e100>;
+ clock-names = "s_axi_aclk";
+ clocks = <0x7>;
+ compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
+ gpio-controller;
+ reg = <0x40010000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x1>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x0>;
+ xlnx,dout-default-2 = <0x0>;
+ xlnx,gpio-width = <0x5>;
+ xlnx,gpio2-width = <0x3>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x1>;
+ xlnx,tri-default = <0xffffffff>;
+ xlnx,tri-default-2 = <0xffffffff>;
+ };
+
+ i2c at 40800000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-frequency = <0x5f5e100>;
+ clocks = <0x7>;
+ compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a";
+ interrupt-names = "iic2intc_irpt";
+ interrupt-parent = <0x3>;
+ interrupts = <0x2 0x2>;
+ reg = <0x40800000 0x10000>;
+
+ i2c-mux at 75 {
+ compatible = "nxp,pca9544";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ reg = <0x75>;
+
+ i2c at 3 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ reg = <0x3>;
+
+ eeprom at 54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ };
+ };
+
+ axi_quad_spi at 44a00000 {
+ bits-per-word = <0x8>;
+ compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
+ fifo-size = <0x100>;
+ interrupt-names = "ip2intc_irpt";
+ interrupt-parent = <0x3>;
+ interrupts = <0x3 0x0>;
+ num-cs = <0x2>;
+ reg = <0x44a00000 0x10000>;
+ xlnx,num-ss-bits = <0x2>;
+ xlnx,spi-mode = <0x2>;
+ xlnx,startup-block;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ flash at 0 {
+ compatible = "n25q512a";
+ reg = <0x0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ spi-tx-bus-width = <0x1>;
+ spi-rx-bus-width = <0x4>;
+ spi-max-frequency = <0x2faf080>;
+
+ partition at 0 {
+ label = "fpga";
+ reg = <0x0 0x1000000>;
+ };
+
+ partition at 1 {
+ label = "boot";
+ reg = <0x1000000 0x180000>;
+ };
+
+ partition at 2 {
+ label = "bootenv";
+ reg = <0x1180000 0x40000>;
+ };
+
+ partition at 3 {
+ label = "kernel";
+ reg = <0x11c0000 0xc00000>;
+ };
+ };
+ };
+
+ timer at 41c00000 {
+ clock-frequency = <0x5f5e100>;
+ clocks = <0x7>;
+ compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a";
+ interrupt-names = "interrupt";
+ interrupt-parent = <0x3>;
+ interrupts = <0x0 0x2>;
+ reg = <0x41c00000 0x10000>;
+ xlnx,count-width = <0x20>;
+ xlnx,gen0-assert = <0x1>;
+ xlnx,gen1-assert = <0x1>;
+ xlnx,one-timer-only = <0x0>;
+ xlnx,trig0-assert = <0x1>;
+ xlnx,trig1-assert = <0x1>;
+ };
+
+ serial at 40600000 {
+ clock-frequency = <0x5f5e100>;
+ clocks = <0x7>;
+ compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
+ current-speed = <0x1c200>;
+ device_type = "serial";
+ interrupt-names = "interrupt";
+ interrupt-parent = <0x3>;
+ interrupts = <0x1 0x0>;
+ port-number = <0x0>;
+ reg = <0x40600000 0x10000>;
+ xlnx,baudrate = <0x1c200>;
+ xlnx,data-bits = <0x8>;
+ xlnx,odd-parity = <0x0>;
+ xlnx,s-axi-aclk-freq-hz-d = "100.0";
+ xlnx,use-parity = <0x0>;
+ };
+
+ ddr4 at 80000000 {
+ compatible = "xlnx,ddr4-2.2";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ interrupt-controller at 41200000 {
+ #interrupt-cells = <0x2>;
+ compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
+ interrupt-controller;
+ reg = <0x41200000 0x10000>;
+ xlnx,kind-of-intr = <0x1a>;
+ xlnx,num-intr-inputs = <0x8>;
+ phandle = <0x3>;
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyUL0,115200 earlycon root=/dev/ram0 rw";
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = "/amba_pl/ethernet at 40c00000";
+ i2c0 = "/amba_pl/i2c at 40800000";
+ serial0 = "/amba_pl/serial at 40600000";
+ spi0 = "/amba_pl/axi_quad_spi at 44a00000";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ phandle = <0x8>;
+ };
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma_reserved: buffer at 10000000 {
+ reg = <0x10000000 0x4000000>;
+ };
+ };
+};
diff --git a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
new file mode 100644
index 0000000000..e92f9e466e
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
@@ -0,0 +1,21 @@
+/*
+ * COPYRIGHT (c) 2021.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+
+const void *bsp_fdt_get(void)
+{
+ return system_dtb;
+}
+
+uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
+{
+ return intr[0];
+}
+
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h b/bsps/microblaze/microblaze_fpga/include/bsp.h
index e83e632553..49918c3353 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -46,6 +46,10 @@ extern "C" {
#include <rtems.h>
+#define BSP_FDT_IS_SUPPORTED
+extern const unsigned char system_dtb[];
+extern const size_t system_dtb_size;
+
#ifdef __cplusplus
}
#endif
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
index a211456e1d..889a8de5a3 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
@@ -23,6 +23,8 @@ source:
- bsps/microblaze/microblaze_fpga/clock/clock.c
- bsps/microblaze/microblaze_fpga/console/console-io.c
- bsps/microblaze/microblaze_fpga/console/debug-io.c
+- bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
+- bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
- bsps/microblaze/microblaze_fpga/irq/irq.c
- bsps/microblaze/microblaze_fpga/start/_exception_handler.S
- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S
--
2.30.2
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