[PATCH 2/2] aarch64/versal: Support DDRMC0 region 0 and 1
Kinsey Moore
kinsey.moore at oarcorp.com
Tue Jul 26 13:47:33 UTC 2022
On 7/22/2022 01:35, chrisj at rtems.org wrote:
> From: Chris Johns <chrisj at rtems.org>
>
> - Support DDRMC0 region 0 up to 2G in size
>
> - Support DDRMC0 region 1 with DDR memory greater than 2G
> up to the DDRMC0 max amount
>
> - Extend the heap with region 1's memory
>
> Closes #4684
> ---
> bsps/aarch64/xilinx-versal/include/bsp.h | 9 ++++
> bsps/aarch64/xilinx-versal/start/bspstart.c | 2 +
> .../aarch64/xilinx-versal/start/bspstartmmu.c | 36 ++++++++++++++
> .../aarch64/xilinx-versal/linkcmds_lp64.yml | 48 +++++++++++++++++--
> 4 files changed, 90 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/aarch64/xilinx-versal/include/bsp.h b/bsps/aarch64/xilinx-versal/include/bsp.h
> index 2017e10ade..0bd93f28bc 100644
> --- a/bsps/aarch64/xilinx-versal/include/bsp.h
> +++ b/bsps/aarch64/xilinx-versal/include/bsp.h
> @@ -47,6 +47,7 @@
> #ifndef ASM
>
> #include <bsp/default-initial-extension.h>
> +#include <bsp/linker-symbols.h>
> #include <bsp/start.h>
>
> #include <rtems.h>
> @@ -61,6 +62,14 @@ extern "C" {
>
> #define BSP_RESET_SMC
>
> +/*
> + * DDRMC mapping
> + */
> +LINKER_SYMBOL(bsp_r0_ram_base)
> +LINKER_SYMBOL(bsp_r0_ram_end)
> +LINKER_SYMBOL(bsp_r1_ram_base)
> +LINKER_SYMBOL(bsp_r1_ram_end)
> +
> /**
> * @brief Versal specific set up of the MMU.
> *
> diff --git a/bsps/aarch64/xilinx-versal/start/bspstart.c b/bsps/aarch64/xilinx-versal/start/bspstart.c
> index 2f0048ddf3..86b3024dd2 100644
> --- a/bsps/aarch64/xilinx-versal/start/bspstart.c
> +++ b/bsps/aarch64/xilinx-versal/start/bspstart.c
> @@ -38,6 +38,8 @@
> #include <bsp/irq-generic.h>
> #include <bsp/linker-symbols.h>
>
> +#include <bsp/aarch64-mmu.h>
> +
Unnecessary include? Nothing referencing MMU functionality was added to
this file.
> void bsp_start( void )
> {
> bsp_interrupt_initialize();
> diff --git a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
> index 5949111d0d..c2fcd62c9f 100644
> --- a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
> +++ b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
> @@ -38,6 +38,9 @@
> #include <bsp/aarch64-mmu.h>
> #include <libcpu/mmu-vmsav8-64.h>
>
> +#include <rtems/malloc.h>
> +#include <rtems/sysinit.h>
> +
> BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
> versal_mmu_config_table[] = {
> AARCH64_MMU_DEFAULT_SECTIONS,
> @@ -57,6 +60,24 @@ versal_mmu_config_table[] = {
> .begin = 0xff000000U,
> .end = 0xffc00000U,
> .flags = AARCH64_MMU_DEVICE
> + }, { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
> + .begin = (uintptr_t) bsp_r1_ram_base,
> + .end = (uintptr_t) bsp_r1_ram_end,
> + .flags = AARCH64_MMU_DATA_RW_CACHED
> + }
> +};
> +
> +/*
> + * Create an MMU table to get the R1 base and end. This avoids
> + * relocation errors as the R1 addresses are in the upper A64 address
> + * space.
> + */
> +static const aarch64_mmu_config_entry
> +bsp_r1_region[] = {
> + { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
> + .begin = (uintptr_t) bsp_r1_ram_base,
> + .end = (uintptr_t) bsp_r1_ram_end,
> + .flags = 0
Is there a reason this data is being repeated over using the data
already in the table above? Even if repeating the data makes it easier,
use of this data structure is a little confusing since it's not being
fed into the MMU routines and setting flags here is unnecessary.
> }
> };
>
> @@ -78,3 +99,18 @@ versal_setup_mmu_and_cache( void )
>
> aarch64_mmu_enable();
> }
> +
> +void bsp_r1_heap_extend(void);
> +void bsp_r1_heap_extend(void)
> +{
> + const aarch64_mmu_config_entry* r1 = &bsp_r1_region[0];
> + if (false && r1->begin != r1->end) {
> + rtems_heap_extend((void*) r1->begin, r1->end - r1->begin);
> + }
> +}
> +
> +RTEMS_SYSINIT_ITEM(
> + bsp_r1_heap_extend,
> + RTEMS_SYSINIT_MALLOC,
> + RTEMS_SYSINIT_ORDER_LAST
> +);
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> index 76c0220f0e..ca353d2662 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> @@ -4,7 +4,8 @@ content: |
> /* SPDX-License-Identifier: BSD-2-Clause */
>
> /*
> - * Copyright (C) 2021 Gedare Bloom <gedare at rtems.org>
> + * Copyright (C) 2021 Gedare Bloom <gedare at rtems.org>
> + * Copyright (C) 2022 Chris Johns <chrisj at rtems.org>
> *
> * Redistribution and use in source and binary forms, with or without
> * modification, are permitted provided that the following conditions
> @@ -28,10 +29,41 @@ content: |
> * POSSIBILITY OF SUCH DAMAGE.
> */
>
> + /*
> + * The RAM supports 32G of DDR4 or LPDDR memory using DDRMC0.
> + *
> + * The DDR Conroller (DDRC) has two regions R0 and R1. R0 is
> + * in the A32 address space and R1 is in the A64 address space.
> + */
> + DDRMC0_REGION_0_BASE = 0x00000000000;
> + DDRMC0_REGION_0_LENGTH = 0x00080000000;
> + DDRMC0_REGION_1_BASE = 0x00800000000;
> + DDRMC0_REGION_1_LENGTH = 0x01000000000;
> +
> + BSP_RAM_BASE = ${BSP_XILINX_VERSAL_RAM_BASE};
> +
> + BSP_R0_RAM_BASE = DDRMC0_REGION_0_BASE;
> + BSP_R0_RAM_LENGTH =
> + ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
> + DDRMC0_REGION_0_LENGTH - BSP_RAM_BASE : ${BSP_XILINX_VERSAL_RAM_LENGTH};
> + BSP_R0_RAM_END = BSP_RAM_BASE + BSP_R0_RAM_LENGTH;
> +
> + BSP_R1_RAM_BASE = DDRMC0_REGION_1_BASE;
> + BSP_R1_RAM_LENGTH =
> + ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
> + ${BSP_XILINX_VERSAL_RAM_LENGTH} - DDRMC0_REGION_0_LENGTH : 0;
> +
> + AARCH64_MMU_TT_PAGES_SIZE = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES};
> +
> MEMORY {
> - RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> - NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> - RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
> + RAM : ORIGIN = BSP_RAM_BASE + ${BSP_XILINX_VERSAL_LOAD_OFFSET},
> + LENGTH = BSP_R0_RAM_LENGTH - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - AARCH64_MMU_TT_PAGES_SIZE
> + RAM1 : ORIGIN = BSP_R1_RAM_BASE,
> + LENGTH = BSP_R1_RAM_LENGTH
> + NOCACHE : ORIGIN = BSP_RAM_BASE + BSP_R0_RAM_LENGTH - AARCH64_MMU_TT_PAGES_SIZE - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
> + LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> + RAM_MMU : ORIGIN = BSP_R0_RAM_END - AARCH64_MMU_TT_PAGES_SIZE,
> + LENGTH = AARCH64_MMU_TT_PAGES_SIZE
> }
>
> REGION_ALIAS ("REGION_START", RAM);
> @@ -58,6 +90,11 @@ content: |
>
> bsp_vector_table_in_start_section = 1;
>
> + bsp_r0_ram_base = DDRMC0_REGION_0_BASE;
> + bsp_r0_ram_end = ORIGIN (RAM) + LENGTH (RAM);
> + bsp_r1_ram_base = ORIGIN (RAM1);
> + bsp_r1_ram_end = ORIGIN (RAM1) + LENGTH (RAM1);
> +
> bsp_translation_table_base = ORIGIN (RAM_MMU);
> bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
>
> @@ -66,7 +103,8 @@ content: |
>
> INCLUDE linkcmds.base
> copyrights:
> -- Copyright (C) 2021 Gedare Bloom <gedare at rtems.org>
> +- Copyright (C) 2021 Gedare Bloom <gedare at rtems.org>
> +- Copyright (C) 2022 Chris Johns <chrisj at rtems.org>
> enabled-by: true
> install-path: ${BSP_LIBDIR}
> links: []
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