[PATCH] irq/arm-gicv3.h: Enable interrupt groups 0 and 1

[Sebastian Huber]

The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets.  Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers.  This fixes the build for the
AArch32 target.
---
 bsps/include/dev/irq/arm-gicv3.h | 23 ++++++-----------------
 1 file changed, 6 insertions(+), 17 deletions(-)

diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a79368ebdf..7db7bad034 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -116,9 +116,11 @@ extern "C" {
 #else /* ARM_MULTILIB_ARCH_V4 */
 
 /* AArch64 GICv3 registers are not named in GCC */
-#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
-#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
+#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"
+#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"
 #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
+#define ICC_IGRPEN0 ICC_IGRPEN0_EL1
+#define ICC_IGRPEN1 ICC_IGRPEN1_EL1
 #define ICC_PMR     "S3_0_C4_C6_0, %0"
 #define ICC_EOIR1   "S3_0_C12_C12_1, %0"
 #define ICC_SRE     "S3_0_C12_C12_5, %0"
@@ -300,20 +302,6 @@ static void gicv3_init_dist(volatile gic_dist *dist)
   }
 }
 
-/*
- * A better way to access these registers than special opcodes
- */
-#define isb() __asm __volatile("isb" : : : "memory")
-
-#define  WRITE_SPECIALREG(reg, _val)                                    \
-  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
-
-#define  gic_icc_write(reg, val)            \
-do {                                        \
-  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
-  isb();                                    \
-} while (0)
-
 static void gicv3_init_cpu_interface(uint32_t cpu_index)
 {
   uint32_t sre_value = 0x7;
@@ -335,7 +323,8 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
   }
 
   /* Enable interrupt groups 0 and 1 */
-  gic_icc_write(IGRPEN1, 1);
+  WRITE_SR(ICC_IGRPEN0, 0x1);
+  WRITE_SR(ICC_IGRPEN1, 0x1);
   WRITE_SR(ICC_CTLR, 0x0);
 }
 
-- 
2.35.3