[PATCH 2/7] bsps/arm: disable cache operations on Cortex-M4

[Karel Gardas]

On 5/23/22 14:45, Sebastian Huber wrote:
> On 16/05/2022 16:02, Karel Gardas wrote:
>> ---
>>   bsps/arm/shared/cache/cache-v7m.c | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/bsps/arm/shared/cache/cache-v7m.c 
>> b/bsps/arm/shared/cache/cache-v7m.c
>> index f5a9e208e5..100d38765f 100644
>> --- a/bsps/arm/shared/cache/cache-v7m.c
>> +++ b/bsps/arm/shared/cache/cache-v7m.c
>> @@ -9,21 +9,25 @@
>>   #include <rtems.h>
>>   #include <chip.h>
>> +#if __CORTEX_M != 0x04U
>>   #define CPU_DATA_CACHE_ALIGNMENT 32
>>   #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
>>   #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
>> +#endif
> 
> This is file for Cortex-M7. Maybe use __CORTEX_M == 0x07U.

This is a misunderstanding on my side. I've thought this was for armv7m 
and not for cotex-m7 specifically.

> You can probably use a single #if with an #endif before the cachimpl.h 
> include.

Indeed, I took it even a bit further and use nochache.c for m4 variant. 
Also I took your advice and use __CORTEX_M comparison for disabling code 
enabling cache and MPU in bspstarthook.c

Thanks for the review!
Karel