bsp/riscv: Store/AMO address misaligned trap occured

[Gedare Bloom]

Check what is the address of .Lsecondary_processor_go
and confirm it is 8-byte aligned.

The patch you indicated with the `.option norelax` could have an
effect on alignment, but it should be the case that the alignment is
ensured (rather than violated).

On Thu, Nov 3, 2022 at 12:37 AM <Padmarao.Begari at microchip.com> wrote:
>
> > On Thu, 2022-11-03 at 05:40 +0000, Padmarao.Begari at microchip.com
> wrote:
> > Hi Gedare,
> > > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
> > >
> > > t0 contains the address of .Lsecondary_processor_go
> > >
> > > start.S has:
> > > ```asm
> > > #if __riscv_xlen == 32
> > >   .align  2
> > > #elif __riscv_xlen == 64
> > >   .align  3
> > > #endif
> > >
> > > .Lsecondary_processor_go:
> > > ```
> > > Can you confirm the value of __riscv_xlen is properly defined to 64
> > > for the PolarFire?
> > >
> > No, the value of __riscv_xlen is showing 32(config.log) instead of 64
> > for PolarFire SoC and other 64-bit RISCV BSPs.
> >
> Ignore previous one "the value of __riscv_xlen is showing
> 32(config.log)"
>
> The __riscv_xlen is 64 for PolarFire SoC, have seen while executing the
> rtems on the board.
>
> > Regards
> > Padmarao
> > > On Wed, Nov 2, 2022 at 12:40 AM <Padmarao.Begari at microchip.com>
> > > wrote:
> > > > Hi Sebastian,
> > > >
> > > > The "Store/AMO address misaligned" trap occured in the "start.S"
> > > >  at "amoswap.w zero, zero, 0(t0)" while testing the sample
> > > >  application with the latest RTEMS master for RISC-V on
> > > > the Microchip PolarFire SoC.
> > > >
> > > > The trap occured after this  89ba2a98/rtems latest commit for
> > > > riscv
> > > > (bsps/riscv: Workaround for sporadic linker issues).
> > > >
> > > > Regards
> > > > Padmarao
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