bsp/riscv: Store/AMO address misaligned trap occured

Padmarao.Begari at microchip.com Padmarao.Begari at microchip.com
Mon Nov 7 05:33:38 UTC 2022


Hi Sebastian,

> On Fri, 2022-11-04 at 14:03 +0100, Sebastian Huber wrote:
> On 04/11/2022 10:49, Sebastian Huber wrote:
> > On 04/11/2022 10:44, Padmarao.Begari at microchip.com wrote:
> > > Hi Sebastian,
> > > 
> > > > On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote:
> > > > 
> > > > On 03/11/2022 06:40,Padmarao.Begari at microchip.com  wrote:
> > > > > > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
> > > > > > 
> > > > > > t0 contains the address of .Lsecondary_processor_go
> > > > > > 
> > > > > > start.S has:
> > > > > > ```asm
> > > > > > #if __riscv_xlen == 32
> > > > > >     .align  2
> > > > > > #elif __riscv_xlen == 64
> > > > > >     .align  3
> > > > > > #endif
> > > > > > 
> > > > > > .Lsecondary_processor_go:
> > > > > > ```
> > > > > > Can you confirm the value of __riscv_xlen is properly
> > > > > > defined to
> > > > > > 64
> > > > > > for the PolarFire?
> > > > > > 
> > > > > No, the value of __riscv_xlen is showing 32(config.log)
> > > > > instead of
> > > > > 64
> > > > > for PolarFire SoC and other 64-bit RISCV BSPs.
> > > > This is a compiler built-in define.  It doesn't matter what is
> > > > in the
> > > > config.log. What matters is that the compiler is invoked with
> > > > the
> > > > right
> > > > options. In my build this looks all right.
> > > > 
> > > > What is the value of t0 in
> > > > 
> > > > amoswap.w zero, zero, 0(t0)
> > > > 
> > > > ?
> > > > 
> > > The "t0" value is 0x10000000ae
> > 
> > Ok, is this the address of .Lsecondary_processor_go?
> > 
> > It is a value > 4GiB. I am not sure how such a value is loaded
> > through
> > la or lla.
> 
> It seems that the .align directive is broken in the assembler. I
> checked
> in b4ffaa7cdcce4fedb857f6b8342301f8dde65c78 as a workaround. Could
> you
> please test this commit?
> 

I have tested it and working fine.

Regards
Padmarao
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