[PATCH 04/10] bsps/riscv: Improve bsp_interrupt_vector_disable()

Sebastian Huber sebastian.huber at embedded-brains.de
Wed Nov 9 16:09:14 UTC 2022


Add support for hart-specific software and timer interrupts.
---
 bsps/riscv/riscv/irq/irq.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 3bce33ae13..238cb7f62a 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -500,8 +500,16 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
     }
 
     rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
+    return RTEMS_SUCCESSFUL;
+  }
+
+  if (vector == RISCV_INTERRUPT_VECTOR_TIMER) {
+    clear_csr(mie, MIP_MTIP);
+    return RTEMS_SUCCESSFUL;
   }
 
+  _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE);
+  clear_csr(mie, MIP_MSIP);
   return RTEMS_SUCCESSFUL;
 }
 
-- 
2.35.3



More information about the devel mailing list