[PATCH] aarch64/versal: Add UART interrupt support

[Chris Johns]

On 22/11/22 6:01 pm, Sebastian Huber wrote:
> Hello Chris,
> 
> On 22/11/2022 03:03, chrisj at rtems.org wrote:
>> +static void versal_uart_write_support(
>> +  rtems_termios_device_context *base,
>> +  const char *buf,
>> +  size_t len
>> +)
>> +{
>> +#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
>> +  versal_uart_context *ctx = (versal_uart_context *) base;
>> +  volatile versal_uart *regs = ctx->regs;
>> +
>> +  if (len > 0) {
>> +    rtems_interrupt_lock_context lock_context;
>> +    size_t len_remaining = len;
>> +    const char *p = &buf[0];
>> +    rtems_interrupt_lock_acquire(&ctx->interrupt_lock, &lock_context);
> 
> you don't need an extra interrupt lock. The rtems_termios_device_context already
> contains an interrupt lock, see rtems_termios_device_lock_acquire(). This lock
> is held while the write support handler is called.
> 

Thanks for the review and I will remove. The driver took a while to isolate a
possible issue in the hardware. I have raised this with Xilinx. The TX will not
start with the single character write. I needed to write past the trigger point.

I think this driver could be moved to shared as the hardware is based on the ARM
IP for the PL011 UART. I wanted to get the chcanges in and used before
considering moving it. Xilinx has changed the IP a little which is a shame.

Chris