[PATCH] bsps/microblaze: Add device tree support to GPIO driver
Alex White
alex.white at oarcorp.com
Wed Apr 19 14:57:19 UTC 2023
This removes the ability to statically configure a second GPIO device.
Instead, any number of GPIO devices can be configured using the device
tree. If a device tree is not used, a single GPIO device can still be
configured statically.
---
.../microblaze_fpga/gpio/microblaze-gpio.c | 188 ++++++++++++------
.../include/bsp/microblaze-gpio.h | 91 ++++-----
.../bsps/microblaze/microblaze_fpga/grp.yml | 12 +-
.../microblaze_fpga/optgpio2dualchannel.yml | 16 --
.../microblaze_fpga/optgpio2enable.yml | 17 --
.../microblaze_fpga/optgpio2interrupt.yml | 16 --
.../microblaze_fpga/optgpio2irq.yml | 18 --
...optgpio2baseaddress.yml => optmaxgpio.yml} | 13 +-
8 files changed, 181 insertions(+), 190 deletions(-)
delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
rename spec/build/bsps/microblaze/microblaze_fpga/{optgpio2baseaddress.yml => optmaxgpio.yml} (54%)
diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
index 9025840e32..b8563b1472 100644
--- a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -34,52 +34,87 @@
*/
#include <assert.h>
+#include <rtems/sysinit.h>
+#include <bspopts.h>
#include <bsp/fatal.h>
#include <bsp/microblaze-gpio.h>
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include <libfdt.h>
+#include <bsp/fdt.h>
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-Microblaze_GPIO_context gpio1_context = {
- .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
- .is_dual = true,
-#else
- .is_dual = false,
-#endif
- .irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
- .has_interrupts = true
-#else
- .has_interrupts = false
-#endif
-};
-
-#if BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-Microblaze_GPIO_context gpio2_context = {
- .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO2_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
- .is_dual = true,
-#else
- .is_dual = false,
-#endif
- .irq = BSP_MICROBLAZE_FPGA_GPIO2_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
- .has_interrupts = true
+static Microblaze_GPIO_context gpio_contexts[BSP_MICROBLAZE_FPGA_MAX_GPIO];
+
+static void microblaze_gpio_initialize( void )
+{
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+ const char* compatible = "xlnx,xps-gpio-1.00.a";
+ const void *fdt = bsp_fdt_get();
+ int node = fdt_node_offset_by_compatible( fdt, -1, compatible );
+ int index = 0;
+
+ /* Initialize up to BSP_MICROBLAZE_FPGA_MAX_GPIO GPIO contexts. */
+ while ( node != -FDT_ERR_NOTFOUND && index < BSP_MICROBLAZE_FPGA_MAX_GPIO ) {
+ const uint32_t *prop;
+
+ prop = fdt_getprop( fdt, node, "reg", NULL );
+ if ( prop != NULL ) {
+ gpio_contexts[index].regs =
+ (Microblaze_GPIO_registers *) fdt32_to_cpu( prop[0] );
+ }
+
+ prop = fdt_getprop( fdt, node, "xlnx,is-dual", NULL );
+ if ( prop != NULL ) {
+ gpio_contexts[index].is_dual =
+ fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+ }
+
+ prop = fdt_getprop( fdt, node, "xlnx,interrupt-present", NULL );
+ if ( prop != NULL ) {
+ gpio_contexts[index].has_interrupts =
+ fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+ }
+
+ if ( gpio_contexts[index].has_interrupts ) {
+ prop = fdt_getprop( fdt, node, "interrupts", NULL );
+ if ( prop != NULL ) {
+ gpio_contexts[index].irq = fdt32_to_cpu( prop[0] );
+ }
+ }
+
+ node = fdt_node_offset_by_compatible( fdt, node, compatible );
+ index++;
+ }
#else
- .has_interrupts = false
-#endif
-};
-#endif
+ gpio_contexts[0].regs =
+ (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE;
+ gpio_contexts[0].is_dual = BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL;
+ gpio_contexts[0].irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ;
+ gpio_contexts[0].has_interrupts = BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT;
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+}
+
+RTEMS_SYSINIT_ITEM(
+ microblaze_gpio_initialize,
+ RTEMS_SYSINIT_DEVICE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE
+);
void microblaze_gpio_set_data_direction(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -90,10 +125,13 @@ void microblaze_gpio_set_data_direction(
}
uint32_t microblaze_gpio_get_data_direction(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -106,10 +144,13 @@ uint32_t microblaze_gpio_get_data_direction(
}
uint32_t microblaze_gpio_discrete_read(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -122,11 +163,14 @@ uint32_t microblaze_gpio_discrete_read(
}
void microblaze_gpio_discrete_write(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -137,11 +181,14 @@ void microblaze_gpio_discrete_write(
}
void microblaze_gpio_discrete_set(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -152,11 +199,14 @@ void microblaze_gpio_discrete_set(
}
void microblaze_gpio_discrete_clear(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -166,13 +216,19 @@ void microblaze_gpio_discrete_clear(
}
}
-rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx )
+rtems_vector_number microblaze_gpio_get_irq( unsigned int gpio_index )
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
return ctx->irq;
}
-void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx )
+void microblaze_gpio_interrupt_global_enable( unsigned int gpio_index )
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( ctx->has_interrupts );
if ( ctx->has_interrupts ) {
@@ -180,8 +236,11 @@ void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx )
}
}
-void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx )
+void microblaze_gpio_interrupt_global_disable( unsigned int gpio_index )
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( ctx->has_interrupts );
if ( ctx->has_interrupts ) {
@@ -190,10 +249,13 @@ void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx )
}
void microblaze_gpio_interrupt_enable(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( ctx->has_interrupts );
assert( channel == 1 || (ctx->is_dual && channel == 2) );
@@ -207,10 +269,13 @@ void microblaze_gpio_interrupt_enable(
}
void microblaze_gpio_interrupt_disable(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -221,10 +286,13 @@ void microblaze_gpio_interrupt_disable(
}
void microblaze_gpio_interrupt_clear(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
)
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( channel == 1 || (ctx->is_dual && channel == 2) );
if ( channel == 1 ) {
@@ -234,8 +302,11 @@ void microblaze_gpio_interrupt_clear(
}
}
-uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx )
+uint32_t microblaze_gpio_interrupt_get_enabled( unsigned int gpio_index )
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( ctx->has_interrupts );
if ( ctx->has_interrupts ) {
@@ -245,8 +316,11 @@ uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx )
return 0;
}
-uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx )
+uint32_t microblaze_gpio_interrupt_get_status( unsigned int gpio_index )
{
+ assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+ Microblaze_GPIO_context *ctx = &gpio_contexts[gpio_index];
+
assert( ctx->has_interrupts );
if ( ctx->has_interrupts ) {
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
index 5fe9c44cf8..22cc409e0a 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
@@ -129,32 +129,22 @@ typedef struct {
bool has_interrupts;
} Microblaze_GPIO_context;
-extern Microblaze_GPIO_context gpio1_context;
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-extern Microblaze_GPIO_context gpio2_context;
-#endif
-
-#define gpio1 ((Microblaze_GPIO_context * const) &gpio1_context)
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-#define gpio2 ((Microblaze_GPIO_context * const) &gpio2_context)
-#endif
-
/**
* @brief Set pin configuration for the specified GPIO channel.
*
* Changes the pin configuration for a channel. Bits set to 0 are output, and
* bits set to 1 are input.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
* @param[in] mask the mask to be applied to @ channel
*
* @retval None
*/
void microblaze_gpio_set_data_direction(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
);
/**
@@ -163,156 +153,157 @@ void microblaze_gpio_set_data_direction(
* Gets the current pin configuration for a specified GPIO channel. Bits set to
* 0 are output, and bits set to 1 are input.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
*
* @retval bitmask specifiying which pins on a channel are input or output
*/
uint32_t microblaze_gpio_get_data_direction(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
);
/**
* @brief Reads data for specified GPIO channel.
*
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
*
* @retval Current values in discretes register.
*/
uint32_t microblaze_gpio_discrete_read(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
);
/**
* @brief Writes to data register for specified GPIO channel.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
* @param[in] mask the mask to be applied to @ channel
*
* @retval None
*/
void microblaze_gpio_discrete_write(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
);
/**
* @brief Set bits to 1 on specified GPIO channel.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
* @param[in] mask the mask to be applied to @ channel
*
* @retval None
*/
void microblaze_gpio_discrete_set(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
);
/**
* @brief Set bits to 0 on specified GPIO channel.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the GPIO channel
* @param[in] mask the mask to be applied to @ channel
*
* @retval None
*/
void microblaze_gpio_discrete_clear(
- Microblaze_GPIO_context *ctx,
- uint32_t channel,
- uint32_t mask
+ unsigned int gpio_index,
+ uint32_t channel,
+ uint32_t mask
);
/**
* @brief Returns the vector number of the interrupt handler.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
*
* @retval the vector number
*/
-rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx );
+rtems_vector_number microblaze_gpio_get_irq( unsigned int gpio_index );
/**
* @brief Turns on interrupts globally.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
*
* @retval None
*/
-void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx );
+void microblaze_gpio_interrupt_global_enable( unsigned int gpio_index );
/**
* @brief Turns off interrupts globally.
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
*
* @retval None
*/
-void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx );
+void microblaze_gpio_interrupt_global_disable( unsigned int gpio_index );
/**
* @brief Enables interrupts on specified channel
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the channel to enable interrupts on
*
* @retval None
*/
void microblaze_gpio_interrupt_enable(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
);
/**
* @brief Disables interrupts on specified channel
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the channel to turn interrupts on for
*
* @retval None
*/
void microblaze_gpio_interrupt_disable(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
);
/**
* @brief Clear status of interrupt signals on a specific channel
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
* @param[in] channel the channel to clear the interrupt pending status from
*
* @retval None
*/
void microblaze_gpio_interrupt_clear(
- Microblaze_GPIO_context *ctx,
- uint32_t channel
+ unsigned int gpio_index,
+ uint32_t channel
);
/**
* @brief Return a bitmask of the interrupts that are enabled
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
*
* @retval the bitmask of enabled interrupts
*/
-uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx );
+uint32_t microblaze_gpio_interrupt_get_enabled( unsigned int gpio_index );
/**
* @brief Return a bitmask of the status of the interrupt signals
*
- * @param[in] ctx the GPIO context
+ * @param[in] gpio_index the GPIO index
*
* @retval bitmask containing statuses of interrupt signals
*/
-uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx );
+uint32_t microblaze_gpio_interrupt_get_status( unsigned int gpio_index );
#ifdef __cplusplus
}
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
index 4f854de2cd..62ac3529af 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -28,24 +28,14 @@ links:
uid: optdcachesize
- role: build-dependency
uid: optdtbheaderpath
-- role: build-dependency
- uid: optgpio2enable
- role: build-dependency
uid: optgpio1baseaddress
-- role: build-dependency
- uid: optgpio2baseaddress
- role: build-dependency
uid: optgpio1dualchannel
-- role: build-dependency
- uid: optgpio2dualchannel
- role: build-dependency
uid: optgpio1irq
-- role: build-dependency
- uid: optgpio2irq
- role: build-dependency
uid: optgpio1interrupt
-- role: build-dependency
- uid: optgpio2interrupt
- role: build-dependency
uid: opticachebaseaddress
- role: build-dependency
@@ -54,6 +44,8 @@ links:
uid: opticachesize
- role: build-dependency
uid: optintcbaseaddress
+- role: build-dependency
+ uid: optmaxgpio
- role: build-dependency
uid: optmaxuarts
- role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
deleted file mode 100644
index b3053021d9..0000000000
--- a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
+++ /dev/null
@@ -1,16 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
-default:
-- enabled-by: true
- value: false
-description: |
- GPIO 2 is dual channel
-enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-links: []
-name: BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
-type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
deleted file mode 100644
index 7fd402af43..0000000000
--- a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
+++ /dev/null
@@ -1,17 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- env-enable: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
-default:
-- enabled-by: true
- value: false
-description: |
- GPIO 2 is enabled
-enabled-by: true
-links: []
-name: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
deleted file mode 100644
index b7ef76dc18..0000000000
--- a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
+++ /dev/null
@@ -1,16 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-boolean: null
-- define-condition: null
-build-type: option
-copyrights:
-- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
-default:
-- enabled-by: true
- value: true
-description: |
- GPIO 2 has interrupt
-enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-links: []
-name: BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
-type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
deleted file mode 100644
index 4a5b63438e..0000000000
--- a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
+++ /dev/null
@@ -1,18 +0,0 @@
-SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-actions:
-- get-integer: null
-- assert-uint32: null
-- define: null
-build-type: option
-copyrights:
-- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
-default:
-- enabled-by: true
- value: 9
-description: |
- the IRQ number of GPIO 2
-enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-format: '{}'
-links: []
-name: BSP_MICROBLAZE_FPGA_GPIO2_IRQ
-type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optmaxgpio.yml
similarity index 54%
rename from spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
rename to spec/build/bsps/microblaze/microblaze_fpga/optmaxgpio.yml
index 4e248830bf..e47f595184 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optmaxgpio.yml
@@ -6,14 +6,15 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+- Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
default:
- enabled-by: true
- value: 0x40010000
+ value: 1
+default-by-variant: []
description: |
- base address of GPIO 2
-enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-format: '{:#010x}'
+ maximum number of GPIO devices
+enabled-by: true
+format: '{}'
links: []
-name: BSP_MICROBLAZE_FPGA_GPIO2_BASE
+name: BSP_MICROBLAZE_FPGA_MAX_GPIO
type: build
--
2.34.1
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