[PATCH 1/3] Adding core-v cv32a6 support

Kevin Eyssartier kevin.eyssartier at thalesgroup.com
Thu Aug 3 13:29:33 UTC 2023


This commit add support for the CV32A6 processor in the rv32imac configuration.
The CORE-V CVA6 is an application class 6 stage RISC-V CPU capable of booting Linux.
It support multiple configurations : ISA (IMACFDB), XLEN 32 and 64, configurable cache size, TLBs, PTW and branch prediction.
It is maintained by the not-for-profit [OpenHW Group](https://www.openhwgroup.org/).
Its code is under the Solderpad Hardware License which is based closely on the Apache Licese Version 2.0.
It can be found at [https://github.com/openhardware/cva6](https://github.com/openhardware/cva6).

This commit support the cv32a6_imac_sv[0|32] configurations.
RTEMS has been tested on the [Genesys2 Digilent FPGA Board](https://digilent.com/reference/programmable-logic/genesys-2/start).
---
 bsps/riscv/riscv/config/cv32a6.cfg        |  9 +++++++++
 spec/build/bsps/riscv/riscv/bspcv32a6.yml | 19 +++++++++++++++++++
 spec/build/cpukit/optarchbits.yml         |  1 +
 3 files changed, 29 insertions(+)
 create mode 100644 bsps/riscv/riscv/config/cv32a6.cfg
 create mode 100644 spec/build/bsps/riscv/riscv/bspcv32a6.yml

diff --git a/bsps/riscv/riscv/config/cv32a6.cfg b/bsps/riscv/riscv/config/cv32a6.cfg
new file mode 100644
index 0000000000..e19e431b53
--- /dev/null
+++ b/bsps/riscv/riscv/config/cv32a6.cfg
@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv32imac -mabi=ilp32
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
diff --git a/spec/build/bsps/riscv/riscv/bspcv32a6.yml b/spec/build/bsps/riscv/riscv/bspcv32a6.yml
new file mode 100644
index 0000000000..ba4a8aa64b
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspcv32a6.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: cv32a6
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 Thales (http://www.thalesgroup.com)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml
index c10a1a1d62..82abd943e1 100644
--- a/spec/build/cpukit/optarchbits.yml
+++ b/spec/build/cpukit/optarchbits.yml
@@ -24,6 +24,7 @@ default:
   - riscv/rv32i
   - riscv/rv32iac
   - riscv/rv32im
+  - riscv/cv32a6
   - riscv/rv32imac
   - riscv/rv32imafc
   - riscv/rv32imafd
-- 
2.25.1



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