[PATCH rtems-docs] user/riscv/sifive_u: Added Documentation for the new SiFive Unleashed BSP

Amna amnamannan289 at gmail.com
Mon Aug 21 17:01:08 UTC 2023


This commit contains all the required information to build and run the
new BSP.
---
 user/bsps/bsps-riscv.rst | 52 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst
index 263796e..76b70ce 100644
--- a/user/bsps/bsps-riscv.rst
+++ b/user/bsps/bsps-riscv.rst
@@ -475,3 +475,55 @@ griscv
 
 This RISC-V BSP supports chips using the
 `GRLIB <https://www.gaisler.com/products/grlib/grlib.pdf>`_.
+
+SiFive Unleashed
+================
+
+SiFive HiFive Unleashed is a development board featuring the Freedom U540
+SoC, A Linux-capable, multi-core, RISC-V processor. The 1.5+ GHz FU540 SoC features
+a 4-core U54 CPU + 1-core U51 CPU. 
+
+It can be run on QEMU provided by the RTEMS source builder's
+devel/qemu bset. This BSP requires a minimum of 128MB (Default) of RAM size
+which can be changed using the RISCV_RAM_REGION_SIZE configuration option. 
+RAM start region is the default 0x80000000. It uses the sifive UART for 
+console. Maximum 5 cores are present in the BSP. sifive_u BSP uses rv64imac 
+architecture.
+
+
+**Building the sifive_u BSP**
+
+Configuration file ``config.ini``:
+
+.. code-block:: none
+
+    [riscv/sifive_u]
+    RTEMS_SMP = True
+
+Build RTEMS:
+
+.. code-block:: shell
+
+    $ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@
+    $ ./waf
+
+**Running the sifive_u BSP**
+
+.. code-block:: shell
+
+    $ qemu-system-riscv64 -nographic -m 256M -smp 2 -machine sifive_u -bios none -kernel hello.exe
+
+Build Configuration Options
+---------------------------
+
+The following options can be used in the BSP section of the ``waf``
+configuration INI file. The ``waf`` defaults can be used to inspect the values.
+
+
+``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS``
+     The maximum number of external interrupts supported by the BSP (default
+     is 53).
+
+``RISCV_RAM_REGION_SIZE``
+     The size of the RAM region for linker command file (default 128MiB).
+
-- 
2.25.1



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