[PATCH 42/47] bsp/tms570: Initialize MPU
Sebastian Huber
sebastian.huber at embedded-brains.de
Thu Dec 21 14:38:15 UTC 2023
From: Tyler Miller <tyler.miller at airbusus.com>
---
bsps/arm/tms570/start/bspstarthooks-hwinit.c | 3 +
bsps/arm/tms570/start/tms570_sys_core.S | 202 +++++++++++++++++++
2 files changed, 205 insertions(+)
diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
index 67c3768a36..6407cc4a45 100644
--- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c
+++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
@@ -337,6 +337,9 @@ static RTEMS_USED void tms570_start_hook_0( void )
tms570_emif_sdram_init();
+ /* Configures and enables the ARM-core Memory Protection Unit (MPU) */
+ _mpuInit_();
+
#if 1
/*
* Do not depend on link register to be restored to
diff --git a/bsps/arm/tms570/start/tms570_sys_core.S b/bsps/arm/tms570/start/tms570_sys_core.S
index c3004e019f..83dee26ec8 100644
--- a/bsps/arm/tms570/start/tms570_sys_core.S
+++ b/bsps/arm/tms570/start/tms570_sys_core.S
@@ -582,4 +582,206 @@ _errata_CORTEXR4_66_:
mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
pop {r0}
bx lr
+
/*-------------------------------------------------------------------------------*/
+@ Initialize Mpu: pulled from LC4357 R5f Halcogen generation
+
+ .weak _mpuInit_
+ .type _mpuInit_, %function
+
+_mpuInit_:
+ @ Disable mpu
+ mrc p15, #0, r0, c1, c0, #0
+ bic r0, r0, #1
+ dsb
+ mcr p15, #0, r0, c1, c0, #0
+ isb
+ @ Disable background region
+ mrc p15, #0, r0, c1, c0, #0
+ bic r0, r0, #0x20000
+ mcr p15, #0, r0, c1, c0, #0
+ @ Setup region 1
+ mov r0, #0
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r1Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0008
+ orr r0, r0, #0x1000
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 2
+ mov r0, #1
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r2Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0002
+ orr r0, r0, #0x0600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 3 - Internal RAM
+ mov r0, #2
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r3Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x000B
+ orr r0, r0, #0x0300
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 4
+ mov r0, #3
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r4Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0010
+ orr r0, r0, #0x1300
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1A << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 5
+ mov r0, #4
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r5Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0000
+ orr r0, r0, #0x0300
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1B << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 6 - EMIF CS0 == External SDRAM
+ mov r0, #5
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r6Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0002
+ orr r0, r0, #0x0300
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 7
+ mov r0, #6
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r7Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0008
+ orr r0, r0, #0x1200
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 8
+ mov r0, #7
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r8Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0010
+ orr r0, r0, #0x1200
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 9
+ mov r0, #8
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r9Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x1200
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 10
+ mov r0, #9
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r10Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x000C
+ orr r0, r0, #0x1300
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 11
+ mov r0, #10
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r11Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x0600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 12
+ mov r0, #11
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r12Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x1600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 13
+ mov r0, #12
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r13Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x1600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 14
+ mov r0, #13
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r14Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x1600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 15
+ mov r0, #14
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r15Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0006
+ orr r0, r0, #0x1600
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
+ mcr p15, #0, r0, c6, c1, #2
+ @ Setup region 16
+ mov r0, #15
+ mcr p15, #0, r0, c6, c2, #0
+ ldr r0, r16Base
+ mcr p15, #0, r0, c6, c1, #0
+ mov r0, #0x0010
+ orr r0, r0, #0x1200
+ mcr p15, #0, r0, c6, c1, #4
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1))
+ mcr p15, #0, r0, c6, c1, #2
+
+ @ Enable mpu
+ mrc p15, #0, r0, c1, c0, #0
+ orr r0, r0, #1
+ dsb
+ mcr p15, #0, r0, c1, c0, #0
+ isb
+ bx lr
+
+r1Base: .word 0x00000000
+r2Base: .word 0x00000000
+r3Base: .word 0x08000000
+r4Base: .word 0xF8000000
+r5Base: .word 0x60000000
+r6Base: .word 0x80000000
+r7Base: .word 0xF0000000
+r8Base: .word 0x00000000
+r9Base: .word 0x00000000
+r10Base: .word 0x00000000
+r11Base: .word 0x00000000
+r12Base: .word 0x00000000
+r13Base: .word 0x00000000
+r14Base: .word 0x00000000
+r15Base: .word 0x00000000
+r16Base: .word 0xFFF80000
--
2.35.3
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