[PATCH 46/47] bsp/tms570: Board-specific tms570_emif_sdram_init()
Sebastian Huber
sebastian.huber at embedded-brains.de
Thu Dec 21 14:38:19 UTC 2023
From: Tyler Miller <tyler.miller at airbusus.com>
---
bsps/arm/tms570/include/bsp/tms570_hwinit.h | 6 +-
bsps/arm/tms570/start/hwinit-lc4357-hdk.c | 58 +++++++++++++
bsps/arm/tms570/start/hwinit-ls3137-hdk.c | 52 +++++++++++
bsps/arm/tms570/start/init_emif_sdram.c | 96 ---------------------
spec/build/bsps/arm/tms570/objhwinit.yml | 1 -
5 files changed, 115 insertions(+), 98 deletions(-)
delete mode 100644 bsps/arm/tms570/start/init_emif_sdram.c
diff --git a/bsps/arm/tms570/include/bsp/tms570_hwinit.h b/bsps/arm/tms570/include/bsp/tms570_hwinit.h
index f88463bb43..2af2f3d48a 100644
--- a/bsps/arm/tms570/include/bsp/tms570_hwinit.h
+++ b/bsps/arm/tms570/include/bsp/tms570_hwinit.h
@@ -69,7 +69,6 @@ void _coreEnableRamEcc_( void );
void _coreDisableRamEcc_( void );
void _mpuInit_( void );
-void tms570_emif_sdram_init( void );
void tms570_memory_init( uint32_t ram );
void tms570_trim_lpo_init( void );
void tms570_flash_init( void );
@@ -83,6 +82,11 @@ void tms570_esm_init( void );
* peripherals that are specific to a particular board.
*/
+/**
+ * @brief Initialize the External Memory InterFace (EMIF) peripheral.
+ */
+void tms570_emif_sdram_init(void);
+
/**
* @brief Initialize PLLs source divider/multipliers.
*/
diff --git a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
index 0c5a471748..1a5386d81b 100644
--- a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
+++ b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
@@ -129,6 +129,64 @@ void tms570_pinmux_init( void )
tms570_pin_config_complete();
}
+void tms570_emif_sdram_init( void )
+{
+ uint32_t dummy;
+
+ /* Do not run attempt to initialize SDRAM when code is running from it */
+ if ( tms570_running_from_sdram() )
+ return;
+
+ // Following the initialization procedure as described in EMIF-errata #5 for the tms570lc43
+ // at EMIF clock rates >= 40Mhz
+ // Note step one of this procedure is running this EMIF initialization sequence before PLL
+ // and clocks are mapped/enabled
+ // For additional details on startup procedure see tms570lc43 TRM s21.2.5.5.B
+
+ // Set SDRAM timings. These are dependent on the EMIF CLK rate, which = VCLK3
+ // Set these based on the final EMIF clock rate once PLL & VCLK is enabled
+ TMS570_EMIF.SDTIMR = (uint32_t)1U << 27U|
+ (uint32_t)0U << 24U|
+ (uint32_t)0U << 20U|
+ (uint32_t)0U << 19U|
+ (uint32_t)1U << 16U|
+ (uint32_t)1U << 12U|
+ (uint32_t)1U << 8U|
+ (uint32_t)0U << 4U;
+
+ /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
+ // Also set this based on the final EMIF clk
+ TMS570_EMIF.SDSRETR = 2;
+ // Program the RR Field of SDRCR to provide 200us of initialization time
+ // Per Errata#5, for EMIF startup, set this based on the non-VLCK3 clk rate.
+ // The Errata is this register must be calculated as `SDRCR = 200us * EMIF_CLK`
+ // (typically this would be `SDRCR = (200us * EMIF_CLK) / 8` )
+ // Since the PLL's arent enabled yet, EMIF_CLK would be EXT_OSCIN / 2
+ TMS570_EMIF.SDRCR = 1600;
+
+ TMS570_EMIF.SDCR = ((uint32_t)0U << 31U)|
+ ((uint32_t)1U << 14U)|
+ ((uint32_t)2U << 9U)|
+ ((uint32_t)1U << 8U)|
+ ((uint32_t)2U << 4U)|
+ ((uint32_t)0); // pagesize = 256
+
+ // Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes
+ dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN;
+ (void) dummy;
+
+ // Program the RR field to the default Refresh Interval of the SDRAM
+ // Program this to the correct interval for the VCLK3/EMIF_CLK rate
+ // Do this in the typical way per TRM: SDRCR = ((200us * EMIF_CLK) / 8) + 1
+ TMS570_EMIF.SDRCR = 1251;
+
+ /* Place the EMIF in Self Refresh Mode For Clock Change */
+ /* Must only write to the upper byte of the SDCR to avoid */
+ /* a second initialization sequence */
+ /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */
+ *((volatile unsigned char *)(&TMS570_EMIF.SDCR) + 0x0U) = 0x80;
+}
+
/**
* @brief Setup all system PLLs (HCG:setupPLL)
*
diff --git a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
index 610d20ecc3..1f2bbd96f2 100644
--- a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
+++ b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
@@ -240,6 +240,58 @@ void tms570_pinmux_init( void )
RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) );
}
+void tms570_emif_sdram_init(void)
+{
+ uint32_t dummy;
+ uint32_t sdtimr = 0;
+ uint32_t sdcr = 0;
+
+ /* Do not run attempt to initialize SDRAM when code is running from it */
+ if ( tms570_running_from_sdram() )
+ return;
+
+ sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 );
+ sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 );
+
+ TMS570_EMIF.SDTIMR = sdtimr;
+
+ /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
+ TMS570_EMIF.SDSRETR = 5;
+ /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
+ TMS570_EMIF.SDRCR = 2000;
+
+ /* SR - Self-Refresh mode bit. */
+ sdcr |= TMS570_EMIF_SDCR_SR * 0;
+ /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */
+ sdcr |= TMS570_EMIF_SDCR_PD * 0;
+ /* PDWR - Perform refreshes during power down. */
+ sdcr |= TMS570_EMIF_SDCR_PDWR * 0;
+ /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */
+ sdcr |= TMS570_EMIF_SDCR_NM * 1;
+ /* CL - CAS Latency. */
+ sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 );
+ /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
+ sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1;
+ /* IBANK - Internal SDRAM Bank size. */
+ sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */
+ /* Page Size. This field defines the internal page size of connected SDRAM devices. */
+ sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */
+
+ TMS570_EMIF.SDCR = sdcr;
+
+ dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN;
+ (void) dummy;
+ TMS570_EMIF.SDRCR = 31;
+
+ /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
+ TMS570_EMIF.SDRCR = 312;
+}
+
/**
* @brief Setup all system PLLs (HCG:setupPLL)
*
diff --git a/bsps/arm/tms570/start/init_emif_sdram.c b/bsps/arm/tms570/start/init_emif_sdram.c
deleted file mode 100644
index 0b190da321..0000000000
--- a/bsps/arm/tms570/start/init_emif_sdram.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMTMS570
- *
- * @brief This source file contains the initialization of
- * external memory/SDRAM interface.
- */
-
-/*
- * Copyright (C) 2016 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- *
- * Czech Technical University in Prague
- * Zikova 1903/4
- * 166 36 Praha 6
- * Czech Republic
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <stdint.h>
-#include <bsp/tms570.h>
-#include <bsp/tms570_hwinit.h>
-
-void tms570_emif_sdram_init( void )
-{
- uint32_t dummy;
- uint32_t sdtimr = 0;
- uint32_t sdcr = 0;
-
- /* Do not run attempt to initialize SDRAM when code is running from it */
- if ( tms570_running_from_sdram() )
- return;
-
- sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 );
- sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 );
-
- TMS570_EMIF.SDTIMR = sdtimr;
-
- /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
- TMS570_EMIF.SDSRETR = 5;
- /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
- TMS570_EMIF.SDRCR = 2000;
-
- /* SR - Self-Refresh mode bit. */
- sdcr |= TMS570_EMIF_SDCR_SR * 0;
- /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */
- sdcr |= TMS570_EMIF_SDCR_PD * 0;
- /* PDWR - Perform refreshes during power down. */
- sdcr |= TMS570_EMIF_SDCR_PDWR * 0;
- /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */
- sdcr |= TMS570_EMIF_SDCR_NM * 1;
- /* CL - CAS Latency. */
- sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 );
- /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
- sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1;
- /* IBANK - Internal SDRAM Bank size. */
- sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */
- /* Page Size. This field defines the internal page size of connected SDRAM devices. */
- sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */
-
- TMS570_EMIF.SDCR = sdcr;
-
- dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN;
- (void) dummy;
- TMS570_EMIF.SDRCR = 31;
-
- /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
- TMS570_EMIF.SDRCR = 312;
-}
diff --git a/spec/build/bsps/arm/tms570/objhwinit.yml b/spec/build/bsps/arm/tms570/objhwinit.yml
index db4b8fdedd..01b1502280 100644
--- a/spec/build/bsps/arm/tms570/objhwinit.yml
+++ b/spec/build/bsps/arm/tms570/objhwinit.yml
@@ -21,7 +21,6 @@ source:
- bsps/arm/tms570/start/bspstarthooks-hwinit.c
- bsps/arm/tms570/start/errata_SSWF021_45.c
- bsps/arm/tms570/start/fail_notification.c
-- bsps/arm/tms570/start/init_emif_sdram.c
- bsps/arm/tms570/start/init_esm.c
- bsps/arm/tms570/start/init_system.c
- bsps/arm/tms570/start/tms570_selftest.c
--
2.35.3
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