[PATCH] bsps/microblaze: Add AXI GPIO driver
Alex White
alex.white at oarcorp.com
Tue Feb 14 21:18:31 UTC 2023
---
.../microblaze_fpga/gpio/microblaze-gpio.c | 261 ++++++++++++++
.../include/bsp/microblaze-gpio.h | 321 ++++++++++++++++++
.../bsps/microblaze/microblaze_fpga/grp.yml | 18 +
.../bsps/microblaze/microblaze_fpga/obj.yml | 2 +
.../microblaze_fpga/optgpio1baseaddress.yml | 20 ++
.../microblaze_fpga/optgpio1dualchannel.yml | 17 +
.../microblaze_fpga/optgpio1interrupt.yml | 17 +
.../microblaze_fpga/optgpio1irq.yml | 19 ++
.../microblaze_fpga/optgpio2baseaddress.yml | 20 ++
.../microblaze_fpga/optgpio2dualchannel.yml | 17 +
.../microblaze_fpga/optgpio2enable.yml | 18 +
.../microblaze_fpga/optgpio2interrupt.yml | 17 +
.../microblaze_fpga/optgpio2irq.yml | 19 ++
13 files changed, 766 insertions(+)
create mode 100644 bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
new file mode 100644
index 0000000000..9025840e32
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI GPIO implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+
+#include <bsp/fatal.h>
+#include <bsp/microblaze-gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+Microblaze_GPIO_context gpio1_context = {
+ .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
+ .is_dual = true,
+#else
+ .is_dual = false,
+#endif
+ .irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
+ .has_interrupts = true
+#else
+ .has_interrupts = false
+#endif
+};
+
+#if BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+Microblaze_GPIO_context gpio2_context = {
+ .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO2_BASE,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
+ .is_dual = true,
+#else
+ .is_dual = false,
+#endif
+ .irq = BSP_MICROBLAZE_FPGA_GPIO2_IRQ,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
+ .has_interrupts = true
+#else
+ .has_interrupts = false
+#endif
+};
+#endif
+
+void microblaze_gpio_set_data_direction(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->gpio_tri = mask;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->gpio2_tri = mask;
+ }
+}
+
+uint32_t microblaze_gpio_get_data_direction(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ return ctx->regs->gpio_tri;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ return ctx->regs->gpio2_tri;
+ }
+
+ return 0;
+}
+
+uint32_t microblaze_gpio_discrete_read(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ return ctx->regs->gpio_data;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ return ctx->regs->gpio2_tri;
+ }
+
+ return 0;
+}
+
+void microblaze_gpio_discrete_write(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->gpio_data = mask;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->gpio2_tri = mask;
+ }
+}
+
+void microblaze_gpio_discrete_set(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->gpio_data |= mask;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->gpio2_tri |= mask;
+ }
+}
+
+void microblaze_gpio_discrete_clear(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->gpio_data &= ~mask;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->gpio2_tri &= ~mask;
+ }
+}
+
+rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx )
+{
+ return ctx->irq;
+}
+
+void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx )
+{
+ assert( ctx->has_interrupts );
+
+ if ( ctx->has_interrupts ) {
+ ctx->regs->gier = GLOBAL_INTERRUPT_REGISTER_ENABLE;
+ }
+}
+
+void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx )
+{
+ assert( ctx->has_interrupts );
+
+ if ( ctx->has_interrupts ) {
+ ctx->regs->gier = 0x0;
+ }
+}
+
+void microblaze_gpio_interrupt_enable(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+)
+{
+ assert( ctx->has_interrupts );
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( ctx->has_interrupts ) {
+ if ( channel == 1 ) {
+ ctx->regs->ip_ier |= CHANNEL_1_INTERRUPT_REGISTER;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->ip_ier |= CHANNEL_2_INTERRUPT_REGISTER;
+ }
+ }
+}
+
+void microblaze_gpio_interrupt_disable(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->ip_ier &= ~CHANNEL_1_INTERRUPT_REGISTER;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->ip_ier &= ~CHANNEL_2_INTERRUPT_REGISTER;
+ }
+}
+
+void microblaze_gpio_interrupt_clear(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+)
+{
+ assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+ if ( channel == 1 ) {
+ ctx->regs->ip_isr &= CHANNEL_1_INTERRUPT_REGISTER;
+ } else if ( ctx->is_dual && channel == 2 ) {
+ ctx->regs->ip_isr &= CHANNEL_2_INTERRUPT_REGISTER;
+ }
+}
+
+uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx )
+{
+ assert( ctx->has_interrupts );
+
+ if ( ctx->has_interrupts ) {
+ return ctx->regs->ip_ier;
+ }
+
+ return 0;
+}
+
+uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx )
+{
+ assert( ctx->has_interrupts );
+
+ if ( ctx->has_interrupts ) {
+ return ctx->regs->ip_isr;
+ }
+
+ return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
new file mode 100644
index 0000000000..5fe9c44cf8
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
@@ -0,0 +1,321 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI GPIO definitions
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H
+#define LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H
+
+#include <bspopts.h>
+#include <bsp/utility.h>
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+ /* Channel 1 data values */
+
+ /*
+ * Used to read general purpose input ports and write to general purpose
+ * output ports from channel 1.
+ */
+ volatile uint32_t gpio_data;
+
+ /*
+ * The 3-state control register for channel 1 is used for the dynamic
+ * configuration of ports as input or output. When a bit is set to 1, the
+ * corresponding I/O port is an input port. When a bit is set to 0, it is an
+ * output port.
+ */
+ volatile uint32_t gpio_tri;
+
+ /* Channel 2 data values */
+
+ /*
+ * Used to read general purpose input ports and write to general purpose
+ * output ports from channel 2.
+ */
+ volatile uint32_t gpio2_data;
+
+ /*
+ * The 3-state control register for channel 2 is used for the dynamic
+ * configuration of ports as input or output. When a bit is set to 1, the
+ * corresponding I/O port is an input port. When a bit is set to 0, it is an
+ * output port.
+ */
+ volatile uint32_t gpio2_tri;
+
+ char _unused[272];
+
+ /* Only the 31st bit is used to enable interrupts globally */
+#define GLOBAL_INTERRUPT_REGISTER_ENABLE BSP_BIT32(31)
+
+ /*
+ * Global Interrupt Enable Register
+ *
+ * Determines whether interrupts are enabled or disabled.
+ *
+ * 0 - Disabled
+ * 1 - Enabled
+ */
+ volatile uint32_t gier;
+
+ char _unused2[12];
+
+ /* Used with ip_isr and ip_ier member variables */
+#define CHANNEL_1_INTERRUPT_REGISTER BSP_BIT32(0)
+#define CHANNEL_2_INTERRUPT_REGISTER BSP_BIT32(1)
+
+ /*
+ * IP Status Registers
+ *
+ * Contains the status bit for each channel.
+ *
+ * 0 - Disabled
+ * 1 - Enabled
+ */
+ volatile uint32_t ip_isr;
+
+ char _unused3[4];
+
+ /*
+ * IP Interrupt Enable Register
+ *
+ * Provides the ability to independtly control whether interrupts for each
+ * channel are enabled or disabled.
+ *
+ * 0 - No Channel input interrupt
+ * 1 - Channel input interrupt
+ */
+ volatile uint32_t ip_ier;
+} Microblaze_GPIO_registers;
+
+typedef struct {
+ Microblaze_GPIO_registers *regs;
+ bool is_dual;
+ uint32_t irq;
+ bool has_interrupts;
+} Microblaze_GPIO_context;
+
+extern Microblaze_GPIO_context gpio1_context;
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+extern Microblaze_GPIO_context gpio2_context;
+#endif
+
+#define gpio1 ((Microblaze_GPIO_context * const) &gpio1_context)
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+#define gpio2 ((Microblaze_GPIO_context * const) &gpio2_context)
+#endif
+
+/**
+ * @brief Set pin configuration for the specified GPIO channel.
+ *
+ * Changes the pin configuration for a channel. Bits set to 0 are output, and
+ * bits set to 1 are input.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ * @param[in] mask the mask to be applied to @ channel
+ *
+ * @retval None
+ */
+void microblaze_gpio_set_data_direction(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+);
+
+/**
+ * @brief Get pin configuration for specified GPIO channel.
+ *
+ * Gets the current pin configuration for a specified GPIO channel. Bits set to
+ * 0 are output, and bits set to 1 are input.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ *
+ * @retval bitmask specifiying which pins on a channel are input or output
+ */
+uint32_t microblaze_gpio_get_data_direction(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+);
+
+/**
+ * @brief Reads data for specified GPIO channel.
+ *
+ * @param[in] channel the GPIO channel
+ *
+ * @retval Current values in discretes register.
+ */
+uint32_t microblaze_gpio_discrete_read(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+);
+
+/**
+ * @brief Writes to data register for specified GPIO channel.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ * @param[in] mask the mask to be applied to @ channel
+ *
+ * @retval None
+ */
+void microblaze_gpio_discrete_write(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+);
+
+/**
+ * @brief Set bits to 1 on specified GPIO channel.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ * @param[in] mask the mask to be applied to @ channel
+ *
+ * @retval None
+ */
+void microblaze_gpio_discrete_set(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+);
+
+/**
+ * @brief Set bits to 0 on specified GPIO channel.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ * @param[in] mask the mask to be applied to @ channel
+ *
+ * @retval None
+ */
+void microblaze_gpio_discrete_clear(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel,
+ uint32_t mask
+);
+
+/**
+ * @brief Returns the vector number of the interrupt handler.
+ *
+ * @param[in] ctx the GPIO context
+ *
+ * @retval the vector number
+ */
+rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx );
+
+/**
+ * @brief Turns on interrupts globally.
+ *
+ * @param[in] ctx the GPIO context
+ *
+ * @retval None
+ */
+void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx );
+
+/**
+ * @brief Turns off interrupts globally.
+ *
+ * @param[in] ctx the GPIO context
+ *
+ * @retval None
+ */
+void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx );
+
+/**
+ * @brief Enables interrupts on specified channel
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the channel to enable interrupts on
+ *
+ * @retval None
+ */
+void microblaze_gpio_interrupt_enable(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+);
+
+/**
+ * @brief Disables interrupts on specified channel
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the channel to turn interrupts on for
+ *
+ * @retval None
+ */
+void microblaze_gpio_interrupt_disable(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+);
+
+/**
+ * @brief Clear status of interrupt signals on a specific channel
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the channel to clear the interrupt pending status from
+ *
+ * @retval None
+ */
+void microblaze_gpio_interrupt_clear(
+ Microblaze_GPIO_context *ctx,
+ uint32_t channel
+);
+
+/**
+ * @brief Return a bitmask of the interrupts that are enabled
+ *
+ * @param[in] ctx the GPIO context
+ *
+ * @retval the bitmask of enabled interrupts
+ */
+uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx );
+
+/**
+ * @brief Return a bitmask of the status of the interrupt signals
+ *
+ * @param[in] ctx the GPIO context
+ *
+ * @retval bitmask containing statuses of interrupt signals
+ */
+uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H */
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
index f3088a68a3..4d1ac0f426 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -28,6 +28,24 @@ links:
uid: optdcachesize
- role: build-dependency
uid: optdtbheaderpath
+- role: build-dependency
+ uid: optgpio2enable
+- role: build-dependency
+ uid: optgpio1baseaddress
+- role: build-dependency
+ uid: optgpio2baseaddress
+- role: build-dependency
+ uid: optgpio1dualchannel
+- role: build-dependency
+ uid: optgpio2dualchannel
+- role: build-dependency
+ uid: optgpio1irq
+- role: build-dependency
+ uid: optgpio2irq
+- role: build-dependency
+ uid: optgpio1interrupt
+- role: build-dependency
+ uid: optgpio2interrupt
- role: build-dependency
uid: opticachebaseaddress
- role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
index 2bbe50d3d9..487a99aae9 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml
@@ -15,6 +15,7 @@ install:
source:
- bsps/microblaze/microblaze_fpga/include/bsp/irq.h
- bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h
+ - bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
- bsps/microblaze/include/bsp/microblaze-fdt-support.h
- bsps/microblaze/include/common/xil_types.h
- bsps/microblaze/include/dev/serial/uartlite.h
@@ -25,6 +26,7 @@ source:
- bsps/microblaze/microblaze_fpga/console/console-io.c
- bsps/microblaze/microblaze_fpga/console/debug-io.c
- bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
+- bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
- bsps/microblaze/microblaze_fpga/irq/irq.c
- bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S
- bsps/microblaze/microblaze_fpga/start/_exception_handler.S
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
new file mode 100644
index 0000000000..f525b0468b
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: 0x40000000
+default-by-variant: []
+description: |
+ base address of GPIO 1
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO1_BASE
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
new file mode 100644
index 0000000000..c8810e2a9a
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: true
+default-by-variant: []
+description: |
+ GPIO 1 is dual channel
+enabled-by: true
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
new file mode 100644
index 0000000000..59df9b1bce
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: true
+default-by-variant: []
+description: |
+ GPIO 1 has interrupt
+enabled-by: true
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
new file mode 100644
index 0000000000..69e3c5d2d5
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: 8
+default-by-variant: []
+description: |
+ the IRQ number of GPIO 1
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO1_IRQ
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
new file mode 100644
index 0000000000..2da5cd722e
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: 0x40010000
+default-by-variant: []
+description: |
+ base address of GPIO 2
+enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO2_BASE
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
new file mode 100644
index 0000000000..c6d4819d8c
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: false
+default-by-variant: []
+description: |
+ GPIO 2 is dual channel
+enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
new file mode 100644
index 0000000000..65e9be167e
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- env-enable: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: false
+default-by-variant: []
+description: |
+ GPIO 2 is enabled
+enabled-by: true
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
new file mode 100644
index 0000000000..de579426d2
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: true
+default-by-variant: []
+description: |
+ GPIO 2 has interrupt
+enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
+type: build
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
new file mode 100644
index 0000000000..18b64f3680
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default:
+- enabled-by: true
+ value: 9
+default-by-variant: []
+description: |
+ the IRQ number of GPIO 2
+enabled-by: BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_GPIO2_IRQ
+type: build
--
2.34.1
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