[PATCH] arm/stm32h7: Add support for STM32H750B-DK
Kinsey Moore
kinsey.moore at oarcorp.com
Tue Jul 11 13:50:16 UTC 2023
This adds support for the STM32H750B-DK discovery kit. This kit includes
a built-in STLINKv3 debugger which provides a USB serial bridge for
USART3. USART1 is routed to the Arduino header and USART2 is routed to
the STMOD connector. This BSP reuses what would otherwise be duplicated
files from the stm32h747i-disco BSP. Note that system_stm32h7xx.c has
been imported from the STM repository with two minor changes wrapped
with #if __rtems__. This hardware has been tested with hello and ticker.
---
.../stm/stm32h750b-dk/stm32h7-config-per.c | 40 ++
.../stm/stm32h750b-dk/system_stm32h7xx.c | 528 ++++++++++++++++++
bsps/arm/stm32h7/console/console-usart2-cfg.c | 4 +-
.../bsps/arm/stm32h7/bspstm32h750b-dk.yml | 23 +
spec/build/bsps/arm/stm32h7/grp.yml | 4 +
spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 1 +
.../bsps/arm/stm32h7/optmemquadspisz.yml | 1 +
.../build/bsps/arm/stm32h7/optmemsdram1sz.yml | 3 +
.../bsps/arm/stm32h7/optprintkinstance.yml | 4 +-
.../bsps/arm/stm32h7/optusart1gpiopins.yml | 3 +
.../bsps/arm/stm32h7/optusart1gpioregs.yml | 1 +
.../bsps/arm/stm32h7/optusart2gpiopins.yml | 20 +
.../bsps/arm/stm32h7/optusart2gpioregs.yml | 19 +
.../bsps/arm/stm32h7/optusart3gpiopins.yml | 2 +
.../bsps/arm/stm32h7/optusart3gpioregs.yml | 2 +
spec/build/bsps/arm/stm32h7/optvariant.yml | 3 +
16 files changed, 655 insertions(+), 3 deletions(-)
create mode 100644 bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
create mode 100644 bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optusart2gpiopins.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optusart2gpioregs.yml
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
new file mode 100644
index 0000000000..f34a633305
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
+ /* for stm32h750b-dk BSP we provide U(S)ART1/2/3 */
+ .PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2
+ | RCC_PERIPHCLK_USART3,
+ .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
+ .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
+};
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
new file mode 100644
index 0000000000..78029a90cf
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
@@ -0,0 +1,528 @@
+/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SDRAM mounted
+ on DISCO board as data memory */
+/*#define DATA_IN_ExtSDRAM*/
+#ifdef __rtems__
+#define DATA_IN_ExtSDRAM
+#endif /* __rtems__ */
+
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+#ifndef __rtems__
+#if defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSDRAM */
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x00000000;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x00000000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x00000000;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x00000000;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x00000000;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x00000001U;
+ }
+
+#if defined (DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM , enable the D2 SRAM clock */
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+ tmpreg = RCC->AHB2ENR;
+ (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+
+/*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+#if defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ float_t fracn1, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ SystemCoreClock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ SystemCoreClock = 0U;
+ }
+ break;
+
+ default:
+ SystemCoreClock = CSI_VALUE;
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+ /* SystemCoreClock frequency : CM7 CPU frequency */
+ SystemCoreClock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+}
+#if defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32h7xx.s before jump to main.
+ * This function configures the external memories SDRAM
+ * This SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0;
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB4ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAFEAFFFA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xF03F000F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x50150005;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABFFA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554005;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAABFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55400555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CC00CC;
+ GPIOG->AFR[1] = 0xC000000C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xBFFEFAFA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0xC0030F0F;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x40010505;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0xCCC00000;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAAABFF;
+ /* Configure PHx pins speed to 100 MHz */
+ GPIOH->OSPEEDR = 0xFFFFFC00;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* Configure PHx pins in Pull-up */
+ GPIOH->PUPDR = 0x55555400;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+ /*SDRAM Timing and access interface configuration*/
+ /*LoadToActiveDelay = 2
+ ExitSelfRefreshDelay = 6
+ SelfRefreshTime = 4
+ RowCycleDelay = 6
+ WriteRecoveryTime = 2
+ RPDelay = 2
+ RCDDelay = 2
+ SDBank = FMC_SDRAM_BANK2
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
+
+ FMC_Bank5_6_R->SDCR[0] = 0x00001800;
+ FMC_Bank5_6_R->SDCR[1] = 0x00000154;
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000;
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6_R->SDCMR = 0x00000009;
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6_R->SDCMR = 0x0000000A;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6_R->SDRTR;
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6_R->SDCR[1];
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
+
+ /*FMC controller Enable*/
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+ (void)(tmp);
+}
+#endif /* DATA_IN_ExtSDRAM */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsps/arm/stm32h7/console/console-usart2-cfg.c b/bsps/arm/stm32h7/console/console-usart2-cfg.c
index e0b406c6c2..d7f59f05d1 100644
--- a/bsps/arm/stm32h7/console/console-usart2-cfg.c
+++ b/bsps/arm/stm32h7/console/console-usart2-cfg.c
@@ -33,9 +33,9 @@
const stm32h7_uart_config stm32h7_usart2_config = {
.gpio = {
- .regs = GPIOA,
+ .regs = STM32H7_USART2_GPIO_REGS,
.config = {
- .Pin = GPIO_PIN_2 | GPIO_PIN_3,
+ .Pin = STM32H7_USART2_GPIO_PINS,
.Mode = GPIO_MODE_AF_PP,
.Pull = GPIO_NOPULL,
.Speed = GPIO_SPEED_FREQ_LOW,
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml b/spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml
new file mode 100644
index 0000000000..f5a1ad3b90
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32h750b-dk
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: stm32h7
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: grp
+source:
+- bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c
+- bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-config-clk.c
+- bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-config-osc.c
+- bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
+- bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
+- bsps/arm/shared/cache/cache-v7m.c
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml b/spec/build/bsps/arm/stm32h7/grp.yml
index e5d679e09d..595762c665 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -98,6 +98,10 @@ links:
uid: optusart1gpioregs
- role: build-dependency
uid: optusart1alternatefunc
+- role: build-dependency
+ uid: optusart2gpiopins
+- role: build-dependency
+ uid: optusart2gpioregs
- role: build-dependency
uid: optusart3gpiopins
- role: build-dependency
diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
index 5080409f04..cee48a999e 100644
--- a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
+++ b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
@@ -10,6 +10,7 @@ default:
- arm/nucleo-h743zi
- arm/stm32h747i-disco
- arm/stm32h747i-disco-m4
+ - arm/stm32h750b-dk
- arm/stm32h757i-eval
- arm/stm32h757i-eval-m4
- arm/stm32h7b3i-dk
diff --git a/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml
index 784c23a785..821ae3c197 100644
--- a/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemquadspisz.yml
@@ -8,6 +8,7 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
+ - arm/stm32h750b-dk
- arm/stm32h757i-eval
- arm/stm32h757i-eval-m4
value: 0x08000000
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
index bd1053db38..56ec66a64f 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
@@ -14,6 +14,9 @@ default:
- arm/stm32h757i-eval-m4
- arm/stm32h7b3i-dk
value: 0x00000000
+- enabled-by:
+ - arm/stm32h750b-dk
+ value: 0x01000000
- enabled-by: true
value: 0x02000000
description: |
diff --git a/spec/build/bsps/arm/stm32h7/optprintkinstance.yml b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml
index 88870626c7..e02a9c4fb7 100644
--- a/spec/build/bsps/arm/stm32h7/optprintkinstance.yml
+++ b/spec/build/bsps/arm/stm32h7/optprintkinstance.yml
@@ -6,7 +6,9 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
-- enabled-by: arm/nucleo-h743zi
+- enabled-by:
+ - arm/nucleo-h743zi
+ - arm/stm32h750b-dk
value: stm32h7_usart3_instance
- enabled-by: true
value: stm32h7_usart1_instance
diff --git a/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml b/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
index 1daefc26d2..e1ea0e77c3 100644
--- a/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
+++ b/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
@@ -6,6 +6,9 @@ build-type: option
copyrights:
- Copyright (C) 2021, 22 embedded brains GmbH & Co. KG
default:
+- enabled-by:
+ - arm/stm32h750b-dk
+ value: ( GPIO_PIN_6 | GPIO_PIN_7 )
- enabled-by:
- arm/stm32h747i-disco
- arm/stm32h747i-disco-m4
diff --git a/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
index 4029725f7e..028f023fd7 100644
--- a/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
+++ b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
@@ -12,6 +12,7 @@ default:
- arm/stm32h7b3i-dk
value: GPIOA
- enabled-by:
+ - arm/stm32h750b-dk
- arm/stm32h757i-eval
- arm/stm32h757i-eval-m4
value: GPIOB
diff --git a/spec/build/bsps/arm/stm32h7/optusart2gpiopins.yml b/spec/build/bsps/arm/stm32h7/optusart2gpiopins.yml
new file mode 100644
index 0000000000..731d9c07f5
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optusart2gpiopins.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 On-Line Applications Research (OAR)
+default:
+- enabled-by:
+ - arm/stm32h750b-dk
+ value: ( GPIO_PIN_5 | GPIO_PIN_6 )
+- enabled-by: true
+ value: ( GPIO_PIN_2 | GPIO_PIN_3 )
+description: |
+ GPIO pins used for the USART1 pin configuration.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_USART2_GPIO_PINS
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/optusart2gpioregs.yml b/spec/build/bsps/arm/stm32h7/optusart2gpioregs.yml
new file mode 100644
index 0000000000..9c297e2efd
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optusart2gpioregs.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 On-Line Applications Research (OAR)
+default:
+- enabled-by: arm/stm32h750b-dk
+ value: GPIOD
+- enabled-by: true
+ value: GPIOA
+description: |
+ GPIO registers used for the USART2 pin configuration.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_USART2_GPIO_REGS
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/optusart3gpiopins.yml b/spec/build/bsps/arm/stm32h7/optusart3gpiopins.yml
index f8b410312a..e03d637e1a 100644
--- a/spec/build/bsps/arm/stm32h7/optusart3gpiopins.yml
+++ b/spec/build/bsps/arm/stm32h7/optusart3gpiopins.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/stm32h750b-dk
+ value: ( GPIO_PIN_10 | GPIO_PIN_11 )
- enabled-by: true
value: ( GPIO_PIN_8 | GPIO_PIN_9 )
description: |
diff --git a/spec/build/bsps/arm/stm32h7/optusart3gpioregs.yml b/spec/build/bsps/arm/stm32h7/optusart3gpioregs.yml
index 806f740e66..60dbd19c4f 100644
--- a/spec/build/bsps/arm/stm32h7/optusart3gpioregs.yml
+++ b/spec/build/bsps/arm/stm32h7/optusart3gpioregs.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/stm32h750b-dk
+ value: GPIOB
- enabled-by: true
value: GPIOD
description: |
diff --git a/spec/build/bsps/arm/stm32h7/optvariant.yml b/spec/build/bsps/arm/stm32h7/optvariant.yml
index bbce5f93ee..a24f0db988 100644
--- a/spec/build/bsps/arm/stm32h7/optvariant.yml
+++ b/spec/build/bsps/arm/stm32h7/optvariant.yml
@@ -26,6 +26,9 @@ default:
- arm/stm32h747i-disco
- arm/stm32h747i-disco-m4
value: STM32H747xx
+- enabled-by:
+ - arm/stm32h750b-dk
+ value: STM32H750xx
- enabled-by: true
value: STM32H743xx
description: |
--
2.39.2
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