[PATCH v3 09/38] bsps/grlib: Move GR740-specific registers
Sebastian Huber
sebastian.huber at embedded-brains.de
Wed Jul 12 13:49:48 UTC 2023
Update #4842.
---
bsps/include/grlib/gr740thsens-regs.h | 226 ------
bsps/include/grlib/grgprbank-regs.h | 677 -----------------
.../leon3/include/bsp/gr740-bootstrap-regs.h} | 78 +-
.../leon3/include/bsp/gr740-iopll-regs.h | 679 ++++++++++++++++++
.../leon3/include/bsp/gr740-thsens-regs.h | 229 ++++++
5 files changed, 948 insertions(+), 941 deletions(-)
delete mode 100644 bsps/include/grlib/gr740thsens-regs.h
delete mode 100644 bsps/include/grlib/grgprbank-regs.h
rename bsps/{include/grlib/grgpreg-regs.h => sparc/leon3/include/bsp/gr740-bootstrap-regs.h} (53%)
create mode 100644 bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h
create mode 100644 bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h
diff --git a/bsps/include/grlib/gr740thsens-regs.h b/bsps/include/grlib/gr740thsens-regs.h
deleted file mode 100644
index f9ec8103b9..0000000000
--- a/bsps/include/grlib/gr740thsens-regs.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSDeviceGR740THSENS
- *
- * @brief This header file defines the GR740THSENS register block interface.
- */
-
-/*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * This file is part of the RTEMS quality process and was automatically
- * generated. If you find something that needs to be fixed or
- * worded better please post a report or patch to an RTEMS mailing list
- * or raise a bug report:
- *
- * https://www.rtems.org/bugs.html
- *
- * For information on updating and regenerating please refer to the How-To
- * section in the Software Requirements Engineering chapter of the
- * RTEMS Software Engineering manual. The manual is provided as a part of
- * a release. For development sources please refer to the online
- * documentation at:
- *
- * https://docs.rtems.org
- */
-
-/* Generated from spec:/dev/grlib/if/gr740thsens-header */
-
-#ifndef _GRLIB_GR740THSENS_REGS_H
-#define _GRLIB_GR740THSENS_REGS_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Generated from spec:/dev/grlib/if/gr740thsens */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENS GR740THSENS
- *
- * @ingroup RTEMSDeviceGRLIB
- *
- * @brief This group contains the GR740THSENS interfaces.
- *
- * @{
- */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENSCTRL Control register (CTRL)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GR740THSENS_CTRL_DIV_SHIFT 16
-#define GR740THSENS_CTRL_DIV_MASK 0x3ff0000U
-#define GR740THSENS_CTRL_DIV_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_CTRL_DIV_MASK ) >> \
- GR740THSENS_CTRL_DIV_SHIFT )
-#define GR740THSENS_CTRL_DIV_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_CTRL_DIV_MASK ) | \
- ( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
- GR740THSENS_CTRL_DIV_MASK ) )
-#define GR740THSENS_CTRL_DIV( _val ) \
- ( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
- GR740THSENS_CTRL_DIV_MASK )
-
-#define GR740THSENS_CTRL_ALEN 0x100U
-
-#define GR740THSENS_CTRL_PDN 0x80U
-
-#define GR740THSENS_CTRL_DCORRECT_SHIFT 2
-#define GR740THSENS_CTRL_DCORRECT_MASK 0x7cU
-#define GR740THSENS_CTRL_DCORRECT_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_CTRL_DCORRECT_MASK ) >> \
- GR740THSENS_CTRL_DCORRECT_SHIFT )
-#define GR740THSENS_CTRL_DCORRECT_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_CTRL_DCORRECT_MASK ) | \
- ( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
- GR740THSENS_CTRL_DCORRECT_MASK ) )
-#define GR740THSENS_CTRL_DCORRECT( _val ) \
- ( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
- GR740THSENS_CTRL_DCORRECT_MASK )
-
-#define GR740THSENS_CTRL_SRSTN 0x2U
-
-#define GR740THSENS_CTRL_CLKEN 0x1U
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENSSTATUS Status register (STATUS)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GR740THSENS_STATUS_MAX_SHIFT 24
-#define GR740THSENS_STATUS_MAX_MASK 0x7f000000U
-#define GR740THSENS_STATUS_MAX_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_STATUS_MAX_MASK ) >> \
- GR740THSENS_STATUS_MAX_SHIFT )
-#define GR740THSENS_STATUS_MAX_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_STATUS_MAX_MASK ) | \
- ( ( ( _val ) << GR740THSENS_STATUS_MAX_SHIFT ) & \
- GR740THSENS_STATUS_MAX_MASK ) )
-#define GR740THSENS_STATUS_MAX( _val ) \
- ( ( ( _val ) << GR740THSENS_STATUS_MAX_SHIFT ) & \
- GR740THSENS_STATUS_MAX_MASK )
-
-#define GR740THSENS_STATUS_MIN_SHIFT 16
-#define GR740THSENS_STATUS_MIN_MASK 0x7f0000U
-#define GR740THSENS_STATUS_MIN_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_STATUS_MIN_MASK ) >> \
- GR740THSENS_STATUS_MIN_SHIFT )
-#define GR740THSENS_STATUS_MIN_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_STATUS_MIN_MASK ) | \
- ( ( ( _val ) << GR740THSENS_STATUS_MIN_SHIFT ) & \
- GR740THSENS_STATUS_MIN_MASK ) )
-#define GR740THSENS_STATUS_MIN( _val ) \
- ( ( ( _val ) << GR740THSENS_STATUS_MIN_SHIFT ) & \
- GR740THSENS_STATUS_MIN_MASK )
-
-#define GR740THSENS_STATUS_SCLK 0x8000U
-
-#define GR740THSENS_STATUS_WE 0x400U
-
-#define GR740THSENS_STATUS_UPD 0x200U
-
-#define GR740THSENS_STATUS_ALACT 0x100U
-
-#define GR740THSENS_STATUS_DATA_SHIFT 0
-#define GR740THSENS_STATUS_DATA_MASK 0x7fU
-#define GR740THSENS_STATUS_DATA_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_STATUS_DATA_MASK ) >> \
- GR740THSENS_STATUS_DATA_SHIFT )
-#define GR740THSENS_STATUS_DATA_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_STATUS_DATA_MASK ) | \
- ( ( ( _val ) << GR740THSENS_STATUS_DATA_SHIFT ) & \
- GR740THSENS_STATUS_DATA_MASK ) )
-#define GR740THSENS_STATUS_DATA( _val ) \
- ( ( ( _val ) << GR740THSENS_STATUS_DATA_SHIFT ) & \
- GR740THSENS_STATUS_DATA_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENSTHRES Threshold register (THRES)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GR740THSENS_THRES_THRES_SHIFT 0
-#define GR740THSENS_THRES_THRES_MASK 0x7fU
-#define GR740THSENS_THRES_THRES_GET( _reg ) \
- ( ( ( _reg ) & GR740THSENS_THRES_THRES_MASK ) >> \
- GR740THSENS_THRES_THRES_SHIFT )
-#define GR740THSENS_THRES_THRES_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GR740THSENS_THRES_THRES_MASK ) | \
- ( ( ( _val ) << GR740THSENS_THRES_THRES_SHIFT ) & \
- GR740THSENS_THRES_THRES_MASK ) )
-#define GR740THSENS_THRES_THRES( _val ) \
- ( ( ( _val ) << GR740THSENS_THRES_THRES_SHIFT ) & \
- GR740THSENS_THRES_THRES_MASK )
-
-/** @} */
-
-/**
- * @brief This structure defines the GR740THSENS register block memory map.
- */
-typedef struct gr740thsens {
- /**
- * @brief See @ref RTEMSDeviceGR740THSENSCTRL.
- */
- uint32_t ctrl;
-
- /**
- * @brief See @ref RTEMSDeviceGR740THSENSSTATUS.
- */
- uint32_t status;
-
- /**
- * @brief See @ref RTEMSDeviceGR740THSENSTHRES.
- */
- uint32_t thres;
-} gr740thsens;
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _GRLIB_GR740THSENS_REGS_H */
diff --git a/bsps/include/grlib/grgprbank-regs.h b/bsps/include/grlib/grgprbank-regs.h
deleted file mode 100644
index bcb5f086c1..0000000000
--- a/bsps/include/grlib/grgprbank-regs.h
+++ /dev/null
@@ -1,677 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSDeviceGRGPRBANK
- *
- * @brief This header file defines the GRGPRBANK register block interface.
- */
-
-/*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * This file is part of the RTEMS quality process and was automatically
- * generated. If you find something that needs to be fixed or
- * worded better please post a report or patch to an RTEMS mailing list
- * or raise a bug report:
- *
- * https://www.rtems.org/bugs.html
- *
- * For information on updating and regenerating please refer to the How-To
- * section in the Software Requirements Engineering chapter of the
- * RTEMS Software Engineering manual. The manual is provided as a part of
- * a release. For development sources please refer to the online
- * documentation at:
- *
- * https://docs.rtems.org
- */
-
-/* Generated from spec:/dev/grlib/if/grgprbank-header */
-
-#ifndef _GRLIB_GRGPRBANK_REGS_H
-#define _GRLIB_GRGPRBANK_REGS_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Generated from spec:/dev/grlib/if/grgprbank */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANK GPRBANK
- *
- * @ingroup RTEMSDeviceGRLIB
- *
- * @brief This group contains the GPRBANK interfaces.
- *
- * @{
- */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKFTMFUNC \
- * FTMCTRL function enable register (FTMFUNC)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_FTMFUNC_FTMEN_SHIFT 0
-#define GRGPRBANK_FTMFUNC_FTMEN_MASK 0x3fffffU
-#define GRGPRBANK_FTMFUNC_FTMEN_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_FTMFUNC_FTMEN_MASK ) >> \
- GRGPRBANK_FTMFUNC_FTMEN_SHIFT )
-#define GRGPRBANK_FTMFUNC_FTMEN_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_FTMFUNC_FTMEN_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_FTMFUNC_FTMEN_SHIFT ) & \
- GRGPRBANK_FTMFUNC_FTMEN_MASK ) )
-#define GRGPRBANK_FTMFUNC_FTMEN( _val ) \
- ( ( ( _val ) << GRGPRBANK_FTMFUNC_FTMEN_SHIFT ) & \
- GRGPRBANK_FTMFUNC_FTMEN_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKALTFUNC \
- * Alternative function enable register (ALTFUNC)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_ALTFUNC_ALTEN_SHIFT 0
-#define GRGPRBANK_ALTFUNC_ALTEN_MASK 0x3fffffU
-#define GRGPRBANK_ALTFUNC_ALTEN_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_ALTFUNC_ALTEN_MASK ) >> \
- GRGPRBANK_ALTFUNC_ALTEN_SHIFT )
-#define GRGPRBANK_ALTFUNC_ALTEN_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_ALTFUNC_ALTEN_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_ALTFUNC_ALTEN_SHIFT ) & \
- GRGPRBANK_ALTFUNC_ALTEN_MASK ) )
-#define GRGPRBANK_ALTFUNC_ALTEN( _val ) \
- ( ( ( _val ) << GRGPRBANK_ALTFUNC_ALTEN_SHIFT ) & \
- GRGPRBANK_ALTFUNC_ALTEN_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKLVDSMCLK \
- * LVDS and memory clock pad enable register (LVDSMCLK)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_LVDSMCLK_SMEM 0x20000U
-
-#define GRGPRBANK_LVDSMCLK_DMEM 0x10000U
-
-#define GRGPRBANK_LVDSMCLK_SPWOE_SHIFT 0
-#define GRGPRBANK_LVDSMCLK_SPWOE_MASK 0xffU
-#define GRGPRBANK_LVDSMCLK_SPWOE_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_LVDSMCLK_SPWOE_MASK ) >> \
- GRGPRBANK_LVDSMCLK_SPWOE_SHIFT )
-#define GRGPRBANK_LVDSMCLK_SPWOE_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_LVDSMCLK_SPWOE_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_LVDSMCLK_SPWOE_SHIFT ) & \
- GRGPRBANK_LVDSMCLK_SPWOE_MASK ) )
-#define GRGPRBANK_LVDSMCLK_SPWOE( _val ) \
- ( ( ( _val ) << GRGPRBANK_LVDSMCLK_SPWOE_SHIFT ) & \
- GRGPRBANK_LVDSMCLK_SPWOE_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKPLLNEWCFG \
- * PLL new configuration register (PLLNEWCFG)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_PLLNEWCFG_SWTAG_SHIFT 27
-#define GRGPRBANK_PLLNEWCFG_SWTAG_MASK 0x18000000U
-#define GRGPRBANK_PLLNEWCFG_SWTAG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLNEWCFG_SWTAG_MASK ) >> \
- GRGPRBANK_PLLNEWCFG_SWTAG_SHIFT )
-#define GRGPRBANK_PLLNEWCFG_SWTAG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLNEWCFG_SWTAG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SWTAG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SWTAG_MASK ) )
-#define GRGPRBANK_PLLNEWCFG_SWTAG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SWTAG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SWTAG_MASK )
-
-#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SHIFT 18
-#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U
-#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK ) >> \
- GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SHIFT )
-#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK ) )
-#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK )
-
-#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SHIFT 9
-#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U
-#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK ) >> \
- GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SHIFT )
-#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK ) )
-#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK )
-
-#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SHIFT 0
-#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU
-#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK ) >> \
- GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SHIFT )
-#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK ) )
-#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKPLLRECFG \
- * PLL reconfigure command register (PLLRECFG)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_PLLRECFG_RECONF_SHIFT 0
-#define GRGPRBANK_PLLRECFG_RECONF_MASK 0x7U
-#define GRGPRBANK_PLLRECFG_RECONF_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLRECFG_RECONF_MASK ) >> \
- GRGPRBANK_PLLRECFG_RECONF_SHIFT )
-#define GRGPRBANK_PLLRECFG_RECONF_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLRECFG_RECONF_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLRECFG_RECONF_SHIFT ) & \
- GRGPRBANK_PLLRECFG_RECONF_MASK ) )
-#define GRGPRBANK_PLLRECFG_RECONF( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLRECFG_RECONF_SHIFT ) & \
- GRGPRBANK_PLLRECFG_RECONF_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKPLLCURCFG \
- * PLL current configuration register (PLLCURCFG)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_PLLCURCFG_SWTAG_SHIFT 27
-#define GRGPRBANK_PLLCURCFG_SWTAG_MASK 0x18000000U
-#define GRGPRBANK_PLLCURCFG_SWTAG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLCURCFG_SWTAG_MASK ) >> \
- GRGPRBANK_PLLCURCFG_SWTAG_SHIFT )
-#define GRGPRBANK_PLLCURCFG_SWTAG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLCURCFG_SWTAG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SWTAG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SWTAG_MASK ) )
-#define GRGPRBANK_PLLCURCFG_SWTAG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SWTAG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SWTAG_MASK )
-
-#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_SHIFT 18
-#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U
-#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK ) >> \
- GRGPRBANK_PLLCURCFG_SPWPLLCFG_SHIFT )
-#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK ) )
-#define GRGPRBANK_PLLCURCFG_SPWPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK )
-
-#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_SHIFT 9
-#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U
-#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK ) >> \
- GRGPRBANK_PLLCURCFG_MEMPLLCFG_SHIFT )
-#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK ) )
-#define GRGPRBANK_PLLCURCFG_MEMPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK )
-
-#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_SHIFT 0
-#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU
-#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK ) >> \
- GRGPRBANK_PLLCURCFG_SYSPLLCFG_SHIFT )
-#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK ) )
-#define GRGPRBANK_PLLCURCFG_SYSPLLCFG( _val ) \
- ( ( ( _val ) << GRGPRBANK_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
- GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKDRVSTR1 \
- * Drive strength configuration register 1 (DRVSTR1)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_DRVSTR1_S9_SHIFT 18
-#define GRGPRBANK_DRVSTR1_S9_MASK 0xc0000U
-#define GRGPRBANK_DRVSTR1_S9_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S9_MASK ) >> \
- GRGPRBANK_DRVSTR1_S9_SHIFT )
-#define GRGPRBANK_DRVSTR1_S9_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S9_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S9_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S9_MASK ) )
-#define GRGPRBANK_DRVSTR1_S9( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S9_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S9_MASK )
-
-#define GRGPRBANK_DRVSTR1_S8_SHIFT 16
-#define GRGPRBANK_DRVSTR1_S8_MASK 0x30000U
-#define GRGPRBANK_DRVSTR1_S8_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S8_MASK ) >> \
- GRGPRBANK_DRVSTR1_S8_SHIFT )
-#define GRGPRBANK_DRVSTR1_S8_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S8_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S8_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S8_MASK ) )
-#define GRGPRBANK_DRVSTR1_S8( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S8_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S8_MASK )
-
-#define GRGPRBANK_DRVSTR1_S7_SHIFT 14
-#define GRGPRBANK_DRVSTR1_S7_MASK 0xc000U
-#define GRGPRBANK_DRVSTR1_S7_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S7_MASK ) >> \
- GRGPRBANK_DRVSTR1_S7_SHIFT )
-#define GRGPRBANK_DRVSTR1_S7_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S7_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S7_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S7_MASK ) )
-#define GRGPRBANK_DRVSTR1_S7( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S7_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S7_MASK )
-
-#define GRGPRBANK_DRVSTR1_S6_SHIFT 12
-#define GRGPRBANK_DRVSTR1_S6_MASK 0x3000U
-#define GRGPRBANK_DRVSTR1_S6_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S6_MASK ) >> \
- GRGPRBANK_DRVSTR1_S6_SHIFT )
-#define GRGPRBANK_DRVSTR1_S6_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S6_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S6_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S6_MASK ) )
-#define GRGPRBANK_DRVSTR1_S6( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S6_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S6_MASK )
-
-#define GRGPRBANK_DRVSTR1_S5_SHIFT 10
-#define GRGPRBANK_DRVSTR1_S5_MASK 0xc00U
-#define GRGPRBANK_DRVSTR1_S5_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S5_MASK ) >> \
- GRGPRBANK_DRVSTR1_S5_SHIFT )
-#define GRGPRBANK_DRVSTR1_S5_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S5_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S5_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S5_MASK ) )
-#define GRGPRBANK_DRVSTR1_S5( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S5_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S5_MASK )
-
-#define GRGPRBANK_DRVSTR1_S4_SHIFT 8
-#define GRGPRBANK_DRVSTR1_S4_MASK 0x300U
-#define GRGPRBANK_DRVSTR1_S4_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S4_MASK ) >> \
- GRGPRBANK_DRVSTR1_S4_SHIFT )
-#define GRGPRBANK_DRVSTR1_S4_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S4_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S4_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S4_MASK ) )
-#define GRGPRBANK_DRVSTR1_S4( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S4_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S4_MASK )
-
-#define GRGPRBANK_DRVSTR1_S3_SHIFT 6
-#define GRGPRBANK_DRVSTR1_S3_MASK 0xc0U
-#define GRGPRBANK_DRVSTR1_S3_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S3_MASK ) >> \
- GRGPRBANK_DRVSTR1_S3_SHIFT )
-#define GRGPRBANK_DRVSTR1_S3_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S3_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S3_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S3_MASK ) )
-#define GRGPRBANK_DRVSTR1_S3( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S3_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S3_MASK )
-
-#define GRGPRBANK_DRVSTR1_S2_SHIFT 4
-#define GRGPRBANK_DRVSTR1_S2_MASK 0x30U
-#define GRGPRBANK_DRVSTR1_S2_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S2_MASK ) >> \
- GRGPRBANK_DRVSTR1_S2_SHIFT )
-#define GRGPRBANK_DRVSTR1_S2_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S2_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S2_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S2_MASK ) )
-#define GRGPRBANK_DRVSTR1_S2( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S2_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S2_MASK )
-
-#define GRGPRBANK_DRVSTR1_S1_SHIFT 2
-#define GRGPRBANK_DRVSTR1_S1_MASK 0xcU
-#define GRGPRBANK_DRVSTR1_S1_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S1_MASK ) >> \
- GRGPRBANK_DRVSTR1_S1_SHIFT )
-#define GRGPRBANK_DRVSTR1_S1_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S1_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S1_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S1_MASK ) )
-#define GRGPRBANK_DRVSTR1_S1( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S1_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S1_MASK )
-
-#define GRGPRBANK_DRVSTR1_S0_SHIFT 0
-#define GRGPRBANK_DRVSTR1_S0_MASK 0x3U
-#define GRGPRBANK_DRVSTR1_S0_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR1_S0_MASK ) >> \
- GRGPRBANK_DRVSTR1_S0_SHIFT )
-#define GRGPRBANK_DRVSTR1_S0_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR1_S0_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S0_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S0_MASK ) )
-#define GRGPRBANK_DRVSTR1_S0( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR1_S0_SHIFT ) & \
- GRGPRBANK_DRVSTR1_S0_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKDRVSTR2 \
- * Drive strength configuration register 2 (DRVSTR2)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_DRVSTR2_S19_SHIFT 18
-#define GRGPRBANK_DRVSTR2_S19_MASK 0xc0000U
-#define GRGPRBANK_DRVSTR2_S19_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S19_MASK ) >> \
- GRGPRBANK_DRVSTR2_S19_SHIFT )
-#define GRGPRBANK_DRVSTR2_S19_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S19_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S19_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S19_MASK ) )
-#define GRGPRBANK_DRVSTR2_S19( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S19_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S19_MASK )
-
-#define GRGPRBANK_DRVSTR2_S18_SHIFT 16
-#define GRGPRBANK_DRVSTR2_S18_MASK 0x30000U
-#define GRGPRBANK_DRVSTR2_S18_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S18_MASK ) >> \
- GRGPRBANK_DRVSTR2_S18_SHIFT )
-#define GRGPRBANK_DRVSTR2_S18_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S18_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S18_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S18_MASK ) )
-#define GRGPRBANK_DRVSTR2_S18( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S18_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S18_MASK )
-
-#define GRGPRBANK_DRVSTR2_S17_SHIFT 14
-#define GRGPRBANK_DRVSTR2_S17_MASK 0xc000U
-#define GRGPRBANK_DRVSTR2_S17_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S17_MASK ) >> \
- GRGPRBANK_DRVSTR2_S17_SHIFT )
-#define GRGPRBANK_DRVSTR2_S17_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S17_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S17_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S17_MASK ) )
-#define GRGPRBANK_DRVSTR2_S17( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S17_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S17_MASK )
-
-#define GRGPRBANK_DRVSTR2_S16_SHIFT 12
-#define GRGPRBANK_DRVSTR2_S16_MASK 0x3000U
-#define GRGPRBANK_DRVSTR2_S16_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S16_MASK ) >> \
- GRGPRBANK_DRVSTR2_S16_SHIFT )
-#define GRGPRBANK_DRVSTR2_S16_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S16_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S16_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S16_MASK ) )
-#define GRGPRBANK_DRVSTR2_S16( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S16_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S16_MASK )
-
-#define GRGPRBANK_DRVSTR2_S15_SHIFT 10
-#define GRGPRBANK_DRVSTR2_S15_MASK 0xc00U
-#define GRGPRBANK_DRVSTR2_S15_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S15_MASK ) >> \
- GRGPRBANK_DRVSTR2_S15_SHIFT )
-#define GRGPRBANK_DRVSTR2_S15_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S15_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S15_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S15_MASK ) )
-#define GRGPRBANK_DRVSTR2_S15( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S15_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S15_MASK )
-
-#define GRGPRBANK_DRVSTR2_S14_SHIFT 8
-#define GRGPRBANK_DRVSTR2_S14_MASK 0x300U
-#define GRGPRBANK_DRVSTR2_S14_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S14_MASK ) >> \
- GRGPRBANK_DRVSTR2_S14_SHIFT )
-#define GRGPRBANK_DRVSTR2_S14_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S14_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S14_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S14_MASK ) )
-#define GRGPRBANK_DRVSTR2_S14( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S14_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S14_MASK )
-
-#define GRGPRBANK_DRVSTR2_S13_SHIFT 6
-#define GRGPRBANK_DRVSTR2_S13_MASK 0xc0U
-#define GRGPRBANK_DRVSTR2_S13_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S13_MASK ) >> \
- GRGPRBANK_DRVSTR2_S13_SHIFT )
-#define GRGPRBANK_DRVSTR2_S13_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S13_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S13_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S13_MASK ) )
-#define GRGPRBANK_DRVSTR2_S13( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S13_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S13_MASK )
-
-#define GRGPRBANK_DRVSTR2_S12_SHIFT 4
-#define GRGPRBANK_DRVSTR2_S12_MASK 0x30U
-#define GRGPRBANK_DRVSTR2_S12_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S12_MASK ) >> \
- GRGPRBANK_DRVSTR2_S12_SHIFT )
-#define GRGPRBANK_DRVSTR2_S12_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S12_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S12_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S12_MASK ) )
-#define GRGPRBANK_DRVSTR2_S12( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S12_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S12_MASK )
-
-#define GRGPRBANK_DRVSTR2_S11_SHIFT 2
-#define GRGPRBANK_DRVSTR2_S11_MASK 0xcU
-#define GRGPRBANK_DRVSTR2_S11_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S11_MASK ) >> \
- GRGPRBANK_DRVSTR2_S11_SHIFT )
-#define GRGPRBANK_DRVSTR2_S11_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S11_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S11_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S11_MASK ) )
-#define GRGPRBANK_DRVSTR2_S11( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S11_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S11_MASK )
-
-#define GRGPRBANK_DRVSTR2_S10_SHIFT 0
-#define GRGPRBANK_DRVSTR2_S10_MASK 0x3U
-#define GRGPRBANK_DRVSTR2_S10_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_DRVSTR2_S10_MASK ) >> \
- GRGPRBANK_DRVSTR2_S10_SHIFT )
-#define GRGPRBANK_DRVSTR2_S10_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_DRVSTR2_S10_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S10_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S10_MASK ) )
-#define GRGPRBANK_DRVSTR2_S10( _val ) \
- ( ( ( _val ) << GRGPRBANK_DRVSTR2_S10_SHIFT ) & \
- GRGPRBANK_DRVSTR2_S10_MASK )
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRGPRBANKLOCKDOWN \
- * Configuration lockdown register (LOCKDOWN)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRGPRBANK_LOCKDOWN_PERMANENT_SHIFT 16
-#define GRGPRBANK_LOCKDOWN_PERMANENT_MASK 0xff0000U
-#define GRGPRBANK_LOCKDOWN_PERMANENT_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_LOCKDOWN_PERMANENT_MASK ) >> \
- GRGPRBANK_LOCKDOWN_PERMANENT_SHIFT )
-#define GRGPRBANK_LOCKDOWN_PERMANENT_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_LOCKDOWN_PERMANENT_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_LOCKDOWN_PERMANENT_SHIFT ) & \
- GRGPRBANK_LOCKDOWN_PERMANENT_MASK ) )
-#define GRGPRBANK_LOCKDOWN_PERMANENT( _val ) \
- ( ( ( _val ) << GRGPRBANK_LOCKDOWN_PERMANENT_SHIFT ) & \
- GRGPRBANK_LOCKDOWN_PERMANENT_MASK )
-
-#define GRGPRBANK_LOCKDOWN_REVOCABLE_SHIFT 0
-#define GRGPRBANK_LOCKDOWN_REVOCABLE_MASK 0xffU
-#define GRGPRBANK_LOCKDOWN_REVOCABLE_GET( _reg ) \
- ( ( ( _reg ) & GRGPRBANK_LOCKDOWN_REVOCABLE_MASK ) >> \
- GRGPRBANK_LOCKDOWN_REVOCABLE_SHIFT )
-#define GRGPRBANK_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPRBANK_LOCKDOWN_REVOCABLE_MASK ) | \
- ( ( ( _val ) << GRGPRBANK_LOCKDOWN_REVOCABLE_SHIFT ) & \
- GRGPRBANK_LOCKDOWN_REVOCABLE_MASK ) )
-#define GRGPRBANK_LOCKDOWN_REVOCABLE( _val ) \
- ( ( ( _val ) << GRGPRBANK_LOCKDOWN_REVOCABLE_SHIFT ) & \
- GRGPRBANK_LOCKDOWN_REVOCABLE_MASK )
-
-/** @} */
-
-/**
- * @brief This structure defines the GPRBANK register block memory map.
- */
-typedef struct grgprbank {
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKFTMFUNC.
- */
- uint32_t ftmfunc;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKALTFUNC.
- */
- uint32_t altfunc;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKLVDSMCLK.
- */
- uint32_t lvdsmclk;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKPLLNEWCFG.
- */
- uint32_t pllnewcfg;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKPLLRECFG.
- */
- uint32_t pllrecfg;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKPLLCURCFG.
- */
- uint32_t pllcurcfg;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKDRVSTR1.
- */
- uint32_t drvstr1;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKDRVSTR2.
- */
- uint32_t drvstr2;
-
- /**
- * @brief See @ref RTEMSDeviceGRGPRBANKLOCKDOWN.
- */
- uint32_t lockdown;
-} grgprbank;
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _GRLIB_GRGPRBANK_REGS_H */
diff --git a/bsps/include/grlib/grgpreg-regs.h b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h
similarity index 53%
rename from bsps/include/grlib/grgpreg-regs.h
rename to bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h
index 852170018f..33fb71aaab 100644
--- a/bsps/include/grlib/grgpreg-regs.h
+++ b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h
@@ -3,13 +3,14 @@
/**
* @file
*
- * @ingroup RTEMSDeviceGRGPREG
+ * @ingroup RTEMSBSPsGR740Bootstrap
*
- * @brief This header file defines the GRGPREG register block interface.
+ * @brief This header file defines the GR740 Boostrap Signals register block
+ * interface.
*/
/*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -50,10 +51,10 @@
* https://docs.rtems.org
*/
-/* Generated from spec:/dev/grlib/if/grgpreg-header */
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap-header */
-#ifndef _GRLIB_GRGPREG_REGS_H
-#define _GRLIB_GRGPREG_REGS_H
+#ifndef _BSP_GR740_BOOTSTRAP_REGS_H
+#define _BSP_GR740_BOOTSTRAP_REGS_H
#include <stdint.h>
@@ -61,70 +62,71 @@
extern "C" {
#endif
-/* Generated from spec:/dev/grlib/if/grgpreg */
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap */
/**
- * @defgroup RTEMSDeviceGRGPREG GRGPREG
+ * @defgroup RTEMSBSPsGR740Bootstrap GR740 Bootstrap Signals
*
- * @ingroup RTEMSDeviceGRLIB
+ * @ingroup RTEMSBSPsSPARCLEON3
*
- * @brief This group contains the GRGPREG interfaces.
+ * @brief This group contains the GR740 Bootstrap Signals interfaces.
*
* @{
*/
/**
- * @defgroup RTEMSDeviceGRGPREGBOOTSTRAP Bootstrap register (BOOTSTRAP)
+ * @defgroup RTEMSBSPsGR740BootstrapBOOTSTRAP Bootstrap register (BOOTSTRAP)
*
* @brief This group contains register bit definitions.
*
* @{
*/
-#define GRGPREG_BOOTSTRAP_B10 0x2000000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B10 0x2000000U
-#define GRGPREG_BOOTSTRAP_B9 0x1000000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B9 0x1000000U
-#define GRGPREG_BOOTSTRAP_B8 0x800000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B8 0x800000U
-#define GRGPREG_BOOTSTRAP_B7 0x400000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B7 0x400000U
-#define GRGPREG_BOOTSTRAP_B6 0x200000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B6 0x200000U
-#define GRGPREG_BOOTSTRAP_B5 0x100000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B5 0x100000U
-#define GRGPREG_BOOTSTRAP_B4 0x80000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B4 0x80000U
-#define GRGPREG_BOOTSTRAP_B3 0x40000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B3 0x40000U
-#define GRGPREG_BOOTSTRAP_B2 0x20000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B2 0x20000U
-#define GRGPREG_BOOTSTRAP_B1 0x10000U
+#define GR740_BOOTSTRAP_BOOTSTRAP_B1 0x10000U
-#define GRGPREG_BOOTSTRAP_GPIO_SHIFT 0
-#define GRGPREG_BOOTSTRAP_GPIO_MASK 0xffffU
-#define GRGPREG_BOOTSTRAP_GPIO_GET( _reg ) \
- ( ( ( _reg ) & GRGPREG_BOOTSTRAP_GPIO_MASK ) >> \
- GRGPREG_BOOTSTRAP_GPIO_SHIFT )
-#define GRGPREG_BOOTSTRAP_GPIO_SET( _reg, _val ) \
- ( ( ( _reg ) & ~GRGPREG_BOOTSTRAP_GPIO_MASK ) | \
- ( ( ( _val ) << GRGPREG_BOOTSTRAP_GPIO_SHIFT ) & \
- GRGPREG_BOOTSTRAP_GPIO_MASK ) )
-#define GRGPREG_BOOTSTRAP_GPIO( _val ) \
- ( ( ( _val ) << GRGPREG_BOOTSTRAP_GPIO_SHIFT ) & \
- GRGPREG_BOOTSTRAP_GPIO_MASK )
+#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT 0
+#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK 0xffffU
+#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_GET( _reg ) \
+ ( ( ( _reg ) & GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) >> \
+ GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT )
+#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) | \
+ ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \
+ GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) )
+#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO( _val ) \
+ ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \
+ GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK )
/** @} */
/**
- * @brief This structure defines the GRGPREG register block memory map.
+ * @brief This structure defines the GR740 Bootstrap Signals register block
+ * memory map.
*/
-typedef struct grgpreg {
+typedef struct gr740_bootstrap {
/**
- * @brief See @ref RTEMSDeviceGRGPREGBOOTSTRAP.
+ * @brief See @ref RTEMSBSPsGR740BootstrapBOOTSTRAP.
*/
uint32_t bootstrap;
-} grgpreg;
+} gr740_bootstrap;
/** @} */
@@ -132,4 +134,4 @@ typedef struct grgpreg {
}
#endif
-#endif /* _GRLIB_GRGPREG_REGS_H */
+#endif /* _BSP_GR740_BOOTSTRAP_REGS_H */
diff --git a/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h
new file mode 100644
index 0000000000..1614ebba8a
--- /dev/null
+++ b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h
@@ -0,0 +1,679 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsGR740IOPLL
+ *
+ * @brief This header file defines the GR740 I/O and PLL configuration register
+ * block interface.
+ */
+
+/*
+ * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll-header */
+
+#ifndef _BSP_GR740_IOPLL_REGS_H
+#define _BSP_GR740_IOPLL_REGS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLL GR740 I/0 and PLL Configuration
+ *
+ * @ingroup RTEMSBSPsSPARCLEON3
+ *
+ * @brief This group contains the GR740 I/0 and PLL Configuration interfaces.
+ *
+ * @{
+ */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLFTMFUNC \
+ * FTMCTRL function enable register (FTMFUNC)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_FTMFUNC_FTMEN_SHIFT 0
+#define GR740_IOPLL_FTMFUNC_FTMEN_MASK 0x3fffffU
+#define GR740_IOPLL_FTMFUNC_FTMEN_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_FTMFUNC_FTMEN_MASK ) >> \
+ GR740_IOPLL_FTMFUNC_FTMEN_SHIFT )
+#define GR740_IOPLL_FTMFUNC_FTMEN_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_FTMFUNC_FTMEN_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
+ GR740_IOPLL_FTMFUNC_FTMEN_MASK ) )
+#define GR740_IOPLL_FTMFUNC_FTMEN( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
+ GR740_IOPLL_FTMFUNC_FTMEN_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLALTFUNC \
+ * Alternative function enable register (ALTFUNC)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_ALTFUNC_ALTEN_SHIFT 0
+#define GR740_IOPLL_ALTFUNC_ALTEN_MASK 0x3fffffU
+#define GR740_IOPLL_ALTFUNC_ALTEN_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_ALTFUNC_ALTEN_MASK ) >> \
+ GR740_IOPLL_ALTFUNC_ALTEN_SHIFT )
+#define GR740_IOPLL_ALTFUNC_ALTEN_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_ALTFUNC_ALTEN_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
+ GR740_IOPLL_ALTFUNC_ALTEN_MASK ) )
+#define GR740_IOPLL_ALTFUNC_ALTEN( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
+ GR740_IOPLL_ALTFUNC_ALTEN_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLLVDSMCLK \
+ * LVDS and memory clock pad enable register (LVDSMCLK)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_LVDSMCLK_SMEM 0x20000U
+
+#define GR740_IOPLL_LVDSMCLK_DMEM 0x10000U
+
+#define GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT 0
+#define GR740_IOPLL_LVDSMCLK_SPWOE_MASK 0xffU
+#define GR740_IOPLL_LVDSMCLK_SPWOE_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \
+ GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT )
+#define GR740_IOPLL_LVDSMCLK_SPWOE_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
+ GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) )
+#define GR740_IOPLL_LVDSMCLK_SPWOE( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
+ GR740_IOPLL_LVDSMCLK_SPWOE_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLPLLNEWCFG \
+ * PLL new configuration register (PLLNEWCFG)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27
+#define GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U
+#define GR740_IOPLL_PLLNEWCFG_SWTAG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) >> \
+ GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT )
+#define GR740_IOPLL_PLLNEWCFG_SWTAG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) )
+#define GR740_IOPLL_PLLNEWCFG_SWTAG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SWTAG_MASK )
+
+#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18
+#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U
+#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK )
+
+#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9
+#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U
+#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK )
+
+#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0
+#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU
+#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLPLLRECFG \
+ * PLL reconfigure command register (PLLRECFG)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_PLLRECFG_RECONF_SHIFT 0
+#define GR740_IOPLL_PLLRECFG_RECONF_MASK 0x7U
+#define GR740_IOPLL_PLLRECFG_RECONF_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLRECFG_RECONF_MASK ) >> \
+ GR740_IOPLL_PLLRECFG_RECONF_SHIFT )
+#define GR740_IOPLL_PLLRECFG_RECONF_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLRECFG_RECONF_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
+ GR740_IOPLL_PLLRECFG_RECONF_MASK ) )
+#define GR740_IOPLL_PLLRECFG_RECONF( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
+ GR740_IOPLL_PLLRECFG_RECONF_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLPLLCURCFG \
+ * PLL current configuration register (PLLCURCFG)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT 27
+#define GR740_IOPLL_PLLCURCFG_SWTAG_MASK 0x18000000U
+#define GR740_IOPLL_PLLCURCFG_SWTAG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) >> \
+ GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT )
+#define GR740_IOPLL_PLLCURCFG_SWTAG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) )
+#define GR740_IOPLL_PLLCURCFG_SWTAG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SWTAG_MASK )
+
+#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT 18
+#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U
+#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK )
+
+#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT 9
+#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U
+#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK )
+
+#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT 0
+#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU
+#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) >> \
+ GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT )
+#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) )
+#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
+ GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLDRVSTR1 \
+ * Drive strength configuration register 1 (DRVSTR1)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_DRVSTR1_S9_SHIFT 18
+#define GR740_IOPLL_DRVSTR1_S9_MASK 0xc0000U
+#define GR740_IOPLL_DRVSTR1_S9_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S9_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S9_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S9_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S9( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S9_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S8_SHIFT 16
+#define GR740_IOPLL_DRVSTR1_S8_MASK 0x30000U
+#define GR740_IOPLL_DRVSTR1_S8_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S8_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S8_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S8_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S8( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S8_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S7_SHIFT 14
+#define GR740_IOPLL_DRVSTR1_S7_MASK 0xc000U
+#define GR740_IOPLL_DRVSTR1_S7_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S7_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S7_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S7_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S7( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S7_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S6_SHIFT 12
+#define GR740_IOPLL_DRVSTR1_S6_MASK 0x3000U
+#define GR740_IOPLL_DRVSTR1_S6_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S6_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S6_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S6_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S6( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S6_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S5_SHIFT 10
+#define GR740_IOPLL_DRVSTR1_S5_MASK 0xc00U
+#define GR740_IOPLL_DRVSTR1_S5_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S5_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S5_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S5_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S5( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S5_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S4_SHIFT 8
+#define GR740_IOPLL_DRVSTR1_S4_MASK 0x300U
+#define GR740_IOPLL_DRVSTR1_S4_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S4_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S4_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S4_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S4( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S4_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S3_SHIFT 6
+#define GR740_IOPLL_DRVSTR1_S3_MASK 0xc0U
+#define GR740_IOPLL_DRVSTR1_S3_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S3_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S3_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S3_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S3( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S3_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S2_SHIFT 4
+#define GR740_IOPLL_DRVSTR1_S2_MASK 0x30U
+#define GR740_IOPLL_DRVSTR1_S2_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S2_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S2_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S2_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S2( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S2_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S1_SHIFT 2
+#define GR740_IOPLL_DRVSTR1_S1_MASK 0xcU
+#define GR740_IOPLL_DRVSTR1_S1_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S1_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S1_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S1_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S1( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S1_MASK )
+
+#define GR740_IOPLL_DRVSTR1_S0_SHIFT 0
+#define GR740_IOPLL_DRVSTR1_S0_MASK 0x3U
+#define GR740_IOPLL_DRVSTR1_S0_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \
+ GR740_IOPLL_DRVSTR1_S0_SHIFT )
+#define GR740_IOPLL_DRVSTR1_S0_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S0_MASK ) )
+#define GR740_IOPLL_DRVSTR1_S0( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
+ GR740_IOPLL_DRVSTR1_S0_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLDRVSTR2 \
+ * Drive strength configuration register 2 (DRVSTR2)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_DRVSTR2_S19_SHIFT 18
+#define GR740_IOPLL_DRVSTR2_S19_MASK 0xc0000U
+#define GR740_IOPLL_DRVSTR2_S19_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S19_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S19_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S19_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S19_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S19_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S19( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S19_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S18_SHIFT 16
+#define GR740_IOPLL_DRVSTR2_S18_MASK 0x30000U
+#define GR740_IOPLL_DRVSTR2_S18_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S18_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S18_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S18_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S18_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S18_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S18( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S18_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S17_SHIFT 14
+#define GR740_IOPLL_DRVSTR2_S17_MASK 0xc000U
+#define GR740_IOPLL_DRVSTR2_S17_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S17_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S17_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S17_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S17_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S17_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S17( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S17_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S16_SHIFT 12
+#define GR740_IOPLL_DRVSTR2_S16_MASK 0x3000U
+#define GR740_IOPLL_DRVSTR2_S16_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S16_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S16_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S16_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S16_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S16_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S16( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S16_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S15_SHIFT 10
+#define GR740_IOPLL_DRVSTR2_S15_MASK 0xc00U
+#define GR740_IOPLL_DRVSTR2_S15_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S15_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S15_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S15_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S15_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S15_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S15( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S15_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S14_SHIFT 8
+#define GR740_IOPLL_DRVSTR2_S14_MASK 0x300U
+#define GR740_IOPLL_DRVSTR2_S14_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S14_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S14_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S14_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S14_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S14_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S14( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S14_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S13_SHIFT 6
+#define GR740_IOPLL_DRVSTR2_S13_MASK 0xc0U
+#define GR740_IOPLL_DRVSTR2_S13_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S13_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S13_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S13_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S13_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S13_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S13( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S13_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S12_SHIFT 4
+#define GR740_IOPLL_DRVSTR2_S12_MASK 0x30U
+#define GR740_IOPLL_DRVSTR2_S12_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S12_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S12_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S12_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S12_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S12_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S12( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S12_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S11_SHIFT 2
+#define GR740_IOPLL_DRVSTR2_S11_MASK 0xcU
+#define GR740_IOPLL_DRVSTR2_S11_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S11_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S11_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S11_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S11_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S11_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S11( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S11_MASK )
+
+#define GR740_IOPLL_DRVSTR2_S10_SHIFT 0
+#define GR740_IOPLL_DRVSTR2_S10_MASK 0x3U
+#define GR740_IOPLL_DRVSTR2_S10_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S10_MASK ) >> \
+ GR740_IOPLL_DRVSTR2_S10_SHIFT )
+#define GR740_IOPLL_DRVSTR2_S10_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S10_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S10_MASK ) )
+#define GR740_IOPLL_DRVSTR2_S10( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
+ GR740_IOPLL_DRVSTR2_S10_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740IOPLLLOCKDOWN \
+ * Configuration lockdown register (LOCKDOWN)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT 16
+#define GR740_IOPLL_LOCKDOWN_PERMANENT_MASK 0xff0000U
+#define GR740_IOPLL_LOCKDOWN_PERMANENT_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) >> \
+ GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT )
+#define GR740_IOPLL_LOCKDOWN_PERMANENT_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
+ GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) )
+#define GR740_IOPLL_LOCKDOWN_PERMANENT( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
+ GR740_IOPLL_LOCKDOWN_PERMANENT_MASK )
+
+#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT 0
+#define GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK 0xffU
+#define GR740_IOPLL_LOCKDOWN_REVOCABLE_GET( _reg ) \
+ ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) >> \
+ GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT )
+#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) | \
+ ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
+ GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) )
+#define GR740_IOPLL_LOCKDOWN_REVOCABLE( _val ) \
+ ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
+ GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK )
+
+/** @} */
+
+/**
+ * @brief This structure defines the GR740 I/0 and PLL Configuration register
+ * block memory map.
+ */
+typedef struct gr740_iopll {
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLFTMFUNC.
+ */
+ uint32_t ftmfunc;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLALTFUNC.
+ */
+ uint32_t altfunc;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLLVDSMCLK.
+ */
+ uint32_t lvdsmclk;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLPLLNEWCFG.
+ */
+ uint32_t pllnewcfg;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLPLLRECFG.
+ */
+ uint32_t pllrecfg;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLPLLCURCFG.
+ */
+ uint32_t pllcurcfg;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR1.
+ */
+ uint32_t drvstr1;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR2.
+ */
+ uint32_t drvstr2;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740IOPLLLOCKDOWN.
+ */
+ uint32_t lockdown;
+} gr740_iopll;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BSP_GR740_IOPLL_REGS_H */
diff --git a/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h
new file mode 100644
index 0000000000..54f33adaee
--- /dev/null
+++ b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsGR740ThSens
+ *
+ * @brief This header file defines the GR740 Temperatur Sensor Controller
+ * register block interface.
+ */
+
+/*
+ * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens-header */
+
+#ifndef _BSP_GR740_THSENS_REGS_H
+#define _BSP_GR740_THSENS_REGS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens */
+
+/**
+ * @defgroup RTEMSBSPsGR740ThSens GR740 Temperatur Sensor Controller
+ *
+ * @ingroup RTEMSBSPsSPARCLEON3
+ *
+ * @brief This group contains the GR740 Temperatur Sensor Controller
+ * interfaces.
+ *
+ * @{
+ */
+
+/**
+ * @defgroup RTEMSBSPsGR740ThSensCTRL Control register (CTRL)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_THSENS_CTRL_DIV_SHIFT 16
+#define GR740_THSENS_CTRL_DIV_MASK 0x3ff0000U
+#define GR740_THSENS_CTRL_DIV_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_CTRL_DIV_MASK ) >> \
+ GR740_THSENS_CTRL_DIV_SHIFT )
+#define GR740_THSENS_CTRL_DIV_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_CTRL_DIV_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \
+ GR740_THSENS_CTRL_DIV_MASK ) )
+#define GR740_THSENS_CTRL_DIV( _val ) \
+ ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \
+ GR740_THSENS_CTRL_DIV_MASK )
+
+#define GR740_THSENS_CTRL_ALEN 0x100U
+
+#define GR740_THSENS_CTRL_PDN 0x80U
+
+#define GR740_THSENS_CTRL_DCORRECT_SHIFT 2
+#define GR740_THSENS_CTRL_DCORRECT_MASK 0x7cU
+#define GR740_THSENS_CTRL_DCORRECT_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_CTRL_DCORRECT_MASK ) >> \
+ GR740_THSENS_CTRL_DCORRECT_SHIFT )
+#define GR740_THSENS_CTRL_DCORRECT_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_CTRL_DCORRECT_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \
+ GR740_THSENS_CTRL_DCORRECT_MASK ) )
+#define GR740_THSENS_CTRL_DCORRECT( _val ) \
+ ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \
+ GR740_THSENS_CTRL_DCORRECT_MASK )
+
+#define GR740_THSENS_CTRL_SRSTN 0x2U
+
+#define GR740_THSENS_CTRL_CLKEN 0x1U
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740ThSensSTATUS Status register (STATUS)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_THSENS_STATUS_MAX_SHIFT 24
+#define GR740_THSENS_STATUS_MAX_MASK 0x7f000000U
+#define GR740_THSENS_STATUS_MAX_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_STATUS_MAX_MASK ) >> \
+ GR740_THSENS_STATUS_MAX_SHIFT )
+#define GR740_THSENS_STATUS_MAX_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_STATUS_MAX_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \
+ GR740_THSENS_STATUS_MAX_MASK ) )
+#define GR740_THSENS_STATUS_MAX( _val ) \
+ ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \
+ GR740_THSENS_STATUS_MAX_MASK )
+
+#define GR740_THSENS_STATUS_MIN_SHIFT 16
+#define GR740_THSENS_STATUS_MIN_MASK 0x7f0000U
+#define GR740_THSENS_STATUS_MIN_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_STATUS_MIN_MASK ) >> \
+ GR740_THSENS_STATUS_MIN_SHIFT )
+#define GR740_THSENS_STATUS_MIN_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_STATUS_MIN_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \
+ GR740_THSENS_STATUS_MIN_MASK ) )
+#define GR740_THSENS_STATUS_MIN( _val ) \
+ ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \
+ GR740_THSENS_STATUS_MIN_MASK )
+
+#define GR740_THSENS_STATUS_SCLK 0x8000U
+
+#define GR740_THSENS_STATUS_WE 0x400U
+
+#define GR740_THSENS_STATUS_UPD 0x200U
+
+#define GR740_THSENS_STATUS_ALACT 0x100U
+
+#define GR740_THSENS_STATUS_DATA_SHIFT 0
+#define GR740_THSENS_STATUS_DATA_MASK 0x7fU
+#define GR740_THSENS_STATUS_DATA_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_STATUS_DATA_MASK ) >> \
+ GR740_THSENS_STATUS_DATA_SHIFT )
+#define GR740_THSENS_STATUS_DATA_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_STATUS_DATA_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \
+ GR740_THSENS_STATUS_DATA_MASK ) )
+#define GR740_THSENS_STATUS_DATA( _val ) \
+ ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \
+ GR740_THSENS_STATUS_DATA_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSBSPsGR740ThSensTHRES Threshold register (THRES)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GR740_THSENS_THRES_THRES_SHIFT 0
+#define GR740_THSENS_THRES_THRES_MASK 0x7fU
+#define GR740_THSENS_THRES_THRES_GET( _reg ) \
+ ( ( ( _reg ) & GR740_THSENS_THRES_THRES_MASK ) >> \
+ GR740_THSENS_THRES_THRES_SHIFT )
+#define GR740_THSENS_THRES_THRES_SET( _reg, _val ) \
+ ( ( ( _reg ) & ~GR740_THSENS_THRES_THRES_MASK ) | \
+ ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \
+ GR740_THSENS_THRES_THRES_MASK ) )
+#define GR740_THSENS_THRES_THRES( _val ) \
+ ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \
+ GR740_THSENS_THRES_THRES_MASK )
+
+/** @} */
+
+/**
+ * @brief This structure defines the GR740 Temperatur Sensor Controller
+ * register block memory map.
+ */
+typedef struct gr740_thsens {
+ /**
+ * @brief See @ref RTEMSBSPsGR740ThSensCTRL.
+ */
+ uint32_t ctrl;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740ThSensSTATUS.
+ */
+ uint32_t status;
+
+ /**
+ * @brief See @ref RTEMSBSPsGR740ThSensTHRES.
+ */
+ uint32_t thres;
+} gr740_thsens;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BSP_GR740_THSENS_REGS_H */
--
2.35.3
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