[PATCH rtems 3/6] imxrt/mcux-sdk: Add HREQ-related bits

[Christian Mauderer]

According to the reference manual the bits exist and they can be used.
Also confirmed by NXP support in the community forum:

https://community.nxp.com/t5/i-MX-RT/i-MXRT1160-LPSPI-HREQ-supported/m-p/1668647#M25512
---
 .../devices/MIMXRT1166/MIMXRT1166_cm7.h       | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h
index 64ce9ee126..1936e4c5de 100644
--- a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h
+++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h
@@ -60038,6 +60038,31 @@ typedef struct {
 
 /*! @name CFGR0 - Configuration 0 */
 /*! @{ */
+#ifdef __rtems__
+#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
+#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request is disabled
+ *  0b1..Host request is enabled
+ */
+#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
+
+#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
+#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..LPSPI_HREQ pin is active low
+ *  0b1..LPSPI_HREQ pin is active high
+ */
+#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
+
+#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
+#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is the LPSPI_HREQ pin
+ *  0b1..Host request input is the input trigger
+ */
+#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
+#endif /* __rtems__ */
 
 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
-- 
2.35.3