[PATCH rtems 6/6] bsps/imxrt: Add imxrt1166_cm7_saltshaker BSP
Christian Mauderer
christian.mauderer at embedded-brains.de
Thu Jul 13 13:42:23 UTC 2023
The BSP is for a custom i.MXRT1166 based board. At the moment, only the
cortex M7 is supported.
---
.../imxrt/boards/saltshaker/clock_config.c | 823 ++++++
.../imxrt/boards/saltshaker/clock_config.h | 35 +
bsps/arm/imxrt/boards/saltshaker/dcd.c | 310 +++
bsps/arm/imxrt/boards/saltshaker/dcd.h | 37 +
.../boards/saltshaker/flash-flexspi-config.c | 73 +
bsps/arm/imxrt/boards/saltshaker/pin_mux.c | 21 +
bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c | 2399 +++++++++++++++++
.../imxrt/dts/imxrt1166-cm7-saltshaker.dts | 296 ++
bsps/arm/imxrt/include/bsp/irq.h | 5 +
.../imxrt/include/imxrt/imxrt1166-pinfunc.h | 1607 +++++++++++
bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi | 1224 +++++++++
bsps/arm/imxrt/start/bspstart.c | 23 +
bsps/arm/imxrt/start/bspstarthooks.c | 4 +-
bsps/arm/imxrt/start/imxrt-ffec-init.c | 4 +
.../arm/imxrt/bspimxrt1166-cm7-saltshaker.yml | 32 +
spec/build/bsps/arm/imxrt/optmemdtcmsz.yml | 2 +
spec/build/bsps/arm/imxrt/optmemextramsz.yml | 2 +
.../bsps/arm/imxrt/optmemflashorigin.yml | 4 +-
spec/build/bsps/arm/imxrt/optmemflashsz.yml | 2 +
spec/build/bsps/arm/imxrt/optmemitcmsz.yml | 2 +
.../bsps/arm/imxrt/optmemocramorigin.yml | 2 +
spec/build/bsps/arm/imxrt/optmemocramsz.yml | 2 +
spec/build/bsps/arm/imxrt/optvariant.yml | 2 +
23 files changed, 6907 insertions(+), 4 deletions(-)
create mode 100644 bsps/arm/imxrt/boards/saltshaker/clock_config.c
create mode 100644 bsps/arm/imxrt/boards/saltshaker/clock_config.h
create mode 100644 bsps/arm/imxrt/boards/saltshaker/dcd.c
create mode 100644 bsps/arm/imxrt/boards/saltshaker/dcd.h
create mode 100644 bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c
create mode 100644 bsps/arm/imxrt/boards/saltshaker/pin_mux.c
create mode 100644 bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
create mode 100644 bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
create mode 100644 bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h
create mode 100644 bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi
create mode 100644 spec/build/bsps/arm/imxrt/bspimxrt1166-cm7-saltshaker.yml
diff --git a/bsps/arm/imxrt/boards/saltshaker/clock_config.c b/bsps/arm/imxrt/boards/saltshaker/clock_config.c
new file mode 100644
index 0000000000..85bc4ef29a
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/clock_config.c
@@ -0,0 +1,823 @@
+/*
+ * Copyright 2017-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1166xxxxx
+package_id: MIMXRT1166DVM6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+#include "fsl_dcdc.h"
+#include "fsl_pmu.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ARM_PLL_CLK.outFreq, value: 600 MHz, locked: true, accuracy: '0.001'}
+- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: AXI_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: BUS_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 120 MHz}
+- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET1_CLK_ROOT.outFreq, value: 50 MHz, locked: true, accuracy: '0.001'}
+- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
+- {id: ENET_25M_CLK_ROOT.outFreq, value: 25 MHz, locked: true, accuracy: '0.001'}
+- {id: ENET_REF_CLK.outFreq, value: 50 MHz, locked: true, accuracy: '0.001'}
+- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ENET_TX_CLK.outFreq, value: 25 MHz, locked: true, accuracy: '0.001'}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
+- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI1_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPSPI2_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPSPI3_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPSPI4_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPSPI5_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPSPI6_CLK_ROOT.outFreq, value: 50 MHz}
+- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M4_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M7_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MQS_MCLK.outFreq, value: 24 MHz}
+- {id: OSC_24M.outFreq, value: 24 MHz}
+- {id: OSC_32K.outFreq, value: 32.768 kHz}
+- {id: OSC_RC_16M.outFreq, value: 16 MHz}
+- {id: OSC_RC_400M.outFreq, value: 400 MHz}
+- {id: OSC_RC_48M.outFreq, value: 48 MHz}
+- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
+- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz, locked: true, accuracy: '0.001'}
+- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 2160/13 MHz}
+- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 396 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz, locked: true, accuracy: '0.001'}
+- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz, locked: true, accuracy: '0.001'}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 200 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
+settings:
+- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
+- {id: SemcConfigurationPatchConfig, value: disabled}
+- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
+- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
+- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '4'}
+- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '100'}
+- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
+- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
+- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
+- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
+- {id: ANADIG_PLL.SYS_PLL2_PFD3_DIV.scale, value: '24'}
+- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
+- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
+- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK}
+- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
+- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
+- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4'}
+- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4'}
+- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK}
+- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '4'}
+- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '8'}
+- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_OSC.OSC_24M}
+- {id: CCM.CLOCK_ROOT58.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
+- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
+- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
+- {id: IOMUXC_GPR.ENET_REF_CLK_SEL.sel, value: CCM.ENET1_CLK_ROOT}
+sources:
+- {id: IOMUXC_GPR.ENET_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
+- {id: IOMUXC_GPR.ENET_TX_CLK_EXT.outFreq, value: 25 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+
+#if __CORTEX_M == 7
+#define BYPASS_LDO_LPSR 1
+#endif
+
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .postDivider = kCLOCK_PllPostDiv4, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+ .loopDivider = 200, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+ };
+
+const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN =
+ {
+ .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */
+ .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
+ {
+ .mfd = 268435455, /* Denominator of spread spectrum */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
+ .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
+ .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ clock_root_config_t rootCfg = {0};
+
+ /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
+ DCDC_BootIntoDCM(DCDC);
+
+#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
+ PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
+ PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
+#endif
+
+ /* Config CLK_1M */
+ CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+ /* Init OSC RC 16M */
+ ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
+
+ /* Init OSC RC 400M */
+ CLOCK_OSC_EnableOscRc400M();
+ CLOCK_OSC_GateOscRc400M(true);
+
+ /* Init OSC RC 48M */
+ CLOCK_OSC_EnableOsc48M(true);
+ CLOCK_OSC_EnableOsc48MDiv2(true);
+
+ /* Config OSC 24M */
+ ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+ /* Wait for 24M OSC to be stable. */
+ while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+ (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
+ {
+ }
+
+ /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
+#if __CORTEX_M == 7
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+
+ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+#if __CORTEX_M == 4
+ rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+
+ rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+#endif
+
+ /* Init Arm Pll. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+
+ /* Init Sys Pll1. */
+ CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
+
+ /* Init Sys Pll2. */
+ CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+
+ /* Init System Pll2 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+
+ /* Init System Pll2 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+
+ /* Init System Pll2 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+
+ /* Init System Pll2 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
+
+ /* Init Sys Pll3. */
+ CLOCK_InitSysPll3();
+
+ /* Init System Pll3 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
+
+ /* Init System Pll3 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
+
+ /* Init System Pll3 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
+
+ /* Init System Pll3 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
+
+ /* Bypass Audio Pll. */
+ CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+
+ /* DeInit Audio Pll. */
+ CLOCK_DeinitAudioPll();
+
+ /* Init Video Pll. */
+ CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
+
+ /* Module clock root configurations. */
+ /* Configure M7 using ARM_PLL_CLK */
+#if __CORTEX_M == 7
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+ /* Configure M4 using SYS_PLL3_CLK */
+#if __CORTEX_M == 4
+ rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
+#endif
+
+ /* Configure BUS using SYS_PLL2_PFD3_CLK */
+ rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
+
+ /* Configure BUS_LPSR using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+
+ /* Configure SEMC using SYS_PLL3_PFD0_CLK */
+#ifndef SKIP_SEMC_INIT
+ rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
+#endif
+
+ /* Configure CSSYS using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
+
+ /* Configure CSTRACE using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
+
+ /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
+#if __CORTEX_M == 4
+ rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
+#endif
+
+ /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
+#if __CORTEX_M == 7
+ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+ /* Configure ADC1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
+
+ /* Configure ADC2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
+
+ /* Configure ACMP using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
+
+ /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+ /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+
+ /* Configure GPT1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
+
+ /* Configure GPT2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
+
+ /* Configure GPT3 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
+
+ /* Configure GPT4 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
+
+ /* Configure GPT5 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
+
+ /* Configure GPT6 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
+
+ /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
+ rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
+#endif
+
+ /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
+
+ /* Configure CAN1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
+
+ /* Configure CAN2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
+
+ /* Configure CAN3 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
+
+ /* Configure LPUART1 using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 22;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
+
+ /* Configure LPUART2 using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 22;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
+
+ /* Configure LPUART3 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
+
+ /* Configure LPUART4 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
+
+ /* Configure LPUART5 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
+
+ /* Configure LPUART6 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
+
+ /* Configure LPUART7 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
+
+ /* Configure LPUART8 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
+
+ /* Configure LPUART9 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
+
+ /* Configure LPUART10 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
+
+ /* Configure LPUART11 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
+
+ /* Configure LPUART12 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
+
+ /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
+
+ /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
+
+ /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
+
+ /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
+
+ /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
+
+ /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
+
+ /* Configure LPSPI1 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
+
+ /* Configure LPSPI2 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
+
+ /* Configure LPSPI3 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
+
+ /* Configure LPSPI4 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
+
+ /* Configure LPSPI5 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
+
+ /* Configure LPSPI6 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
+
+ /* Configure EMV1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
+
+ /* Configure EMV2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
+
+ /* Configure ENET1 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
+
+ /* Configure ENET2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
+
+ /* Configure ENET_25M using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 8;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
+
+ /* Configure ENET_TIMER1 using OSC_24M */
+ rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
+
+ /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
+
+ /* Configure USDHC1 using SYS_PLL1_DIV5_CLK */
+ rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+
+ /* Configure USDHC2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+
+ /* Configure ASRC using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
+
+ /* Configure MQS using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
+
+ /* Configure MIC using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
+
+ /* Configure SPDIF using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
+
+ /* Configure SAI1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
+
+ /* Configure SAI2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
+
+ /* Configure SAI3 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
+
+ /* Configure SAI4 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
+
+ /* Configure GC355 using PLL_VIDEO_CLK */
+ rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
+
+ /* Configure LCDIF using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
+
+ /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
+
+ /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
+
+ /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
+
+ /* Configure CSI2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
+
+ /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
+
+ /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
+
+ /* Configure CSI using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
+
+ /* Configure CKO1 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
+
+ /* Configure CKO2 using OSC_RC_48M_DIV2 */
+ rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
+
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Tx clock source. */
+ IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK;
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
+ /* Set ENET_1G Tx clock source. */
+ IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
+ /* Set ENET_1G Ref clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
+ /* Set GPT3 High frequency reference clock source. */
+ IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
+ /* Set GPT4 High frequency reference clock source. */
+ IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
+ /* Set GPT5 High frequency reference clock source. */
+ IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
+ /* Set GPT6 High frequency reference clock source. */
+ IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
+
+#if __CORTEX_M == 7
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
+#else
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
+#endif
+}
diff --git a/bsps/arm/imxrt/boards/saltshaker/clock_config.h b/bsps/arm/imxrt/boards/saltshaker/clock_config.h
new file mode 100644
index 0000000000..f918d969b3
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/clock_config.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BOARD_CLOCK_CONFIG_H
+#define BOARD_CLOCK_CONFIG_H
+
+#include <bspopts.h>
+#include <fsl_clock_config.h>
+#define FLEXSPI_IN_USE
+
+#endif /* BOARD_CLOCK_CONFIG_H */
diff --git a/bsps/arm/imxrt/boards/saltshaker/dcd.c b/bsps/arm/imxrt/boards/saltshaker/dcd.c
new file mode 100644
index 0000000000..94c51ff4bb
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/dcd.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2017-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#include "dcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.dcd_data"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.dcd_data"
+#endif
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx v3.0
+processor: MIMXRT1166xxxxx
+package_id: MIMXRT1166DVM6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
+const uint8_t dcd_data[] = {
+ /* HEADER */
+ /* Tag */
+ 0xD2,
+ /* Image Length */
+ 0x03, 0x98,
+ /* Version */
+ 0x41,
+
+ /* COMMANDS */
+
+ /* group: 'SDRAM Initialization' */
+ /* #1.1-93, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x02, 0xEC, 0x04,
+ /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4, comment: 'SEMC_CLKROOT = SYS_PLL2_PFD1 / 2' */
+ 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03,
+ /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4, comment: 'SEMC_ADDR00' */
+ 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+ /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4, comment: 'SEMC_ADDR01' */
+ 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+ /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4, comment: 'SEMC_ADDR02' */
+ 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4, comment: 'SEMC_ADDR03' */
+ 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+ /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4, comment: 'SEMC_ADDR04' */
+ 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+ /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4, comment: 'SEMC_ADDR05' */
+ 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+ /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4, comment: 'SEMC_ADDR06' */
+ 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4, comment: 'SEMC_ADDR07' */
+ 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+ /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4, comment: 'SEMC_ADDR08' */
+ 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+ /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4, comment: 'SEMC_ADDR09' */
+ 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+ /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4, comment: 'SEMC_ADDR10' */
+ 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4, comment: 'SEMC_ADDR11' */
+ 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4, comment: 'SEMC_ADDR12' */
+ 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+ /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4, comment: 'SEMC_BA0' */
+ 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+ /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4, comment: 'SEMC_BA1' */
+ 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+ /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4, comment: 'SEMC_CKE' */
+ 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4, comment: 'SEMC_CLK' */
+ 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+ /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4, comment: 'SEMC_CS0' */
+ 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
+ /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4, comment: 'SEMC_WE' */
+ 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+ /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4, comment: 'SEMC_CAS' */
+ 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+ /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4, comment: 'SEMC_RAS' */
+ 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+ /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4, comment: 'SEMC_DM00' */
+ 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+ /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4, comment: 'SEMC_DM01' */
+ 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+ /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4, comment: 'SEMC_DATA00' */
+ 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
+ /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4, comment: 'SEMC_DATA01' */
+ 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+ /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4, comment: 'SEMC_DATA02' */
+ 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+ /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4, comment: 'SEMC_DATA03' */
+ 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4, comment: 'SEMC_DATA04' */
+ 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+ /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4, comment: 'SEMC_DATA05' */
+ 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+ /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4, comment: 'SEMC_DATA06' */
+ 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+ /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4, comment: 'SEMC_DATA07' */
+ 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4, comment: 'SEMC_DATA08' */
+ 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+ /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4, comment: 'SEMC_DATA09' */
+ 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4, comment: 'SEMC_DATA10' */
+ 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+ /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4, comment: 'SEMC_DATA11' */
+ 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+ /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4, comment: 'SEMC_DATA12' */
+ 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4, comment: 'SEMC_DATA13' */
+ 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+ /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4, comment: 'SEMC_DATA14' */
+ 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+ /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4, comment: 'SEMC_DATA15' */
+ 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+ /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4, comment: 'SEMC_DQS' */
+ 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10,
+ /* #1.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4, comment: 'SEMC_ADDR00' */
+ 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08,
+ /* #1.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4, comment: 'SEMC_ADDR01' */
+ 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08,
+ /* #1.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4, comment: 'SEMC_ADDR02' */
+ 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08,
+ /* #1.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4, comment: 'SEMC_ADDR03' */
+ 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08,
+ /* #1.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4, comment: 'SEMC_ADDR04' */
+ 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08,
+ /* #1.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4, comment: 'SEMC_ADDR05' */
+ 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
+ /* #1.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4, comment: 'SEMC_ADDR06' */
+ 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08,
+ /* #1.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4, comment: 'SEMC_ADDR07' */
+ 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08,
+ /* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4, comment: 'SEMC_ADDR08' */
+ 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08,
+ /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4, comment: 'SEMC_ADDR09' */
+ 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08,
+ /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4, comment: 'SEMC_ADDR10' */
+ 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4, comment: 'SEMC_ADDR11' */
+ 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4, comment: 'SEMC_ADDR12' */
+ 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08,
+ /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4, comment: 'SEMC_BA0' */
+ 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08,
+ /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4, comment: 'SEMC_BA1' */
+ 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08,
+ /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4, comment: 'SEMC_CKE' */
+ 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4, comment: 'SEMC_CLK' */
+ 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08,
+ /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x04, size: 4, comment: 'SEMC_CS0' */
+ 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x04,
+ /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4, comment: 'SEMC_WE' */
+ 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08,
+ /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4, comment: 'SEMC_CAS' */
+ 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08,
+ /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4, comment: 'SEMC_RAS' */
+ 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08,
+ /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4, comment: 'SEMC_DM00' */
+ 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08,
+ /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4, comment: 'SEMC_DM01' */
+ 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08,
+ /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4, comment: 'SEMC_DATA00' */
+ 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08,
+ /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4, comment: 'SEMC_DATA01' */
+ 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08,
+ /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4, comment: 'SEMC_DATA02' */
+ 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08,
+ /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4, comment: 'SEMC_DATA03' */
+ 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08,
+ /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4, comment: 'SEMC_DATA04' */
+ 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08,
+ /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4, comment: 'SEMC_DATA05' */
+ 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08,
+ /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4, comment: 'SEMC_DATA06' */
+ 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08,
+ /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4, comment: 'SEMC_DATA07' */
+ 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08,
+ /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4, comment: 'SEMC_DATA08' */
+ 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08,
+ /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4, comment: 'SEMC_DATA09' */
+ 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4, comment: 'SEMC_DATA10' */
+ 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08,
+ /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4, comment: 'SEMC_DATA11' */
+ 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08,
+ /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4, comment: 'SEMC_DATA12' */
+ 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08,
+ /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4, comment: 'SEMC_DATA13' */
+ 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4, comment: 'SEMC_DATA14' */
+ 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08,
+ /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4, comment: 'SEMC_DATA15' */
+ 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08,
+ /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4, comment: 'SEMC_DQS' */
+ 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08,
+ /* #1.82, command: write_value, address: SEMC_MCR, value: 0x1FFF0004, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
+ 0x40, 0x0D, 0x40, 0x00, 0x1F, 0xFF, 0x00, 0x04,
+ /* #1.83, command: write_value, address: SEMC_BMCR0, value: 0x104085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
+ 0x40, 0x0D, 0x40, 0x08, 0x00, 0x10, 0x40, 0x85,
+ /* #1.84, command: write_value, address: SEMC_BMCR1, value: 0x40246085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
+ 0x40, 0x0D, 0x40, 0x0C, 0x40, 0x24, 0x60, 0x85,
+ /* #1.85, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4, comment: 'CS0: Start add Address 0x80000000; Memsize 64MByte' */
+ 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D,
+ /* #1.86, command: write_value, address: SEMC_SDRAMCR0, value: 0xF35, size: 4, comment: 'PortSize 16; Burst Len 8; 9 Bit Column Addresses; CAS Latency 3' */
+ 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x35,
+ /* #1.87, command: write_value, address: SEMC_SDRAMCR1, value: 0x00664B22, size: 4, comment: 'PRE2ACT: tRP = 18ns; ACT2RW: tRCD = 18ns; RFRC: tRFC=72ns; WRC: tWR=15ns; CKEOFF: tRAS_min = 42ns; ACT2PRE: tRAS_min = 42ns' */
+ 0x40, 0x0D, 0x40, 0x44, 0x00, 0x66, 0x4B, 0x22,
+ /* #1.88, command: write_value, address: SEMC_SDRAMCR2, value: 0x00090B13, size: 4, comment: 'SRCC: tXSR=120ns; REF2REF: tRFC=72ns; ACT2ACT: tRC=60ns' */
+ 0x40, 0x0D, 0x40, 0x48, 0x00, 0x09, 0x0B, 0x13,
+ /* #1.89, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A00, size: 4, comment: 'Default values from NXP examples for SEMC' */
+ 0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x00,
+ /* #1.90, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+ 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00,
+ /* #1.91, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+ 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02,
+ /* #1.92, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+ 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00,
+ /* #1.93, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4, comment: 'IP Command: Precharge All' */
+ 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+ /* #2, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #3, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #4, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #5, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #6, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #7.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
+ 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
+ /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Auto Refresh' */
+ 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #8, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #9, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #10, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #11, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #12, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #13.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
+ 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
+ /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Precharge All' */
+ 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+ /* #14, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #15, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #16, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #17, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #18, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #19.1-3, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x1C, 0x04,
+ /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
+ 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
+ /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4, comment: 'Mode: BurstLen8; CAS Latency 3' */
+ 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33,
+ /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4, comment: 'IP Command: Mode Set' */
+ 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+ /* #20, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #21, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #22, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #23, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #24, command: nop */
+ 0xC0, 0x00, 0x04, 0x00,
+ /* #25.1-2, command header bytes for merged 'Write - value' command */
+ 0xCC, 0x00, 0x14, 0x04,
+ /* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
+ 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
+ /* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A01, size: 4, comment: 'Enable autorefresh. Otherwise same as above.' */
+ 0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x01
+ };
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
+#else
+const uint8_t dcd_data[] = {0x00};
+#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/bsps/arm/imxrt/boards/saltshaker/dcd.h b/bsps/arm/imxrt/boards/saltshaker/dcd.h
new file mode 100644
index 0000000000..ba918a4aed
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/dcd.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BOARD_DCD_H
+#define BOARD_DCD_H
+
+#include <bsp/flash-headers.h>
+#include <stdint.h>
+#define XIP_BOOT_HEADER_ENABLE 1
+#define XIP_BOOT_HEADER_DCD_ENABLE 1
+#define dcd_data imxrt_dcd_data
+
+#endif /* BOARD_DCD_H */
diff --git a/bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c b/bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c
new file mode 100644
index 0000000000..14df880685
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/flash-headers.h>
+#include <bspopts.h>
+
+const flexspi_nor_config_t imxrt_flexspi_config = {
+ .memConfig = {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+ .csHoldTime = 1u, /* In serial Clk cycles. tSLCH = 3ns for the W25Q64JV. */
+ .csSetupTime = 1u, /* In serial Clk cycles. tCHSH = 3ns for the W25Q64JV. */
+ .columnAddressWidth = 0u, /* W25Q64JV needs one linear address. */
+ .controllerMiscOption = 0u,
+ .deviceType = kFlexSpiDeviceType_SerialNOR,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_100MHz, /* FIXME: 133MHz should be possible */
+ .sflashA1Size = IMXRT_MEMORY_FLASH_SIZE,
+ .dataValidTime = {0u, 0u}, /* Only relevant for Clock < 100MHz */
+ .busyOffset = 0,
+ .busyBitPolarity = 0,
+ .lookupTable = {
+ /* Read LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 0] = FLEXSPI_LUT_SEQ(
+ CMD_SDR, FLEXSPI_1PAD, 0xEB,
+ RADDR_SDR, FLEXSPI_4PAD, 24),
+ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
+ DUMMY_SDR, FLEXSPI_4PAD, 6,
+ READ_SDR, FLEXSPI_4PAD, 4),
+ /* Read Status LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS + 0] = FLEXSPI_LUT_SEQ(
+ CMD_SDR, FLEXSPI_1PAD, 0x5,
+ READ_SDR, FLEXSPI_1PAD, 4),
+ /* Write Enable LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE + 0] = 0,
+ /* Erase Sector LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 0] = 0,
+ /* Page Program LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 0] = 0,
+ /* Erase Chip LUTs */
+ [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE + 0] = 0,
+ },
+ },
+ .pageSize = 256,
+ .sectorSize = 4096,
+ .blockSize = 32 * 1024,
+ .isUniformBlockSize = 1,
+};
diff --git a/bsps/arm/imxrt/boards/saltshaker/pin_mux.c b/bsps/arm/imxrt/boards/saltshaker/pin_mux.c
new file mode 100644
index 0000000000..20206bdc14
--- /dev/null
+++ b/bsps/arm/imxrt/boards/saltshaker/pin_mux.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include <bsp.h>
+#include <bsp/start.h>
+
+BSP_START_TEXT_SECTION
+void BOARD_InitDEBUG_UARTPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_LPUART8_TXD, 0U);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_03_LPUART8_RXD, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_LPUART8_TXD, 0x10B0u);
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_03_LPUART8_RXD, 0x10B0u);
+}
diff --git a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
new file mode 100644
index 0000000000..f533172bbc
--- /dev/null
+++ b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
@@ -0,0 +1,2399 @@
+/*
+ * Declarations for C structure representing binary file imxrt_dtb
+ *
+ * WARNING: Automatically generated -- do not edit!
+ */
+
+#include <sys/types.h>
+
+const unsigned char imxrt_dtb[] __attribute__(( __aligned__(8) )) = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x6f, 0xdf, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x69, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xff,
+ 0x00, 0x00, 0x69, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x01, 0x63, 0x68, 0x6f, 0x73, 0x65, 0x6e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x1b,
+ 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x61, 0x69, 0x70, 0x73, 0x2d, 0x62, 0x75,
+ 0x73, 0x40, 0x34, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x2f, 0x75,
+ 0x61, 0x72, 0x74, 0x40, 0x34, 0x30, 0x30, 0x39, 0x38, 0x30, 0x30, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x61, 0x6c, 0x69, 0x61, 0x73, 0x65, 0x73, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x27, 0x2f, 0x73, 0x6f, 0x63,
+ 0x2f, 0x61, 0x69, 0x70, 0x73, 0x2d, 0x62, 0x75, 0x73, 0x40, 0x34, 0x30,
+ 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x2f, 0x61, 0x63, 0x6d, 0x70, 0x40,
+ 0x34, 0x30, 0x31, 0x61, 0x34, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x2d,
+ 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x61, 0x69, 0x70, 0x73, 0x2d, 0x62, 0x75,
+ 0x73, 0x40, 0x34, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x2f, 0x61,
+ 0x63, 0x6d, 0x70, 0x40, 0x34, 0x30, 0x31, 0x61, 0x38, 0x30, 0x30, 0x30,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x25,
+ 0x00, 0x00, 0x00, 0x33, 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x61, 0x69, 0x70,
+ 0x73, 0x2d, 0x62, 0x75, 0x73, 0x40, 0x34, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x2f, 0x61, 0x63, 0x6d, 0x70, 0x40, 0x34, 0x30, 0x31, 0x61,
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+ 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65, 0x67, 0x00, 0x70,
+ 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x73, 0x74, 0x61, 0x74, 0x75,
+ 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
+ 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x72, 0x61, 0x6e, 0x67, 0x65,
+ 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x73,
+ 0x00, 0x23, 0x64, 0x6d, 0x61, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00,
+ 0x72, 0x74, 0x65, 0x6d, 0x73, 0x2c, 0x70, 0x61, 0x74, 0x68, 0x00, 0x64,
+ 0x6d, 0x61, 0x2d, 0x6e, 0x61, 0x6d, 0x65, 0x73, 0x00, 0x64, 0x6d, 0x61,
+ 0x73, 0x00, 0x70, 0x69, 0x6e, 0x63, 0x74, 0x72, 0x6c, 0x2d, 0x30, 0x00,
+ 0x66, 0x73, 0x6c, 0x2c, 0x70, 0x69, 0x6e, 0x73, 0x00, 0x67, 0x70, 0x69,
+ 0x6f, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72,
+ 0x00, 0x23, 0x67, 0x70, 0x69, 0x6f, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73,
+ 0x00, 0x62, 0x75, 0x73, 0x2d, 0x77, 0x69, 0x64, 0x74, 0x68, 0x00, 0x63,
+ 0x64, 0x2d, 0x67, 0x70, 0x69, 0x6f, 0x73, 0x00, 0x63, 0x64, 0x2d, 0x69,
+ 0x6e, 0x76, 0x65, 0x72, 0x74, 0x65, 0x64, 0x00, 0x76, 0x6d, 0x6d, 0x63,
+ 0x2d, 0x73, 0x75, 0x70, 0x70, 0x6c, 0x79, 0x00, 0x69, 0x6e, 0x74, 0x65,
+ 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x6e, 0x61, 0x6d, 0x65, 0x73, 0x00,
+ 0x66, 0x73, 0x6c, 0x2c, 0x6e, 0x75, 0x6d, 0x2d, 0x74, 0x78, 0x2d, 0x71,
+ 0x75, 0x65, 0x75, 0x65, 0x73, 0x00, 0x66, 0x73, 0x6c, 0x2c, 0x6e, 0x75,
+ 0x6d, 0x2d, 0x72, 0x78, 0x2d, 0x71, 0x75, 0x65, 0x75, 0x65, 0x73, 0x00,
+ 0x70, 0x68, 0x79, 0x2d, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x70, 0x68, 0x79,
+ 0x2d, 0x72, 0x65, 0x73, 0x65, 0x74, 0x2d, 0x67, 0x70, 0x69, 0x6f, 0x73,
+ 0x00, 0x72, 0x65, 0x67, 0x75, 0x6c, 0x61, 0x74, 0x6f, 0x72, 0x2d, 0x6e,
+ 0x61, 0x6d, 0x65, 0x00, 0x72, 0x65, 0x67, 0x75, 0x6c, 0x61, 0x74, 0x6f,
+ 0x72, 0x2d, 0x6d, 0x69, 0x6e, 0x2d, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x76,
+ 0x6f, 0x6c, 0x74, 0x00, 0x72, 0x65, 0x67, 0x75, 0x6c, 0x61, 0x74, 0x6f,
+ 0x72, 0x2d, 0x6d, 0x61, 0x78, 0x2d, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x76,
+ 0x6f, 0x6c, 0x74, 0x00, 0x67, 0x70, 0x69, 0x6f, 0x00, 0x72, 0x65, 0x67,
+ 0x75, 0x6c, 0x61, 0x74, 0x6f, 0x72, 0x2d, 0x62, 0x6f, 0x6f, 0x74, 0x2d,
+ 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+const size_t imxrt_dtb_size = sizeof(imxrt_dtb);
diff --git a/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
new file mode 100644
index 0000000000..81740ce499
--- /dev/null
+++ b/bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020-2023 embedded brains GmbH & Co. KG
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * FIXME: Compilation should be automated.
+ *
+ * Compile this file with the following commands:
+ * export BSP_DIR="${RTEMS_SRC_DIR}/bsps/arm/imxrt/"
+ * arm-rtems6-cpp -P -x assembler-with-cpp -I "${BSP_DIR}/include/" -include "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dts" /dev/null | \
+ * dtc -O dtb -o "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dtb" -b 0 -p 64
+ * rtems-bin2c -A 8 -C -N imxrt_dtb "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dtb" "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.c"
+ */
+
+/dts-v1/;
+
+#include <imxrt/imxrt1166-pinfunc.h>
+#include <imxrt/imxrt1166.dtsi>
+
+/ {
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_led>;
+ status = "okay";
+
+ led-0 {
+ gpios = <&gpio9 15 0>;
+ };
+ led-1 {
+ gpios = <&gpio9 16 0>;
+ };
+ led-2 {
+ gpios = <&gpio9 18 0>;
+ };
+ };
+
+ usdhc1_vcard: usdhc1_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "usdhc1-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio10 2 0>;
+ regulator-boot-on;
+ };
+};
+
+&lpuart8 {
+ pinctrl-0 = <&pinctrl_lpuart8>;
+ status = "okay";
+};
+
+&chosen {
+ stdout-path = &lpuart8;
+};
+
+&fec2 {
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-reset-gpios = <&gpio9 14 1>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&lpi2c1 {
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+};
+
+&lpi2c5 {
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+};
+
+&lpi2c6 {
+ pinctrl-0 = <&pinctrl_lpi2c6>;
+};
+
+&lpspi1 {
+ pinctrl-0 = <&pinctrl_lpspi1>;
+};
+
+&lpspi3 {
+ pinctrl-0 = <&pinctrl_lpspi3>;
+};
+
+&lpspi4 {
+ pinctrl-0 = <&pinctrl_lpspi4>;
+};
+
+&lpuart7 {
+ pinctrl-0 = <&pinctrl_lpuart7>;
+};
+
+&lpuart12 {
+ pinctrl-0 = <&pinctrl_lpuart12>;
+};
+
+&usdhc1 {
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio9 31 1>;
+ cd-inverted;
+ vmmc-supply = <&usdhc1_vcard>;
+};
+
+&video_mux {
+ pinctrl-0 = <&pinctrl_video_mux>;
+};
+
+&iomuxc {
+ pinctrl_lpuart8: lpuart8grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_02_LPUART8_TXD 0x8
+ IMXRT_PAD_GPIO_AD_03_LPUART8_RXD 0x13000
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_33_ENET_MDIO 0x1c
+ IMXRT_PAD_GPIO_EMC_B2_19_ENET_MDC 0x00
+ IMXRT_PAD_GPIO_AD_26_ENET_RX_DATA00 0x02
+ IMXRT_PAD_GPIO_AD_27_ENET_RX_DATA01 0x02
+ IMXRT_PAD_GPIO_AD_24_ENET_RX_EN 0x02
+ IMXRT_PAD_GPIO_AD_30_ENET_TX_DATA00 0x02
+ IMXRT_PAD_GPIO_AD_31_ENET_TX_DATA01 0x02
+ IMXRT_PAD_GPIO_AD_28_ENET_TX_EN 0x02
+ IMXRT_PAD_GPIO_AD_29_ENET_REF_CLK 0x40000002
+ IMXRT_PAD_GPIO_AD_25_ENET_RX_ER 0x02
+ /* ENET_RST */
+ IMXRT_PAD_GPIO_AD_15_GPIO9_IO14 0x1c
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_08_LPI2C1_SCL 0x40000011
+ IMXRT_PAD_GPIO_AD_09_LPI2C1_SDA 0x40000011
+ >;
+ };
+
+ pinctrl_lpspi3: lpspi3grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_EMC_B2_04_LPSPI3_SCK 0x04
+ IMXRT_PAD_GPIO_EMC_B2_06_LPSPI3_SOUT 0x04
+ IMXRT_PAD_GPIO_EMC_B2_07_LPSPI3_SIN 0x04
+ IMXRT_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 0x04
+ IMXRT_PAD_GPIO_EMC_B2_08_LPSPI3_PCS1 0x04
+ IMXRT_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 0x04
+ IMXRT_PAD_GPIO_EMC_B2_10_LPSPI3_PCS3 0x04
+ >;
+ };
+
+ pinctrl_lpspi3: lpspi3grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_EMC_B2_04_LPSPI3_SCK 0x06
+ IMXRT_PAD_GPIO_EMC_B2_06_LPSPI3_SOUT 0x06
+ IMXRT_PAD_GPIO_EMC_B2_07_LPSPI3_SIN 0x06
+ IMXRT_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 0x06
+ IMXRT_PAD_GPIO_EMC_B2_08_LPSPI3_PCS1 0x06
+ IMXRT_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 0x06
+ IMXRT_PAD_GPIO_EMC_B2_10_LPSPI3_PCS3 0x06
+ >;
+ };
+
+ pinctrl_lpspi1: lpspi1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_20_LPSPI1_PCS3 0x06
+ IMXRT_PAD_GPIO_EMC_B2_00_LPSPI1_SCK 0x06
+ IMXRT_PAD_GPIO_EMC_B2_01_LPSPI1_PCS0 0x06
+ IMXRT_PAD_GPIO_EMC_B2_02_LPSPI1_SOUT 0x06
+ IMXRT_PAD_GPIO_EMC_B2_03_LPSPI1_SIN 0x06
+ >;
+ };
+
+ pinctrl_lpspi4: lpspi4grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_SD_B2_00_LPSPI4_SCK 0x06
+ IMXRT_PAD_GPIO_SD_B2_01_LPSPI4_PCS0 0x06
+ IMXRT_PAD_GPIO_SD_B2_02_LPSPI4_SOUT 0x06
+ IMXRT_PAD_GPIO_SD_B2_03_LPSPI4_SIN 0x06
+ IMXRT_PAD_GPIO_SD_B2_04_LPSPI4_PCS1 0x06
+ IMXRT_PAD_GPIO_SD_B2_05_LPSPI4_PCS2 0x06
+ >;
+ };
+
+ pinctrl_lpuart7: lpuart7grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_00_LPUART7_TXD 0x0c
+ IMXRT_PAD_GPIO_AD_01_LPUART7_RXD 0x0c
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_SD_B1_00_USDHC1_CMD 0x04
+ IMXRT_PAD_GPIO_SD_B1_01_USDHC1_CLK 0x08
+ IMXRT_PAD_GPIO_SD_B1_02_USDHC1_DATA0 0x04
+ IMXRT_PAD_GPIO_SD_B1_03_USDHC1_DATA1 0x04
+ IMXRT_PAD_GPIO_SD_B1_04_USDHC1_DATA2 0x04
+ IMXRT_PAD_GPIO_SD_B1_05_USDHC1_DATA3 0x04
+ IMXRT_PAD_GPIO_AD_32_GPIO9_IO31 0x10 /* CD */
+ IMXRT_PAD_GPIO_AD_34_GPIO10_IO01 0x00 /* VSEL */
+ IMXRT_PAD_GPIO_AD_35_GPIO10_IO02 0x00 /* PWR_B */
+ >;
+ };
+
+ pinctrl_video_mux: videomuxgrp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x0a
+ IMXRT_PAD_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x0a
+ IMXRT_PAD_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x0a
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_AD_16_GPIO9_IO15 0x00
+ IMXRT_PAD_GPIO_AD_17_GPIO9_IO16 0x00
+ IMXRT_PAD_GPIO_AD_19_GPIO9_IO18 0x00
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_LPSR_09_LPI2C5_SCL 0x40000011
+ IMXRT_PAD_GPIO_LPSR_08_LPI2C5_SDA 0x40000011
+ >;
+ };
+
+ pinctrl_lpi2c6: lpi2c6grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_LPSR_07_LPI2C6_SCL 0x40000011
+ IMXRT_PAD_GPIO_LPSR_06_LPI2C6_SDA 0x40000011
+ >;
+ };
+
+ pinctrl_lpuart12: lpuart12grp {
+ fsl,pins = <
+ IMXRT_PAD_GPIO_LPSR_00_LPUART12_TXD 0x0d
+ IMXRT_PAD_GPIO_LPSR_01_LPUART12_RXD 0x0d
+ IMXRT_PAD_GPIO_LPSR_04_LPUART12_RTS_B 0x0d
+ IMXRT_PAD_GPIO_LPSR_05_LPUART12_CTS_B 0x0d
+ >;
+ };
+};
+
+&iomuxc_snvs {
+};
diff --git a/bsps/arm/imxrt/include/bsp/irq.h b/bsps/arm/imxrt/include/bsp/irq.h
index df51b2b2de..b232eede56 100644
--- a/bsps/arm/imxrt/include/bsp/irq.h
+++ b/bsps/arm/imxrt/include/bsp/irq.h
@@ -34,6 +34,7 @@
#ifndef LIBBSP_ARM_IMXRT_IRQ_H
#define LIBBSP_ARM_IMXRT_IRQ_H
+#include <bspopts.h>
#ifndef ASM
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
@@ -43,7 +44,11 @@
extern "C" {
#endif /* __cplusplus */
+#if IMXRT_IS_MIMXRT10xx
#define BSP_INTERRUPT_VECTOR_COUNT 160
+#elif IMXRT_IS_MIMXRT11xx
+#define BSP_INTERRUPT_VECTOR_COUNT 217
+#endif
#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
#ifdef __cplusplus
diff --git a/bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h b/bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h
new file mode 100644
index 0000000000..7379ff87c5
--- /dev/null
+++ b/bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h
@@ -0,0 +1,1607 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMimxrt
+ *
+ * @brief Pin function definitions for i.MXRT1166.
+ *
+ * Note: This file is basically a reformatted version of the fsl_iomuxc.h. RTEMS
+ * uses a driver based on the FreeBSD iomux driver for the i.mx6. That driver
+ * expects a different order of the values.
+ */
+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_IMXRT_IMXRT1166_PINFUNC_H
+#define LIBBSP_ARM_IMXRT_IMXRT1166_PINFUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* LPSR pins. Base address is 0x40c08000 */
+
+#define IMXRT_PAD_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0
+#define IMXRT_PAD_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0 0x5 0
+
+#define IMXRT_PAD_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 1
+#define IMXRT_PAD_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0
+
+#define IMXRT_PAD_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 1
+#define IMXRT_PAD_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0 0x7 0
+#define IMXRT_PAD_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0 0x8 0
+#define IMXRT_PAD_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 1
+#define IMXRT_PAD_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 1
+#define IMXRT_PAD_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0 0x7 0
+#define IMXRT_PAD_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0 0x8 0
+#define IMXRT_PAD_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 1
+#define IMXRT_PAD_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 1
+#define IMXRT_PAD_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0 0x7 0
+#define IMXRT_PAD_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0 0x8 0
+
+#define IMXRT_PAD_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 1
+#define IMXRT_PAD_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 2
+#define IMXRT_PAD_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 1
+#define IMXRT_PAD_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 1
+#define IMXRT_PAD_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0 0x7 0
+
+#define IMXRT_PAD_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 1
+#define IMXRT_PAD_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 1
+#define IMXRT_PAD_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 2
+
+#define IMXRT_PAD_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 1
+#define IMXRT_PAD_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0 0x7 0
+#define IMXRT_PAD_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 2
+#define IMXRT_PAD_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0 0x1 0
+#define IMXRT_PAD_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0
+#define IMXRT_PAD_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0 0x4 0
+#define IMXRT_PAD_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0 0x6 0
+#define IMXRT_PAD_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 1
+#define IMXRT_PAD_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 1
+
+#define IMXRT_PAD_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 1
+#define IMXRT_PAD_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 1
+#define IMXRT_PAD_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 1
+
+#define IMXRT_PAD_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 1
+#define IMXRT_PAD_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 1
+#define IMXRT_PAD_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 1
+#define IMXRT_PAD_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0 0xA 0
+
+#define IMXRT_PAD_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0 0xA 0
+#define IMXRT_PAD_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0 0x0 0
+#define IMXRT_PAD_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 1
+#define IMXRT_PAD_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0 0x2 0
+#define IMXRT_PAD_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0 0x5 0
+#define IMXRT_PAD_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 1
+#define IMXRT_PAD_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 1
+
+/* SNVS pins. Base address is 0x40c94000 */
+
+#define IMXRT_PAD_WAKEUP_DIG_GPIO13_IO00 0x000 0x040 0 0x5 0
+/* NOTE: Can't handle that pin. It's distributed between SNVS and LPSR */
+// #define IMXRT_PAD_WAKEUP_DIG_NMI_GLUE_NMI 0x000 0x040 0x40C080C4 0x7 1
+
+#define IMXRT_PAD_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x004 0x044 0 0x0 0
+#define IMXRT_PAD_PMIC_ON_REQ_DIG_GPIO13_IO01 0x004 0x044 0 0x5 0
+
+#define IMXRT_PAD_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x008 0x048 0 0x0 0
+#define IMXRT_PAD_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x008 0x048 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x00C 0x04C 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_00_DIG_GPIO13_IO03 0x00C 0x04C 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x010 0x050 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_01_DIG_GPIO13_IO04 0x010 0x050 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x014 0x054 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_02_DIG_GPIO13_IO05 0x014 0x054 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x018 0x058 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_03_DIG_GPIO13_IO06 0x018 0x058 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x01C 0x05C 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_04_DIG_GPIO13_IO07 0x01C 0x05C 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x020 0x060 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_05_DIG_GPIO13_IO08 0x020 0x060 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x024 0x064 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_06_DIG_GPIO13_IO09 0x024 0x064 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x028 0x068 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_07_DIG_GPIO13_IO10 0x028 0x068 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x02C 0x06C 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_08_DIG_GPIO13_IO11 0x02C 0x06C 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x030 0x070 0 0x0 0
+#define IMXRT_PAD_GPIO_SNVS_09_DIG_GPIO13_IO12 0x030 0x070 0 0x5 0
+
+#define IMXRT_PAD_TEST_MODE_DIG 0 0x034 0 0 0
+
+#define IMXRT_PAD_POR_B_DIG 0 0x038 0 0 0
+
+#define IMXRT_PAD_ONOFF_DIG 0 0x03C 0 0 0
+
+/* Normal pins. Base address is 0x400e8000 */
+
+#define IMXRT_PAD_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0 0x8 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0 0x5 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0 0x5 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0 0x5 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0 0x5 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0 0x5 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0 0x9 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 1
+#define IMXRT_PAD_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0 0x9 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 1
+
+#define IMXRT_PAD_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0 0x7 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 1
+#define IMXRT_PAD_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0
+#define IMXRT_PAD_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0 0x9 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 1
+#define IMXRT_PAD_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 1
+#define IMXRT_PAD_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0 0xA 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0 0x2 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0
+
+#define IMXRT_PAD_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0 0xA 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0 0x0 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 1
+#define IMXRT_PAD_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0 0x4 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0 0x5 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0
+#define IMXRT_PAD_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 1
+#define IMXRT_PAD_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 1
+#define IMXRT_PAD_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0
+#define IMXRT_PAD_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0
+#define IMXRT_PAD_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 1
+#define IMXRT_PAD_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0
+#define IMXRT_PAD_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 1
+#define IMXRT_PAD_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0
+#define IMXRT_PAD_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 1
+#define IMXRT_PAD_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0
+#define IMXRT_PAD_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 1
+#define IMXRT_PAD_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 1
+#define IMXRT_PAD_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_04_WDOG1_B 0x11C 0x360 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 1
+#define IMXRT_PAD_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 1
+#define IMXRT_PAD_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_05_GPT2_CLK 0x120 0x364 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 1
+#define IMXRT_PAD_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_05_WDOG2_B 0x120 0x364 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 1
+#define IMXRT_PAD_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0
+#define IMXRT_PAD_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0
+#define IMXRT_PAD_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 1
+#define IMXRT_PAD_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0
+#define IMXRT_PAD_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0
+#define IMXRT_PAD_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 1
+#define IMXRT_PAD_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0
+#define IMXRT_PAD_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0
+#define IMXRT_PAD_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0
+#define IMXRT_PAD_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0
+#define IMXRT_PAD_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0
+#define IMXRT_PAD_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0
+#define IMXRT_PAD_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0
+#define IMXRT_PAD_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 1
+#define IMXRT_PAD_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0
+#define IMXRT_PAD_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0
+#define IMXRT_PAD_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0
+#define IMXRT_PAD_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0 0xB 0
+#define IMXRT_PAD_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 1
+#define IMXRT_PAD_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0
+#define IMXRT_PAD_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0
+#define IMXRT_PAD_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0 0x8 0
+
+#define IMXRT_PAD_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0
+#define IMXRT_PAD_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0
+#define IMXRT_PAD_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0
+#define IMXRT_PAD_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_17_GPT1_CLK 0x150 0x394 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 1
+#define IMXRT_PAD_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 2
+#define IMXRT_PAD_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0 0xB 0
+#define IMXRT_PAD_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0
+#define IMXRT_PAD_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_18_ENET_CRS 0x154 0x398 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 1
+
+#define IMXRT_PAD_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0
+#define IMXRT_PAD_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0
+#define IMXRT_PAD_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_19_ENET_COL 0x158 0x39C 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 1
+#define IMXRT_PAD_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0
+#define IMXRT_PAD_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0
+#define IMXRT_PAD_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0
+#define IMXRT_PAD_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0
+#define IMXRT_PAD_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0
+#define IMXRT_PAD_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0
+#define IMXRT_PAD_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0
+#define IMXRT_PAD_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0
+#define IMXRT_PAD_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0
+#define IMXRT_PAD_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0
+#define IMXRT_PAD_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0
+#define IMXRT_PAD_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0
+#define IMXRT_PAD_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0
+#define IMXRT_PAD_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0
+#define IMXRT_PAD_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0
+#define IMXRT_PAD_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 1
+#define IMXRT_PAD_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0
+#define IMXRT_PAD_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0
+#define IMXRT_PAD_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0
+#define IMXRT_PAD_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0
+#define IMXRT_PAD_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 1
+#define IMXRT_PAD_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0
+#define IMXRT_PAD_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0
+#define IMXRT_PAD_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 1
+#define IMXRT_PAD_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 1
+
+#define IMXRT_PAD_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0
+#define IMXRT_PAD_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0
+#define IMXRT_PAD_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 1
+#define IMXRT_PAD_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 1
+#define IMXRT_PAD_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 1
+
+#define IMXRT_PAD_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0 0xB 0
+#define IMXRT_PAD_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 1
+#define IMXRT_PAD_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 1
+#define IMXRT_PAD_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 1
+#define IMXRT_PAD_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0
+#define IMXRT_PAD_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0
+#define IMXRT_PAD_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 1
+#define IMXRT_PAD_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0 0xB 0
+
+#define IMXRT_PAD_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 1
+#define IMXRT_PAD_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 1
+#define IMXRT_PAD_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 1
+#define IMXRT_PAD_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 1
+#define IMXRT_PAD_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 1
+#define IMXRT_PAD_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 1
+#define IMXRT_PAD_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0
+#define IMXRT_PAD_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 1
+#define IMXRT_PAD_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0 0x9 0
+
+#define IMXRT_PAD_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 1
+#define IMXRT_PAD_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 1
+#define IMXRT_PAD_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 1
+#define IMXRT_PAD_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0
+#define IMXRT_PAD_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 1
+#define IMXRT_PAD_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 3
+#define IMXRT_PAD_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0 0x1 0
+#define IMXRT_PAD_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0 0x9 0
+#define IMXRT_PAD_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0 0xA 0
+
+#define IMXRT_PAD_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0 0xA 0
+#define IMXRT_PAD_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0 0x0 0
+#define IMXRT_PAD_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 1
+#define IMXRT_PAD_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0 0x2 0
+#define IMXRT_PAD_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0 0x3 0
+#define IMXRT_PAD_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0 0x4 0
+#define IMXRT_PAD_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0 0x5 0
+#define IMXRT_PAD_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0 0x6 0
+#define IMXRT_PAD_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0 0x8 0
+#define IMXRT_PAD_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0 0x9 0
+
+#define IMXRT_PAD_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0 0x6 0
+#define IMXRT_PAD_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 1
+#define IMXRT_PAD_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 1
+#define IMXRT_PAD_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 1
+#define IMXRT_PAD_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 1
+#define IMXRT_PAD_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 1
+#define IMXRT_PAD_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0 0x9 0
+
+#define IMXRT_PAD_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 1
+#define IMXRT_PAD_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 1
+#define IMXRT_PAD_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0 0x9 0
+#define IMXRT_PAD_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 1
+#define IMXRT_PAD_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0 0x8 0
+#define IMXRT_PAD_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0 0x9 0
+#define IMXRT_PAD_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 1
+#define IMXRT_PAD_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 1
+#define IMXRT_PAD_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0 0x8 0
+#define IMXRT_PAD_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0 0x9 0
+
+#define IMXRT_PAD_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 2
+#define IMXRT_PAD_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0 0x1 0
+#define IMXRT_PAD_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0 0x2 0
+#define IMXRT_PAD_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0 0x5 0
+
+#define IMXRT_PAD_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0 0x2 0
+#define IMXRT_PAD_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 1
+#define IMXRT_PAD_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0 0x8 0
+#define IMXRT_PAD_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 1
+#define IMXRT_PAD_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0 0xA 0
+
+#define IMXRT_PAD_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0 0x2 0
+#define IMXRT_PAD_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 1
+
+#define IMXRT_PAD_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0 0x2 0
+#define IMXRT_PAD_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 1
+
+#define IMXRT_PAD_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0 0xA 0
+#define IMXRT_PAD_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0 0x2 0
+#define IMXRT_PAD_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0 0x3 0
+#define IMXRT_PAD_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 1
+
+#define IMXRT_PAD_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0 0x0 0
+#define IMXRT_PAD_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 1
+#define IMXRT_PAD_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 1
+#define IMXRT_PAD_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 1
+#define IMXRT_PAD_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0 0x4 0
+#define IMXRT_PAD_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0 0x5 0
+#define IMXRT_PAD_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 1
+#define IMXRT_PAD_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0
+#define IMXRT_PAD_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 1
+#define IMXRT_PAD_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 1
+
+#define IMXRT_PAD_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 1
+#define IMXRT_PAD_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 1
+
+#define IMXRT_PAD_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 1
+#define IMXRT_PAD_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 1
+
+#define IMXRT_PAD_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 2
+#define IMXRT_PAD_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 2
+#define IMXRT_PAD_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 2
+#define IMXRT_PAD_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 1
+#define IMXRT_PAD_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 2
+#define IMXRT_PAD_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0 0x8 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0 0x9 0
+#define IMXRT_PAD_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0 0x8 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0 0x8 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 1
+
+#define IMXRT_PAD_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 1
+
+#define IMXRT_PAD_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 1
+#define IMXRT_PAD_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 1
+#define IMXRT_PAD_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 2
+
+#define IMXRT_PAD_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 1
+#define IMXRT_PAD_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 1
+#define IMXRT_PAD_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 2
+
+#define IMXRT_PAD_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 1
+#define IMXRT_PAD_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 2
+#define IMXRT_PAD_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 2
+
+#define IMXRT_PAD_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 1
+#define IMXRT_PAD_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0 0x9 0
+#define IMXRT_PAD_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0 0xA 0
+
+#define IMXRT_PAD_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 1
+#define IMXRT_PAD_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 1
+
+#define IMXRT_PAD_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0 0x1 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 1
+#define IMXRT_PAD_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 2
+#define IMXRT_PAD_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 1
+#define IMXRT_PAD_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 1
+
+#define IMXRT_PAD_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0 0x6 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0 0xA 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 3
+
+#define IMXRT_PAD_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0 0x0 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 1
+#define IMXRT_PAD_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0 0x2 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0 0x3 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0 0x4 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0 0x5 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 2
+#define IMXRT_PAD_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0 0x8 0
+#define IMXRT_PAD_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 1
+#define IMXRT_PAD_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0 0xA 0
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_IMXRT_IMXRT1050_PINFUNC_H */
diff --git a/bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi b/bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi
new file mode 100644
index 0000000000..8f7083e2c4
--- /dev/null
+++ b/bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi
@@ -0,0 +1,1224 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020-2023 embedded brains GmbH & Co. KG
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen: chosen {};
+
+ aliases {
+ acmp1 = &acmp1;
+ acmp2 = &acmp2;
+ acmp3 = &acmp3;
+ acmp4 = &acmp4;
+ adc-etc = &adc_etc;
+ aips-1 = &aips_1;
+ aips-2 = &aips_2;
+ aips-3 = &aips_3;
+ aips-4 = &aips_4;
+ aips-m7 = &aips_m7;
+ analog = &analog;
+ aoi1 = &aoi1;
+ aoi2 = &aoi2;
+ asrc = &asrc;
+ caam = &caam;
+ can1 = &can1;
+ can2 = &can2;
+ can3 = &can3;
+ ccm = &ccm;
+ csi = &csi;
+ dac = &dac;
+ dcdc = &dcdc;
+ dma-mux0 = &dma_mux0;
+ dma-mux1-lpsr = &dma_mux1_lpsr;
+ edma = &edma;
+ edma-lpsr = &edma_lpsr;
+ elcdif = &elcdif;
+ emvsim1 = &emvsim1;
+ emvsim2 = &emvsim2;
+ ewm = &ewm;
+ fec1 = &fec1;
+ fec2 = &fec2;
+ flexio1 = &flexio1;
+ flexio2 = &flexio2;
+ flexpwm1 = &flexpwm1;
+ flexpwm2 = &flexpwm2;
+ flexpwm3 = &flexpwm3;
+ flexpwm4 = &flexpwm4;
+ flexram-cm7 = &flexram_cm7;
+ flexspi1 = &flexspi1;
+ flexspi2 = &flexspi2;
+ gpc = &gpc;
+ /*
+ * Linux convention starts GPIO at 0. Therefore the driver
+ * shared with i.MX6 expects 0 too. The driver also expects only
+ * numbers. So m7_2 is 13 and m7_3 is 14.
+ */
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ gpio7 = &gpio8;
+ gpio8 = &gpio9;
+ gpio9 = &gpio10;
+ gpio10 = &gpio11;
+ gpio11 = &gpio12;
+ gpio12 = &gpio13;
+ gpio13 = &gpio_m7_2;
+ gpio14 = &gpio_m7_3;
+ gpt1 = &gpt1;
+ gpt2 = &gpt2;
+ gpt3 = &gpt3;
+ gpt4 = &gpt4;
+ gpt5 = &gpt5;
+ gpt6 = &gpt6;
+ iee = &iee;
+ iee-apc = &iee_apc;
+ iomuxc = &iomuxc;
+ iomuxc-gpr = &iomuxc_gpr;
+ iomuxc-lpsr = &iomuxc_lpsr;
+ iomuxc-lpsr-gpr = &iomuxc_lpsr_gpr;
+ iomuxc-snvs = &iomuxc_snvs;
+ iomuxc-snvs-gpr = &iomuxc_snvs_gpr;
+ keymgr = &keymgr;
+ kpp = &kpp;
+ lcdifv2 = &lcdifv2;
+ lpadc1 = &lpadc1;
+ lpadc2 = &lpadc2;
+ lpi2c1 = &lpi2c1;
+ lpi2c2 = &lpi2c2;
+ lpi2c3 = &lpi2c3;
+ lpi2c4 = &lpi2c4;
+ lpi2c5 = &lpi2c5;
+ lpi2c6 = &lpi2c6;
+ lpspi1 = &lpspi1;
+ lpspi2 = &lpspi2;
+ lpspi3 = &lpspi3;
+ lpspi4 = &lpspi4;
+ lpspi5 = &lpspi5;
+ lpspi6 = &lpspi6;
+ lpuart1 = &lpuart1;
+ lpuart10 = &lpuart10;
+ lpuart11 = &lpuart11;
+ lpuart12 = &lpuart12;
+ lpuart2 = &lpuart2;
+ lpuart3 = &lpuart3;
+ lpuart4 = &lpuart4;
+ lpuart5 = &lpuart5;
+ lpuart6 = &lpuart6;
+ lpuart7 = &lpuart7;
+ lpuart8 = &lpuart8;
+ lpuart9 = &lpuart9;
+ mecc1 = &mecc1;
+ mecc2 = &mecc2;
+ mipi-csi = &mipi_csi;
+ mipi-dsi = &mipi_dsi;
+ mu = μ
+ nvic = &nvic;
+ ocotp = &ocotp;
+ pdm = &pdm;
+ pgmc = &pgmc;
+ pit1 = &pit1;
+ pit2 = &pit2;
+ pxp = &pxp;
+ qdc1 = &qdc1;
+ qdc2 = &qdc2;
+ qdc3 = &qdc3;
+ qdc4 = &qdc4;
+ qtimer1 = &qtimer1;
+ qtimer2 = &qtimer2;
+ qtimer3 = &qtimer3;
+ qtimer4 = &qtimer4;
+ rdc = &rdc;
+ rdc-semaphore1 = &rdc_semaphore1;
+ rdc-semaphore2 = &rdc_semaphore2;
+ romcp = &romcp;
+ sai1 = &sai1;
+ sai2 = &sai2;
+ sai3 = &sai3;
+ sai4 = &sai4;
+ semc = &semc;
+ snvs = &snvs;
+ snvs-sram = &snvs_sram;
+ spdif = &spdif;
+ src = &src;
+ ssarc-hp = &ssarc_hp;
+ ssarc-lp = &ssarc_lp;
+ systick = &systick;
+ usbotg1 = &usbotg1;
+ usbotg2 = &usbotg2;
+ usbphy1 = &usbphy1;
+ usbphy2 = &usbphy2;
+ usdhc1 = &usdhc1;
+ usdhc2 = &usdhc2;
+ video-mux = &video_mux;
+ wdog1 = &wdog1;
+ wdog2 = &wdog2;
+ wdog3 = &wdog3;
+ wdog4 = &wdog4;
+ xbar1 = &xbar1;
+ xbar2 = &xbar2;
+ xbar3 = &xbar3;
+ xecc-flexspi1 = &xecc_flexspi1;
+ xecc-flexspi2 = &xecc_flexspi2;
+ xecc-semc = &xecc_semc;
+ xrdc2-mgr-m4 = &xrdc2_mgr_m4;
+ xrdc2-mgr-m7 = &xrdc2_mgr_m7;
+ };
+
+ nvic: interrupt-controller at e000e100 {
+ compatible = "arm,armv7m-nvic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe000e100 0xc00>;
+ };
+
+ systick: timer at e000e010 {
+ compatible = "arm,armv7m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&nvic>;
+ ranges;
+
+ aips_1: aips-bus at 40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x00400000>;
+ ranges;
+
+ mecc1: mecc at 40014000 {
+ reg = <0x40014000 0x4000>;
+ interrupts = <206>, <207>;
+ };
+
+ mecc2: mecc at 40018000 {
+ reg = <0x40018000 0x4000>;
+ interrupts = <208>, <209>;
+ };
+
+ xecc_flexspi1: xecc_flexspi at 4001c000 {
+ reg = <0x4001c000 0x4000>;
+ interrupts = <210>, <211>;
+ };
+
+ xecc_flexspi2: xecc_flexspi at 40020000 {
+ reg = <0x40020000 0x4000>;
+ interrupts = <212>, <213>;
+ };
+
+ xecc_semc: xecc_semc at 40024000 {
+ reg = <0x40024000 0x4000>;
+ interrupts = <214>, <215>;
+ };
+
+ flexram_cm7: flexram at 40028000 {
+ reg = <0x40028000 0x4000>;
+ interrupts = <50>;
+ };
+
+ ewm: ewm at 4002c000 {
+ reg = <0x4002c000 0x4000>;
+ interrupts = <114>;
+ };
+
+ wdog1: wdog at 40030000 {
+ reg = <0x40030000 0x4000>;
+ interrupts = <112>;
+ };
+
+ wdog2: wdog at 40034000 {
+ reg = <0x40034000 0x4000>;
+ interrupts = <65>;
+ };
+
+ wdog3: wdog at 40038000 {
+ reg = <0x40038000 0x4000>;
+ interrupts = <113>;
+ };
+
+ xbar1: xbar at 4003c000 {
+ reg = <0x4003c000 0x4000>;
+ interrupts = <143>, <144>;
+ };
+
+ xbar2: xbar at 40040000 {
+ reg = <0x40040000 0x4000>;
+ };
+
+ xbar3: xbar at 40044000 {
+ reg = <0x40044000 0x4000>;
+ };
+
+ adc_etc: adc at 40048000 {
+ reg = <0x40048000 0x4000>;
+ interrupts = <145>, <146>, <147>, <148>, <149>;
+ };
+
+ lpadc1: adc at 40050000 {
+ reg = <0x40050000 0x4000>;
+ interrupts = <88>;
+ };
+
+ lpadc2: adc at 40054000 {
+ reg = <0x40054000 0x4000>;
+ interrupts = <89>;
+ };
+
+ dac: dac at 40064000 {
+ reg = <0x40064000 0x4000>;
+ interrupts = <63>;
+ };
+
+ iee_apc: iee_apc at 40068000 {
+ reg = <0x40068000 0x4000>;
+ };
+
+ iee: iee at 4006c000 {
+ reg = <0x4006c000 0x4000>;
+ };
+
+ edma: dma-controller at 40070000 {
+ compatible = "fsl,imxrt-edma";
+ /*
+ * Use DMA cells just like Linux:
+ * First cell is the DMAMUX which is allways 0
+ * in our case. Second one is the request
+ * source.
+ */
+ #dma-cells = <2>;
+ reg = <0x40070000 0x4000>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>,
+ <12>, <13>, <14>, <15>,
+ <16>;
+ };
+
+ dma_mux0: dma_mux at 40074000 {
+ reg = <0x40074000 0x4000>;
+ };
+
+ lpuart1: uart at 4007c000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x4007c000 0x4000>;
+ interrupts = <20>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS1";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 8>, <&edma 0 9>;
+ };
+
+ lpuart2: uart at 40080000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40080000 0x4000>;
+ interrupts = <21>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS2";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 10>, <&edma 0 11>;
+ };
+
+ lpuart3: uart at 40084000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40084000 0x4000>;
+ interrupts = <22>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS3";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 12>, <&edma 0 13>;
+ };
+
+ lpuart4: uart at 40088000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40088000 0x4000>;
+ interrupts = <23>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS4";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 14>, <&edma 0 15>;
+ };
+
+ lpuart5: uart at 4008c000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x4008c000 0x4000>;
+ interrupts = <24>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS5";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 16>, <&edma 0 17>;
+ };
+
+ lpuart6: uart at 40090000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40090000 0x4000>;
+ interrupts = <25>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS6";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 18>, <&edma 0 19>;
+ };
+
+ lpuart7: uart at 40094000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40094000 0x4000>;
+ interrupts = <26>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS7";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 20>, <&edma 0 21>;
+ };
+
+ lpuart8: uart at 40098000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40098000 0x4000>;
+ interrupts = <27>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS8";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 22>, <&edma 0 23>;
+ };
+
+ lpuart9: uart at 4009c000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x4009c000 0x4000>;
+ interrupts = <28>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS9";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 24>, <&edma 0 25>;
+ };
+
+ lpuart10: uart at 400a0000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x400a0000 0x4000>;
+ interrupts = <29>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS10";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 26>, <&edma 0 27>;
+ };
+
+ flexio1: flexio at 400ac000 {
+ reg = <0x400ac000 0x4000>;
+ interrupts = <110>;
+ };
+
+ flexio2: flexio at 400b0000 {
+ reg = <0x400b0000 0x4000>;
+ interrupts = <111>;
+ };
+
+ aoi1: aoi at 400b8000 {
+ reg = <0x400b8000 0x4000>;
+ };
+
+ aoi2: aoi at 400bc000 {
+ reg = <0x400bc000 0x4000>;
+ };
+
+ can1: can at 400c4000 {
+ reg = <0x400c4000 0x4000>;
+ interrupts = <44>, <45>;
+ };
+
+ can2: can at 400c8000 {
+ reg = <0x400c8000 0x4000>;
+ interrupts = <46>, <47>;
+ };
+
+ flexspi1: spi at 400cc000 {
+ reg = <0x400cc000 0x4000>;
+ interrupts = <130>;
+ };
+
+ flexspi2: spi at 400d0000 {
+ reg = <0x400d0000 0x4000>;
+ interrupts = <131>;
+ };
+
+ semc: semc at 400d4000 {
+ reg = <0x400d4000 0x4000>;
+ interrupts = <132>;
+ };
+
+ pit1: pit at 400d8000 {
+ reg = <0x400d8000 0x4000>;
+ interrupts = <155>;
+ };
+
+ kpp: kpp at 400e0000 {
+ reg = <0x400e0000 0x4000>;
+ interrupts = <51>;
+ };
+
+ iomuxc_gpr: iomuxc_gpr at 400e4000 {
+ reg = <0x400e4000 0x4000>;
+ interrupts = <53>;
+ };
+
+ iomuxc: pinctrl at 400e8000 {
+ compatible = "nxp,imxrt1166-iomuxc",
+ "nxp,imxrt1050-iomuxc";
+ reg = <0x400e8000 0x4000>;
+ };
+
+ gpt1: timer at 400ec000 {
+ reg = <0x400ec000 0x4000>;
+ interrupts = <119>;
+ };
+
+ gpt2: timer at 400f0000 {
+ reg = <0x400f0000 0x4000>;
+ interrupts = <120>;
+ };
+
+ gpt3: timer at 400f4000 {
+ reg = <0x400f4000 0x4000>;
+ interrupts = <121>;
+ };
+
+ gpt4: timer at 400f8000 {
+ reg = <0x400f8000 0x4000>;
+ interrupts = <122>;
+ };
+
+ gpt5: timer at 400fc000 {
+ reg = <0x400fc000 0x4000>;
+ interrupts = <123>;
+ };
+
+ gpt6: timer at 40100000 {
+ reg = <0x40100000 0x4000>;
+ interrupts = <124>;
+ };
+
+ lpi2c1: i2c at 40104000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x40104000 0x4000>;
+ interrupts = <32>;
+ status = "disabled";
+ rtems,path = "/dev/i2c1";
+ dmas = <&edma 0 48>;
+ };
+
+ lpi2c2: i2c at 40108000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x40108000 0x4000>;
+ interrupts = <33>;
+ status = "disabled";
+ rtems,path = "/dev/i2c2";
+ dmas = <&edma 0 49>;
+ };
+
+ lpi2c3: i2c at 4010c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x4010c000 0x4000>;
+ interrupts = <34>;
+ status = "disabled";
+ rtems,path = "/dev/i2c3";
+ dmas = <&edma 0 50>;
+ };
+
+ lpi2c4: i2c at 40110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x40110000 0x4000>;
+ interrupts = <35>;
+ status = "disabled";
+ rtems,path = "/dev/i2c4";
+ dmas = <&edma 0 51>;
+ };
+
+ lpspi1: spi at 40114000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40114000 0x4000>;
+ interrupts = <38>;
+ status = "disabled";
+ rtems,path = "/dev/spi1";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 37>, <&edma 0 36>;
+ };
+
+ lpspi2: spi at 40118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40118000 0x4000>;
+ interrupts = <39>;
+ status = "disabled";
+ rtems,path = "/dev/spi2";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 39>, <&edma 0 38>;
+ };
+
+ lpspi3: spi at 4011c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x4011c000 0x4000>;
+ interrupts = <40>;
+ status = "disabled";
+ rtems,path = "/dev/spi3";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 41>, <&edma 0 40>;
+ };
+
+ lpspi4: spi at 40120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40120000 0x4000>;
+ interrupts = <41>;
+ status = "disabled";
+ rtems,path = "/dev/spi4";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 43>, <&edma 0 42>;
+ };
+
+ gpio1: gpio at 4012c000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x4012c000 0x4000>;
+ interrupts = <100>, <101>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 40130000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40130000 0x4000>;
+ interrupts = <102>, <103>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 40134000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40134000 0x4000>;
+ interrupts = <104>, <105>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 40138000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40138000 0x4000>;
+ interrupts = <106>, <107>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 4013c000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x4013c000 0x4000>;
+ interrupts = <108>, <109>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio at 40140000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40140000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ emvsim1: emvsim at 40154000 {
+ reg = <0x40154000 0x4000>;
+ interrupts = <204>;
+ };
+
+ emvsim2: emvsim at 40158000 {
+ reg = <0x40158000 0x4000>;
+ interrupts = <205>;
+ };
+
+ qtimer1: timer at 4015c000 {
+ compatible = "nxp,imxrt-qtimer";
+ reg = <0x4015c000 0x4000>;
+ interrupts = <171>;
+ };
+
+ qtimer2: timer at 40160000 {
+ compatible = "nxp,imxrt-qtimer";
+ reg = <0x40160000 0x4000>;
+ interrupts = <172>;
+ };
+
+ qtimer3: timer at 40164000 {
+ compatible = "nxp,imxrt-qtimer";
+ reg = <0x40164000 0x4000>;
+ interrupts = <173>;
+ };
+
+ qtimer4: timer at 40168000 {
+ compatible = "nxp,imxrt-qtimer";
+ reg = <0x40168000 0x4000>;
+ interrupts = <174>;
+ };
+
+ qdc1: qdc at 40174000 {
+ reg = <0x40174000 0x4000>;
+ interrupts = <165>;
+ };
+
+ qdc2: qdc at 40178000 {
+ reg = <0x40178000 0x4000>;
+ interrupts = <166>;
+ };
+
+ qdc3: qdc at 4017c000 {
+ reg = <0x4017c000 0x4000>;
+ interrupts = <167>;
+ };
+
+ qdc4: qdc at 40180000 {
+ reg = <0x40180000 0x4000>;
+ interrupts = <168>;
+ };
+
+ flexpwm1: pwm at 4018c000 {
+ compatible = "nxp,imxrt-flexpwm";
+ reg = <0x4018c000 0x4000>;
+ interrupts = <125>, <126>, <127>, <128>, <129>;
+ };
+
+ flexpwm2: pwm at 40190000 {
+ compatible = "nxp,imxrt-flexpwm";
+ reg = <0x40190000 0x4000>;
+ interrupts = <177>, <178>, <179>, <180>, <181>;
+ };
+
+ flexpwm3: pwm at 40194000 {
+ compatible = "nxp,imxrt-flexpwm";
+ reg = <0x40194000 0x4000>;
+ interrupts = <182>, <183>, <184>, <185>, <186>;
+ };
+
+ flexpwm4: pwm at 40198000 {
+ compatible = "nxp,imxrt-flexpwm";
+ reg = <0x40198000 0x4000>;
+ interrupts = <187>, <188>, <189>, <190>, <191>;
+ };
+
+ acmp1: acmp at 401a4000 {
+ reg = <0x401a4000 0x4000>;
+ interrupts = <157>;
+ };
+
+ acmp2: acmp at 401a8000 {
+ reg = <0x401a8000 0x4000>;
+ interrupts = <158>;
+ };
+
+ acmp3: acmp at 401ac000 {
+ reg = <0x401ac000 0x4000>;
+ interrupts = <159>;
+ };
+
+ acmp4: acmp at 401b0000 {
+ reg = <0x401b0000 0x4000>;
+ interrupts = <160>;
+ };
+ };
+
+ aips_2: aips-bus at 40400000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40400000 0x00400000>;
+ ranges;
+
+ spdif: spdif at 40400000 {
+ reg = <0x40400000 0x4000>;
+ interrupts = <82>;
+ };
+
+ sai1: sai at 40404000 {
+ reg = <0x40404000 0x4000>;
+ interrupts = <76>;
+ };
+
+ sai2: sai at 40408000 {
+ reg = <0x40408000 0x4000>;
+ interrupts = <77>;
+ };
+
+ sai3: sai at 4040c000 {
+ reg = <0x4040c000 0x4000>;
+ interrupts = <78>, <79>;
+ };
+
+ asrc: asrc at 40410000 {
+ reg = <0x40410000 0x4000>;
+ interrupts = <97>;
+ };
+
+ usdhc1: sdhci at 40418000 {
+ reg = <0x40418000 0x4000>;
+ interrupts = <133>;
+ compatible = "fsl,imxrt1160-usdhc", "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: sdhci at 4041c000 {
+ reg = <0x4041c000 0x4000>;
+ interrupts = <134>;
+ compatible = "fsl,imxrt1160-usdhc", "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+ bus-width = <8>;
+ status = "disabled";
+ };
+
+ fec1: ethernet at 40420000 {
+ compatible = "fsl,imxrt-fec", "fsl,imx6ul-fec";
+ reg = <0x40420000 0x4000>;
+ interrupt-names = "int0", "int1", "int2", "pps";
+ interrupts = <139>, <140>, <141>, <142>;
+ fsl,num-tx-queues = <1>;
+ fsl,num-rx-queues = <1>;
+ phy-mode = "grmii";
+ status = "disabled";
+ };
+
+ fec2: ethernet at 40424000 {
+ compatible = "fsl,imxrt-fec", "fsl,imx6ul-fec";
+ reg = <0x40424000 0x4000>;
+ interrupt-names = "int0", "pps";
+ interrupts = <137>, <138>;
+ fsl,num-tx-queues = <1>;
+ fsl,num-rx-queues = <1>;
+ phy-mode = "rmii";
+ status = "disabled";
+ };
+
+ usbotg2: usb at 4042c000 {
+ reg = <0x4042c000 0x4000>;
+ interrupts = <135>;
+ };
+
+ usbotg1: usb at 40430000 {
+ reg = <0x40430000 0x4000>;
+ interrupts = <136>;
+ };
+
+ usbphy1: usbphy at 40434000 {
+ reg = <0x40434000 0x4000>;
+ interrupts = <90>;
+ };
+
+ usbphy2: usbphy at 40438000 {
+ reg = <0x40438000 0x4000>;
+ interrupts = <91>;
+ };
+
+ caam: caam at 40440000 {
+ reg = <0x40440000 0x100000>;
+ interrupts = <69>, <70>, <71>, <72>, <73>, <74>;
+ };
+ };
+
+ aips_3: aips-bus at 40800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40800000 0x00400000>;
+ ranges;
+
+ csi: csi at 40800000 {
+ reg = <0x40800000 0x4000>;
+ interrupts = <56>;
+ };
+
+ elcdif: lcdif at 40804000 {
+ reg = <0x40804000 0x4000>;
+ interrupts = <54>;
+ };
+
+ lcdifv2: lcdif at 40808000 {
+ reg = <0x40808000 0x4000>;
+ interrupts = <55>;
+ };
+
+ mipi_dsi: dsi at 4080c000 {
+ reg = <0x4080c000 0x4000>;
+ interrupts = <59>;
+ };
+
+ mipi_csi: csi at 40810000 {
+ reg = <0x40810000 0x4000>;
+ interrupts = <58>;
+ };
+
+ pxp: pxp at 40814000 {
+ reg = <0x40814000 0x4000>;
+ interrupts = <57>;
+ };
+
+ video_mux: video_mux at 40818000 {
+ reg = <0x40818000 0x4000>;
+ interrupts = <95>, <96>;
+ };
+ };
+
+ aips_4: aips-bus at 40c00000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40c00000 0x00400000>;
+ ranges;
+
+ gpc: gpc at 40c00000 {
+ reg = <0x40c00000 0x4000>;
+ interrupts = <117>;
+ };
+
+ src: src at 40c04000 {
+ reg = <0x40c04000 0x4000>;
+ };
+
+ iomuxc_lpsr: iomuxc_lpsr at 40c08000 {
+ compatible = "nxp,imxrt1166-iomuxc",
+ "nxp,imxrt1050-iomuxc";
+ reg = <0x40c08000 0x4000>;
+ };
+
+ iomuxc_lpsr_gpr: iomuxc_lpsr_gpr at 40c0c000 {
+ reg = <0x40c0c000 0x4000>;
+ };
+
+ wdog4: wdog at 40c10000 {
+ reg = <0x40c10000 0x4000>;
+ };
+
+ edma_lpsr: dma-controller at 40c14000 {
+ compatible = "fsl,imxrt-edma";
+ #dma-cells = <2>;
+ reg = <0x40c14000 0x4000>;
+ };
+
+ dma_mux1_lpsr: dma_mux at 40c18000 {
+ reg = <0x40c18000 0x4000>;
+ };
+
+ pdm: pdm at 40c20000 {
+ reg = <0x40c20000 0x4000>;
+ interrupts = <200>, <201>, <202>, <203>;
+ };
+
+ lpuart11: uart at 40c24000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40c24000 0x4000>;
+ interrupts = <30>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS11";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 28>, <&edma 0 29>;
+ };
+
+ lpuart12: uart at 40c28000 {
+ compatible = "nxp,imxrt-lpuart";
+ reg = <0x40c28000 0x4000>;
+ interrupts = <31>;
+ status = "disabled";
+ rtems,path = "/dev/ttyS12";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 30>, <&edma 0 31>;
+ };
+
+ lpspi5: spi at 40c2c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40c2c000 0x4000>;
+ interrupts = <42>;
+ status = "disabled";
+ rtems,path = "/dev/spi5";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 45>, <&edma 0 44>;
+ };
+
+ lpspi6: spi at 40c30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpspi";
+ reg = <0x40c30000 0x4000>;
+ interrupts = <43>;
+ status = "disabled";
+ rtems,path = "/dev/spi6";
+ dma-names = "tx", "rx";
+ dmas = <&edma 0 47>, <&edma 0 46>;
+ };
+
+ lpi2c5: i2c at 40c34000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x40c34000 0x4000>;
+ interrupts = <36>;
+ status = "disabled";
+ rtems,path = "/dev/i2c5";
+ dmas = <&edma 0 52>;
+ };
+
+ lpi2c6: i2c at 40c38000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imxrt-lpi2c";
+ reg = <0x40c38000 0x4000>;
+ interrupts = <37>;
+ status = "disabled";
+ rtems,path = "/dev/i2c6";
+ dmas = <&edma 0 53>;
+ };
+
+ can3: can at 40c3c000 {
+ reg = <0x40c3c000 0x4000>;
+ interrupts = <48>, <49>;
+ };
+
+ sai4: sai at 40c40000 {
+ reg = <0x40c40000 0x4000>;
+ interrupts = <80>, <81>;
+ };
+
+ rdc_semaphore1: rdc_semaphore at 40c44000 {
+ reg = <0x40c44000 0x4000>;
+ };
+
+ mu: mu at 40c48000 {
+ reg = <0x40c48000 0x8000>;
+ interrupts = <118>;
+ };
+
+ gpio7: gpio at 40c5c000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c5c000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio8: gpio at 40c60000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c60000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio9: gpio at 40c64000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c64000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio10: gpio at 40c68000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c68000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio11: gpio at 40c6c000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c6c000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio12: gpio at 40c70000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40c70000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ rdc: rdc at 40c78000 {
+ reg = <0x40c78000 0x4000>;
+ interrupts = <92>;
+ };
+
+ keymgr: keymgr at 40c80000 {
+ reg = <0x40c80000 0x4000>;
+ interrupts = <64>;
+ };
+
+ analog: analog at 40c84000 {
+ reg = <0x40c84000 0x4000>;
+ };
+
+ pgmc: pgmc at 40c88000 {
+ reg = <0x40c88000 0x4000>;
+ };
+
+ snvs: snvs at 40c90000 {
+ reg = <0x40c90000 0x4000>;
+ interrupts = <66>, <67>, <68>;
+ };
+
+ iomuxc_snvs: iomuxc_snvs at 40c94000 {
+ compatible = "nxp,imxrt1166-iomuxc",
+ "nxp,imxrt1050-iomuxc";
+ reg = <0x40c94000 0x4000>;
+ };
+
+ iomuxc_snvs_gpr: iomuxc_snvs_gpr at 40c98000 {
+ reg = <0x40c98000 0x4000>;
+ };
+
+ snvs_sram: snvs_sram at 40c9c000 {
+ reg = <0x40c9c000 0x4000>;
+ };
+
+ gpio13: gpio at 40ca0000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x40ca0000 0x4000>;
+ interrupts = <93>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ romcp: romcp at 40ca4000 {
+ reg = <0x40ca4000 0x4000>;
+ };
+
+ dcdc: dcdc at 40ca8000 {
+ reg = <0x40ca8000 0x4000>;
+ };
+
+ ocotp: ocotp at 40cac000 {
+ reg = <0x40cac000 0x4000>;
+ interrupts = <115>, <116>;
+ };
+
+ pit2: pit at 40cb0000 {
+ reg = <0x40cb0000 0x4000>;
+ interrupts = <156>;
+ };
+
+ ssarc_hp: ssarc at 40cb4000 {
+ reg = <0x40cb4000 0x4000>;
+ };
+
+ ssarc_lp: ssarc at 40cb8000 {
+ reg = <0x40cb8000 0x4000>;
+ };
+
+ ccm: ccm at 40cc0000 {
+ reg = <0x40cc0000 0x8000>;
+ };
+
+ rdc_semaphore2: rdc_semaphore at 40ccc000 {
+ reg = <0x40ccc000 0x4000>;
+ };
+
+ xrdc2_mgr_m4: xrdc2_mgr at 40cd0000 {
+ reg = <0x40cd0000 0x10000>;
+ };
+
+ xrdc2_mgr_m7: xrdc2_mgr at 40ce0000 {
+ reg = <0x40ce0000 0x10000>;
+ };
+ };
+
+ aips_m7: aips-bus at 42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x42000000 0x00100000>;
+ ranges;
+
+ gpio_m7_2: gpio at 42008000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x42008000 0x4000>;
+ interrupts = <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio_m7_3: gpio at 4200c000 {
+ compatible = "fsl,imxrt-gpio",
+ "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x4200c000 0x4000>;
+ interrupts = <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+};
diff --git a/bsps/arm/imxrt/start/bspstart.c b/bsps/arm/imxrt/start/bspstart.c
index 7398ffbe73..1d583d7ca4 100644
--- a/bsps/arm/imxrt/start/bspstart.c
+++ b/bsps/arm/imxrt/start/bspstart.c
@@ -59,6 +59,13 @@ static void imxrt_disable_wait_mode(void)
* every WFI.
*/
CLOCK_SetMode(kCLOCK_ModeRun);
+#elif IMXRT_IS_MIMXRT11xx
+ /*
+ * i.MX RT11xx doesn't support disabling power saving for WFI. On the other
+ * hand it doesn't have a separate interrupt controller like the i.MX RT1050.
+ * So a power save during WFI is only annoying during debugging but doesn't
+ * hurt otherwise.
+ */
#else
#error Disabling wait mode not implemented for this chip.
#endif
@@ -129,6 +136,22 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
return intr[0];
}
+/*
+ * Clock frequencies for peripherals like SD card. These are used by libbsd
+ * drivers.
+ */
+#if IMXRT_IS_MIMXRT11xx
+uint32_t
+imx_ccm_sdhci_hz(void)
+{
+ /*
+ * We don't know which SDHCI is used. So just return the clock frequency
+ * of the first SDHCI and hope the best.
+ */
+ return CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1);
+}
+#endif
+
/* Make sure to pull in the flash headers */
__attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data;
__attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table;
diff --git a/bsps/arm/imxrt/start/bspstarthooks.c b/bsps/arm/imxrt/start/bspstarthooks.c
index 4814373641..c10d0dbcfe 100644
--- a/bsps/arm/imxrt/start/bspstarthooks.c
+++ b/bsps/arm/imxrt/start/bspstarthooks.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
+ * Copyright (c) 2013-2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,8 +35,6 @@
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
- /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user
- * friendly if that would be done here with a readable structure. */
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}
diff --git a/bsps/arm/imxrt/start/imxrt-ffec-init.c b/bsps/arm/imxrt/start/imxrt-ffec-init.c
index 5cdcfcdab8..c0a8e168e3 100644
--- a/bsps/arm/imxrt/start/imxrt-ffec-init.c
+++ b/bsps/arm/imxrt/start/imxrt-ffec-init.c
@@ -41,6 +41,7 @@ void imxrt_ffec_init(void)
fdt = bsp_fdt_get();
+#if IMXRT_IS_MIMXRT10xx
const clock_enet_pll_config_t config = {
.enableClkOutput = true,
.enableClkOutput25M = false,
@@ -50,6 +51,9 @@ void imxrt_ffec_init(void)
CLOCK_InitEnetPll(&config);
iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#else
+ iomuxc_gpr->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
+#endif
node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
if (node >= 0) {
diff --git a/spec/build/bsps/arm/imxrt/bspimxrt1166-cm7-saltshaker.yml b/spec/build/bsps/arm/imxrt/bspimxrt1166-cm7-saltshaker.yml
new file mode 100644
index 0000000000..b9bdc3ca8a
--- /dev/null
+++ b/spec/build/bsps/arm/imxrt/bspimxrt1166-cm7-saltshaker.yml
@@ -0,0 +1,32 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: imxrt1166-cm7-saltshaker
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: imxrt
+includes:
+- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166
+- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers
+- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/xip
+- bsps/arm/imxrt/mcux-sdk/drivers/common
+- bsps/arm/imxrt/mcux-sdk/drivers/semc
+install:
+- destination: ${BSP_INCLUDEDIR}/imxrt
+ source:
+ - bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
+ - bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi
+ - bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h
+links:
+- role: build-dependency
+ uid: obj-mimxrt1166-cm7
+source:
+- bsps/arm/imxrt/boards/saltshaker/clock_config.c
+- bsps/arm/imxrt/boards/saltshaker/dcd.c
+- bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c
+- bsps/arm/imxrt/boards/saltshaker/pin_mux.c
+- bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
+type: build
diff --git a/spec/build/bsps/arm/imxrt/optmemdtcmsz.yml b/spec/build/bsps/arm/imxrt/optmemdtcmsz.yml
index 2ed8320586..1605ac7953 100644
--- a/spec/build/bsps/arm/imxrt/optmemdtcmsz.yml
+++ b/spec/build/bsps/arm/imxrt/optmemdtcmsz.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x00040000
- enabled-by: true
value: 0x00020000
description: |
diff --git a/spec/build/bsps/arm/imxrt/optmemextramsz.yml b/spec/build/bsps/arm/imxrt/optmemextramsz.yml
index c33ef0f60b..6a40bdecdf 100644
--- a/spec/build/bsps/arm/imxrt/optmemextramsz.yml
+++ b/spec/build/bsps/arm/imxrt/optmemextramsz.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x04000000
- enabled-by: true
value: 0x02000000
description: |
diff --git a/spec/build/bsps/arm/imxrt/optmemflashorigin.yml b/spec/build/bsps/arm/imxrt/optmemflashorigin.yml
index 407114d834..5bcbe827af 100644
--- a/spec/build/bsps/arm/imxrt/optmemflashorigin.yml
+++ b/spec/build/bsps/arm/imxrt/optmemflashorigin.yml
@@ -7,12 +7,14 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x30000000
- enabled-by: true
value: 0x60000000
description: |
Origin of the external flash memory. That can be for example a flash
connected to FlexSPI or to SEMC. The default value is for a HyperFlash
- connected to FlexSPI.
+ connected to FlexSPI or a board specific variant for special BSPs.
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/imxrt/optmemflashsz.yml b/spec/build/bsps/arm/imxrt/optmemflashsz.yml
index 5ec54768c6..b46d15bd4e 100644
--- a/spec/build/bsps/arm/imxrt/optmemflashsz.yml
+++ b/spec/build/bsps/arm/imxrt/optmemflashsz.yml
@@ -7,6 +7,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x00800000
- enabled-by: true
value: 0x04000000
description: |
diff --git a/spec/build/bsps/arm/imxrt/optmemitcmsz.yml b/spec/build/bsps/arm/imxrt/optmemitcmsz.yml
index 37523f5617..5e13d371ac 100644
--- a/spec/build/bsps/arm/imxrt/optmemitcmsz.yml
+++ b/spec/build/bsps/arm/imxrt/optmemitcmsz.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x0003ff00
- enabled-by: true
value: 0x0001ff00
description: |
diff --git a/spec/build/bsps/arm/imxrt/optmemocramorigin.yml b/spec/build/bsps/arm/imxrt/optmemocramorigin.yml
index 359f47d933..6c344ca5b6 100644
--- a/spec/build/bsps/arm/imxrt/optmemocramorigin.yml
+++ b/spec/build/bsps/arm/imxrt/optmemocramorigin.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2023 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x20340000
- enabled-by: true
value: 0x20200000
description: |
diff --git a/spec/build/bsps/arm/imxrt/optmemocramsz.yml b/spec/build/bsps/arm/imxrt/optmemocramsz.yml
index bf9d16c6b8..dd215dfb81 100644
--- a/spec/build/bsps/arm/imxrt/optmemocramsz.yml
+++ b/spec/build/bsps/arm/imxrt/optmemocramsz.yml
@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: 0x00040000
- enabled-by: true
value: 0x00040000
description: |
diff --git a/spec/build/bsps/arm/imxrt/optvariant.yml b/spec/build/bsps/arm/imxrt/optvariant.yml
index 1d18b2869e..68a1f53267 100644
--- a/spec/build/bsps/arm/imxrt/optvariant.yml
+++ b/spec/build/bsps/arm/imxrt/optvariant.yml
@@ -90,6 +90,8 @@ actions:
conf.define("IMXRT_IS_{}xx".format(value[:8]), True)
build-type: option
default:
+- enabled-by: arm/imxrt1166-cm7-saltshaker
+ value: MIMXRT1166DVM6A_cm7
- enabled-by: true
value: MIMXRT1052DVL6B
enabled-by: true
--
2.35.3
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