[PATCH] score/arm: style fixes
Gedare Bloom
gedare at rtems.org
Tue Jul 25 21:54:25 UTC 2023
On Tue, Jul 25, 2023 at 3:38 PM Gedare Bloom <gedare at rtems.org> wrote:
>
> ---
> cpukit/score/cpu/arm/__aeabi_read_tp.c | 2 +-
> cpukit/score/cpu/arm/__tls_get_addr.c | 4 +-
> .../score/cpu/arm/aarch32-psma-init-default.c | 2 +-
> cpukit/score/cpu/arm/aarch32-psma-init.c | 82 ++++-----
> cpukit/score/cpu/arm/arm-exception-default.c | 6 +-
> .../score/cpu/arm/arm-exception-frame-print.c | 159 ++++++++----------
> cpukit/score/cpu/arm/armv4-sync-synchronize.c | 2 +-
> cpukit/score/cpu/arm/armv7-thread-idle.c | 4 +-
> .../score/cpu/arm/armv7m-context-initialize.c | 14 +-
> cpukit/score/cpu/arm/armv7m-context-restore.c | 4 +-
> .../score/cpu/arm/armv7m-exception-default.c | 26 +--
> .../cpu/arm/armv7m-exception-handler-get.c | 4 +-
> .../cpu/arm/armv7m-exception-handler-set.c | 19 +--
> .../cpu/arm/armv7m-exception-priority-get.c | 8 +-
> .../arm/armv7m-exception-priority-handler.c | 8 +-
> .../cpu/arm/armv7m-exception-priority-set.c | 8 +-
> cpukit/score/cpu/arm/armv7m-initialize.c | 2 +-
> cpukit/score/cpu/arm/armv7m-isr-dispatch.c | 20 +--
> cpukit/score/cpu/arm/armv7m-isr-enter-leave.c | 4 +-
> cpukit/score/cpu/arm/armv7m-isr-level-get.c | 2 +-
> cpukit/score/cpu/arm/armv7m-isr-level-set.c | 4 +-
> .../score/cpu/arm/armv7m-isr-vector-install.c | 8 +-
> .../cpu/arm/armv7m-multitasking-start-stop.c | 4 +-
> cpukit/score/cpu/arm/cpu.c | 51 +++---
> 24 files changed, 209 insertions(+), 238 deletions(-)
>
> diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
> index 0f4eba8d9a..e3bc529f18 100644
> --- a/cpukit/score/cpu/arm/__aeabi_read_tp.c
> +++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
> @@ -37,8 +37,8 @@
> #include "config.h"
> #endif
>
> -#include <rtems/score/thread.h>
> #include <rtems/score/percpu.h>
> +#include <rtems/score/thread.h>
>
> #ifndef RTEMS_SMP
>
> diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c
> index 7ef42fdcb4..fe38368812 100644
> --- a/cpukit/score/cpu/arm/__tls_get_addr.c
> +++ b/cpukit/score/cpu/arm/__tls_get_addr.c
> @@ -47,8 +47,8 @@ void *__tls_get_addr(const TLS_Index *ti);
> void *__tls_get_addr(const TLS_Index *ti)
> {
> const Thread_Control *executing = _Thread_Get_executing();
> - void *tls_data = (char *) executing->Registers.thread_id
> - + _TLS_Get_thread_control_block_area_size();
> + void *tls_data = (char *) executing->Registers.thread_id;
This one I manually edited, as the alignment and breaking causes it to
be quite ugly. I should add a blank line here though, after the decls.
> + tls_data += _TLS_Get_thread_control_block_area_size();
>
> assert(ti->module == 1);
>
> diff --git a/cpukit/score/cpu/arm/aarch32-psma-init-default.c b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
> index 615e7a528a..8ef8b5233a 100644
> --- a/cpukit/score/cpu/arm/aarch32-psma-init-default.c
> +++ b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
> @@ -42,7 +42,7 @@
>
> #if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'R'
>
> -void _AArch32_PMSA_Initialize_default( void )
> +void _AArch32_PMSA_Initialize_default(void)
> {
> _AArch32_PMSA_Initialize(
> AARCH32_PMSA_MEM_ATTR(
> diff --git a/cpukit/score/cpu/arm/aarch32-psma-init.c b/cpukit/score/cpu/arm/aarch32-psma-init.c
> index 93a3673a98..b30cb5e308 100644
> --- a/cpukit/score/cpu/arm/aarch32-psma-init.c
> +++ b/cpukit/score/cpu/arm/aarch32-psma-init.c
> @@ -46,7 +46,7 @@
> #include <rtems/score/cpu.h>
>
> #define AARCH32_PMSA_REGION_MAX \
> - ( ( AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT ) + 1 )
> + ((AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT) + 1)
>
> static void _AArch32_PMSA_Configure(
> const AArch32_PMSA_Region *regions,
> @@ -57,36 +57,36 @@ static void _AArch32_PMSA_Configure(
> size_t ri;
> uint32_t sctlr;
>
> - for ( ri = 0 ; ri < region_used; ++ri ) {
> + for ( ri = 0; ri < region_used; ++ri ) {
> uint32_t prbar;
> uint32_t prlar;
> uint32_t attr;
>
> - prbar = regions[ ri ].base;
> - prlar = regions[ ri ].limit;
> - attr = regions[ ri ].attributes;
> + prbar = regions[ri].base;
> + prlar = regions[ri].limit;
> + attr = regions[ri].attributes;
>
> - prbar |= ( attr >> 6 ) & 0x3fU;
> + prbar |= (attr >> 6) & 0x3fU;
> prlar |= attr & 0x3fU;
>
> - _AArch32_Write_prselr( ri );
> + _AArch32_Write_prselr(ri);
> _ARM_Instruction_synchronization_barrier();
> - _AArch32_Write_prbar( prbar );
> - _AArch32_Write_prlar( prlar );
> + _AArch32_Write_prbar(prbar);
> + _AArch32_Write_prlar(prlar);
> }
>
> - for ( ri = region_used ; ri < region_max; ++ri ) {
> - _AArch32_Write_prselr( ri );
> + for ( ri = region_used; ri < region_max; ++ri ) {
> + _AArch32_Write_prselr(ri);
> _ARM_Instruction_synchronization_barrier();
> - _AArch32_Write_prbar( 0 );
> - _AArch32_Write_prlar( 0 );
> + _AArch32_Write_prbar(0);
> + _AArch32_Write_prlar(0);
> }
>
> _ARM_Data_synchronization_barrier();
> - sctlr = _AArch32_Read_sctlr();
> + sctlr = _AArch32_Read_sctlr();
> sctlr |= AARCH32_SCTLR_M | AARCH32_SCTLR_I | AARCH32_SCTLR_C;
> - sctlr &= ~( AARCH32_SCTLR_A | AARCH32_SCTLR_BR );
> - _AArch32_Write_sctlr( sctlr );
> + sctlr &= ~(AARCH32_SCTLR_A | AARCH32_SCTLR_BR);
> + _AArch32_Write_sctlr(sctlr);
> _ARM_Instruction_synchronization_barrier();
> }
>
> @@ -109,16 +109,16 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
> uint32_t attr;
> uint32_t limit;
>
> - base = sections[ si ].begin;
> - end = sections[ si ].end;
> - attr = sections[ si ].attributes;
> + base = sections[si].begin;
> + end = sections[si].end;
> + attr = sections[si].attributes;
>
> if ( base == end ) {
> continue;
> }
>
> - base = RTEMS_ALIGN_DOWN( base, AARCH32_PMSA_MIN_REGION_ALIGN );
> - end = RTEMS_ALIGN_UP( end, AARCH32_PMSA_MIN_REGION_ALIGN );
> + base = RTEMS_ALIGN_DOWN(base, AARCH32_PMSA_MIN_REGION_ALIGN);
> + end = RTEMS_ALIGN_UP(end, AARCH32_PMSA_MIN_REGION_ALIGN);
> limit = end - AARCH32_PMSA_MIN_REGION_ALIGN;
>
> for ( ri = 0; ri < region_used; ++ri ) {
> @@ -126,16 +126,16 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
> uint32_t region_limit;
> uint32_t region_attr;
>
> - region_base = regions[ ri ].base;
> - region_limit = regions[ ri ].limit;
> - region_attr = regions[ ri ].attributes;
> + region_base = regions[ri].base;
> + region_limit = regions[ri].limit;
> + region_attr = regions[ri].attributes;
>
> if ( attr == region_attr ) {
> uint32_t region_end;
>
> if ( end - region_base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {
> /* Extend the region */
> - regions[ ri ].base = base;
> + regions[ri].base = base;
> break;
> }
>
> @@ -143,7 +143,7 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
>
> if ( region_end - base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {
> /* Extend the region */
> - regions[ ri ].limit = limit;
> + regions[ri].limit = limit;
> break;
> }
>
> @@ -161,14 +161,14 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
> }
>
> for ( i = region_used; i > ri; --i ) {
> - regions[ i ] = regions[ i - 1 ];
> + regions[i] = regions[i - 1];
> }
>
> /* New first region */
> ++region_used;
> - regions[ ri ].base = base;
> - regions[ ri ].limit = limit;
> - regions[ ri ].attributes = attr;
> + regions[ri].base = base;
> + regions[ri].limit = limit;
> + regions[ri].attributes = attr;
> break;
> }
> }
> @@ -180,9 +180,9 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
>
> /* New last region */
> ++region_used;
> - regions[ ri ].base = base;
> - regions[ ri ].limit = limit;
> - regions[ ri ].attributes = attr;
> + regions[ri].base = base;
> + regions[ri].limit = limit;
> + regions[ri].attributes = attr;
> }
> }
>
> @@ -196,15 +196,15 @@ void _AArch32_PMSA_Initialize(
> size_t section_count
> )
> {
> - AArch32_PMSA_Region regions[ AARCH32_PMSA_REGION_MAX ];
> - size_t region_max;
> - size_t region_used;
> + AArch32_PMSA_Region regions[AARCH32_PMSA_REGION_MAX];
> + size_t region_max;
> + size_t region_used;
>
> - _AArch32_Write_mair0( memory_attributes_0 );
> - _AArch32_Write_mair1( memory_attributes_1 );
> + _AArch32_Write_mair0(memory_attributes_0);
> + _AArch32_Write_mair1(memory_attributes_1);
>
> - region_max = ( _AArch32_Read_mpuir() & AARCH32_MPUIR_REGION_MASK ) >>
> - AARCH32_MPUIR_REGION_SHIFT;
> + region_max = (_AArch32_Read_mpuir() & AARCH32_MPUIR_REGION_MASK) >>
> + AARCH32_MPUIR_REGION_SHIFT;
>
> region_used = _AArch32_PMSA_Map_sections_to_regions(
> sections,
> @@ -214,7 +214,7 @@ void _AArch32_PMSA_Initialize(
> );
>
> if ( region_used > 0 ) {
> - _AArch32_PMSA_Configure( regions, region_used, region_max );
> + _AArch32_PMSA_Configure(regions, region_used, region_max);
> }
> }
>
> diff --git a/cpukit/score/cpu/arm/arm-exception-default.c b/cpukit/score/cpu/arm/arm-exception-default.c
> index 02df769287..190c2bf68d 100644
> --- a/cpukit/score/cpu/arm/arm-exception-default.c
> +++ b/cpukit/score/cpu/arm/arm-exception-default.c
> @@ -38,10 +38,10 @@
> #include "config.h"
> #endif
>
> -#include <rtems/score/cpu.h>
> #include <rtems/fatal.h>
> +#include <rtems/score/cpu.h>
>
> -void _ARM_Exception_default( CPU_Exception_frame *frame )
> +void _ARM_Exception_default(CPU_Exception_frame *frame)
> {
> - rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
> + rtems_fatal(RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame);
> }
> diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-frame-print.c
> index b089648184..c625cf2479 100644
> --- a/cpukit/score/cpu/arm/arm-exception-frame-print.c
> +++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c
> @@ -46,12 +46,12 @@
> #endif
> #include <rtems/bspIo.h>
>
> -static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
> +static void _ARM_VFP_context_print(const ARM_VFP_context *vfp_context)
> {
> #ifdef ARM_MULTILIB_VFP
> if ( vfp_context != NULL ) {
> const uint64_t *dx = &vfp_context->register_d0;
> - int i;
> + int i;
>
> printk(
> "FPEXC = 0x%08" PRIx32 "\nFPSCR = 0x%08" PRIx32 "\n",
> @@ -67,138 +67,119 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
> int regcount = 0;
> #endif
> for ( i = 0; i < regcount; ++i ) {
> - uint32_t low = (uint32_t) dx[i];
> + uint32_t low = (uint32_t) dx[i];
> uint32_t high = (uint32_t) (dx[i] >> 32);
>
> - printk( "D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low );
> + printk("D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low);
> }
> }
> #endif
> }
>
> -static void _ARM_Cortex_M_fault_info_print( void )
> +static void _ARM_Cortex_M_fault_info_print(void)
> {
> #if defined(ARM_MULTILIB_ARCH_V7M)
> /*
> * prints content of additional debugging registers
> * available on Cortex-Mx where x > 0 cores.
> */
> - uint32_t cfsr = _ARMV7M_SCB->cfsr;
> - uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET( cfsr );
> - uint8_t bfsr = ( ARMV7M_SCB_CFSR_BFSR_GET( cfsr ) >> 8 );
> - uint16_t ufsr = ( ARMV7M_SCB_CFSR_UFSR_GET( cfsr ) >> 16 );
> - uint32_t hfsr = _ARMV7M_SCB->hfsr;
> + uint32_t cfsr = _ARMV7M_SCB->cfsr;
> + uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET(cfsr);
> + uint8_t bfsr = (ARMV7M_SCB_CFSR_BFSR_GET(cfsr) >> 8);
> + uint16_t ufsr = (ARMV7M_SCB_CFSR_UFSR_GET(cfsr) >> 16);
> + uint32_t hfsr = _ARMV7M_SCB->hfsr;
> if ( mmfsr > 0 ) {
> - printk( "MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr );
> - if ( ( mmfsr & 0x1 ) != 0 ) {
> - printk( " IACCVIOL : 1 (instruction access violation)\n" );
> + printk("MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr);
> + if ( (mmfsr & 0x1) != 0 ) {
> + printk(" IACCVIOL : 1 (instruction access violation)\n");
> }
> - if ( ( mmfsr & 0x2 ) != 0 ) {
> - printk( " DACCVIOL : 1 (data access violation)\n" );
> + if ( (mmfsr & 0x2) != 0 ) {
> + printk(" DACCVIOL : 1 (data access violation)\n");
> }
> - if ( (mmfsr & 0x8 ) != 0 ) {
> - printk(
> - " MUNSTKERR : 1 (fault on unstacking on exception return)\n"
> - );
> + if ( (mmfsr & 0x8) != 0 ) {
> + printk(" MUNSTKERR : 1 (fault on unstacking on exception return)\n");
> }
> - if ( ( mmfsr & 0x10 ) != 0 ) {
> - printk( " MSTKERR : 1 (fault on stacking on exception entry)\n" );
> + if ( (mmfsr & 0x10) != 0 ) {
> + printk(" MSTKERR : 1 (fault on stacking on exception entry)\n");
> }
> - if ( (mmfsr & 0x20 ) != 0 ) {
> - printk( " MLSPERR : 1 (fault during lazy FP stack preservation)\n" );
> + if ( (mmfsr & 0x20) != 0 ) {
> + printk(" MLSPERR : 1 (fault during lazy FP stack preservation)\n");
> }
> - if ( (mmfsr & 0x80 ) != 0 ) {
> + if ( (mmfsr & 0x80) != 0 ) {
> printk(
> " MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
> - _ARMV7M_SCB->mmfar
> + _ARMV7M_SCB->mmfar
> );
> - }
> - else {
> - printk( " MMFARVALID : 0 (undetermined error address)\n" );
> + } else {
> + printk(" MMFARVALID : 0 (undetermined error address)\n");
> }
> }
> if ( bfsr > 0 ) {
> - printk( "BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr );
> - if ( ( bfsr & 0x1 ) != 0 ) {
> - printk( " IBUSERR : 1 (instruction fetch error)\n" );
> + printk("BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr);
> + if ( (bfsr & 0x1) != 0 ) {
> + printk(" IBUSERR : 1 (instruction fetch error)\n");
> }
> - if ( (bfsr & 0x2 ) != 0 ) {
> - printk(
> - " PRECISERR : 1 (data bus error with known exact location)\n"
> - );
> + if ( (bfsr & 0x2) != 0 ) {
> + printk(" PRECISERR : 1 (data bus error with known exact location)\n");
> }
> - if ( ( bfsr & 0x4) != 0 ) {
> - printk(
> - " IMPRECISERR: 1 (data bus error without known exact location)\n"
> + if ( (bfsr & 0x4) != 0 ) {
> + printk(" IMPRECISERR: 1 (data bus error without known exact location)\n"
> );
> }
> - if ( (bfsr & 0x8 ) != 0 ) {
> - printk(
> - " UNSTKERR : 1 (fault on unstacking on exception return)\n"
> - );
> + if ( (bfsr & 0x8) != 0 ) {
> + printk(" UNSTKERR : 1 (fault on unstacking on exception return)\n");
> }
> - if ( ( bfsr & 0x10 ) != 0 ) {
> - printk( " STKERR : 1 (fault on stacking on exception entry)\n" );
> + if ( (bfsr & 0x10) != 0 ) {
> + printk(" STKERR : 1 (fault on stacking on exception entry)\n");
> }
> - if ( ( bfsr & 0x20 ) != 0 ) {
> - printk( " LSPERR : 1 (fault during lazy FP stack preservation)\n" );
> + if ( (bfsr & 0x20) != 0 ) {
> + printk(" LSPERR : 1 (fault during lazy FP stack preservation)\n");
> }
> - if ( (bfsr & 0x80 ) != 0 ) {
> + if ( (bfsr & 0x80) != 0 ) {
> printk(
> " BFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
> - _ARMV7M_SCB->bfar
> + _ARMV7M_SCB->bfar
> );
> - }
> - else {
> - printk( " BFARVALID : 0 (undetermined error address)\n" );
> + } else {
> + printk(" BFARVALID : 0 (undetermined error address)\n");
> }
> }
> if ( ufsr > 0 ) {
> - printk( "UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);
> - if ( (ufsr & 0x1 ) != 0 ) {
> - printk( " UNDEFINSTR : 1 (undefined instruction issued)\n");
> + printk("UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);
> + if ( (ufsr & 0x1) != 0 ) {
> + printk(" UNDEFINSTR : 1 (undefined instruction issued)\n");
> }
> - if ( (ufsr & 0x2 ) != 0 ) {
> - printk(
> - " INVSTATE : 1"
> - " (invalid instruction state"
> - " (Thumb not set in EPSR or invalid IT state in EPSR))\n"
> - );
> + if ( (ufsr & 0x2) != 0 ) {
> + printk(" INVSTATE : 1"
> + " (invalid instruction state"
> + " (Thumb not set in EPSR or invalid IT state in EPSR))\n");
> }
> - if ( (ufsr & 0x4 ) != 0 ) {
> - printk( " INVPC : 1 (integrity check failure on EXC_RETURN)\n" );
> + if ( (ufsr & 0x4) != 0 ) {
> + printk(" INVPC : 1 (integrity check failure on EXC_RETURN)\n");
> }
> - if ( (ufsr & 0x8 ) != 0 ) {
> - printk(
> - " NOCP : 1"
> - " (coprocessor instruction issued"
> - " but coprocessor disabled or non existent)\n"
> - );
> + if ( (ufsr & 0x8) != 0 ) {
> + printk(" NOCP : 1"
> + " (coprocessor instruction issued"
> + " but coprocessor disabled or non existent)\n");
> }
> - if ( ( ufsr & 0x100) != 0 ) {
> - printk( " UNALIGNED : 1 (unaligned access operation occurred)\n" );
> + if ( (ufsr & 0x100) != 0 ) {
> + printk(" UNALIGNED : 1 (unaligned access operation occurred)\n");
> }
> - if ( ( ufsr & 0x200) != 0 ) {
> - printk( " DIVBYZERO : 1 (division by zero)" );
> + if ( (ufsr & 0x200) != 0 ) {
> + printk(" DIVBYZERO : 1 (division by zero)");
> }
> }
> - if ( (hfsr & (
> - ARMV7M_SCB_HFSR_VECTTBL_MASK
> - | ARMV7M_SCB_HFSR_DEBUGEVT_MASK
> - | ARMV7M_SCB_HFSR_FORCED_MASK
> - ) ) != 0 ) {
> - printk( "HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr );
> - if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK ) != 0 ) {
> - printk(
> - " VECTTBL : 1 (error in address located in vector table)\n"
> - );
> - }
> - if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK ) != 0 ) {
> - printk(
> - " FORCED : 1 (configurable fault escalated to hard fault)\n"
> + if ( (hfsr & (ARMV7M_SCB_HFSR_VECTTBL_MASK | ARMV7M_SCB_HFSR_DEBUGEVT_MASK |
> + ARMV7M_SCB_HFSR_FORCED_MASK)) != 0 ) {
> + printk("HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr);
> + if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK) != 0 ) {
> + printk(" VECTTBL : 1 (error in address located in vector table)\n");
> + }
> + if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK) != 0 ) {
> + printk(" FORCED : 1 (configurable fault escalated to hard fault)\n"
> );
> }
> - if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK ) != 0 ) {
> + if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK) != 0 ) {
> printk(
> " DEBUGEVT : 1 (debug event occurred with debug system disabled)\n"
> );
> @@ -206,7 +187,7 @@ static void _ARM_Cortex_M_fault_info_print( void )
> }
> #endif
> }
> -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
> +void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
> {
> printk(
> "\n"
> @@ -248,6 +229,6 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
> (intptr_t) frame->vector
> );
>
> - _ARM_VFP_context_print( frame->vfp_context );
> + _ARM_VFP_context_print(frame->vfp_context);
> _ARM_Cortex_M_fault_info_print();
> }
> diff --git a/cpukit/score/cpu/arm/armv4-sync-synchronize.c b/cpukit/score/cpu/arm/armv4-sync-synchronize.c
> index 2f454306d8..82b0a69566 100644
> --- a/cpukit/score/cpu/arm/armv4-sync-synchronize.c
> +++ b/cpukit/score/cpu/arm/armv4-sync-synchronize.c
> @@ -35,7 +35,7 @@
>
> #include <rtems/score/cpu.h>
>
> -void __sync_synchronize( void )
> +void __sync_synchronize(void)
> {
> _ARM_Data_memory_barrier();
> }
> diff --git a/cpukit/score/cpu/arm/armv7-thread-idle.c b/cpukit/score/cpu/arm/armv7-thread-idle.c
> index 720cb2be83..c4e8e66210 100644
> --- a/cpukit/score/cpu/arm/armv7-thread-idle.c
> +++ b/cpukit/score/cpu/arm/armv7-thread-idle.c
> @@ -40,8 +40,7 @@
>
> #include <rtems/score/cpu.h>
>
> -
> -void *_CPU_Thread_Idle_body( uintptr_t ignored )
> +void *_CPU_Thread_Idle_body(uintptr_t ignored)
> {
> while ( true ) {
> #ifdef ARM_MULTILIB_HAS_WFI
> @@ -49,4 +48,3 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
> #endif /* ARM_MULTILIB_HAS_WFI */
> }
> }
> -
> diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
> index d67bcf93b5..b0cfbccef2 100644
> --- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
> +++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
> @@ -48,12 +48,12 @@
>
> void _CPU_Context_Initialize(
> Context_Control *context,
> - void *stack_area_begin,
> - size_t stack_area_size,
> - uint32_t new_level,
> - void (*entry_point)( void ),
> - bool is_fp,
> - void *tls_area
> + void *stack_area_begin,
> + size_t stack_area_size,
> + uint32_t new_level,
> + void (*entry_point)(void),
> + bool is_fp,
> + void *tls_area
> )
> {
> char *stack_area_end = (char *) stack_area_begin + stack_area_size;
> @@ -64,7 +64,7 @@ void _CPU_Context_Initialize(
> context->register_sp = stack_area_end;
>
> if ( tls_area != NULL ) {
> - context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
> + context->thread_id = (uint32_t) _TLS_Initialize_area(tls_area);
> }
> }
>
> diff --git a/cpukit/score/cpu/arm/armv7m-context-restore.c b/cpukit/score/cpu/arm/armv7m-context-restore.c
> index b888abe29f..625a33c626 100644
> --- a/cpukit/score/cpu/arm/armv7m-context-restore.c
> +++ b/cpukit/score/cpu/arm/armv7m-context-restore.c
> @@ -43,9 +43,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void __attribute__((naked)) _CPU_Context_restore(
> - Context_Control *heir
> -)
> +void __attribute__((naked)) _CPU_Context_restore(Context_Control *heir)
> {
> __asm__ volatile (
> "movw r2, #:lower16:_Per_CPU_Information\n"
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c
> index 35dde50dc3..6d3eb49ea0 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-default.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-default.c
> @@ -42,21 +42,21 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void __attribute__((naked)) _ARMV7M_Exception_default( void )
> +void __attribute__((naked)) _ARMV7M_Exception_default(void)
> {
> - /* On exception entry, ARMv7M saves context state onto a stack pointed to
> - * by either MSP or PSP. The value stored in LR indicates whether we were
> - * in Thread or Handler mode, whether we were using the FPU (if any),
> - * and which stack pointer we were using.
> - * In particular, bit 2 of LR will be 0 if we were using MSP.
> - *
> - * For a more detailed explanation, see the Exception Entry Behavior
> - * section of the ARMv7M Architecture Reference Manual.
> - */
> + /* On exception entry, ARMv7M saves context state onto a stack pointed to
> + * by either MSP or PSP. The value stored in LR indicates whether we were
> + * in Thread or Handler mode, whether we were using the FPU (if any),
> + * and which stack pointer we were using.
> + * In particular, bit 2 of LR will be 0 if we were using MSP.
> + *
> + * For a more detailed explanation, see the Exception Entry Behavior
> + * section of the ARMv7M Architecture Reference Manual.
> + */
>
> - /* As we're in Handler mode here, we'll always operate on MSP.
> - * However, we need to store the right SP in our CPU_Exception_frame.
> - */
> + /* As we're in Handler mode here, we'll always operate on MSP.
> + * However, we need to store the right SP in our CPU_Exception_frame.
> + */
> __asm__ volatile (
> "sub sp, %[cpufsz]\n" /* Allocate space for a CPU_Exception_frame. */
> "stm sp, {r0-r12}\n"
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
> index 41effd1e18..c26d783723 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
> @@ -43,9 +43,9 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index )
> +ARMV7M_Exception_handler _ARMV7M_Get_exception_handler(int index)
> {
> - return _ARMV7M_SCB->vtor [index];
> + return _ARMV7M_SCB->vtor[index];
> }
>
> #endif /* ARM_MULTILIB_ARCH_V7M */
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
> index 94c9dc5360..9dd81a5df7 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
> @@ -38,25 +38,22 @@
> #include "config.h"
> #endif
>
> -#include <rtems/score/armv7m.h>
> #include <rtems/rtems/cache.h>
> +#include <rtems/score/armv7m.h>
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void _ARMV7M_Set_exception_handler(
> - int index,
> - ARMV7M_Exception_handler handler
> -)
> +void _ARMV7M_Set_exception_handler(int index, ARMV7M_Exception_handler handler)
> {
> - if ( _ARMV7M_SCB->vtor [index] != handler ) {
> - _ARMV7M_SCB->vtor [index] = handler;
> + if ( _ARMV7M_SCB->vtor[index] != handler ) {
> + _ARMV7M_SCB->vtor[index] = handler;
> rtems_cache_flush_multiple_data_lines(
> - &_ARMV7M_SCB->vtor [index],
> - sizeof(_ARMV7M_SCB->vtor [index])
> + &_ARMV7M_SCB->vtor[index],
> + sizeof(_ARMV7M_SCB->vtor[index])
> );
> rtems_cache_invalidate_multiple_instruction_lines(
> - &_ARMV7M_SCB->vtor [index],
> - sizeof(_ARMV7M_SCB->vtor [index])
> + &_ARMV7M_SCB->vtor[index],
> + sizeof(_ARMV7M_SCB->vtor[index])
> );
> }
> }
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
> index bb0892a32f..fdcc2f0f68 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
> @@ -42,12 +42,12 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -int _ARMV7M_Get_exception_priority( int vector )
> +int _ARMV7M_Get_exception_priority(int vector)
> {
> - if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
> - return _ARMV7M_NVIC_Get_priority( ARMV7M_IRQ_OF_VECTOR( vector ) );
> + if ( _ARMV7M_Is_vector_an_irq(vector) ) {
> + return _ARMV7M_NVIC_Get_priority(ARMV7M_IRQ_OF_VECTOR(vector));
> } else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {
> - return _ARMV7M_SCB->shpr [vector - 4];
> + return _ARMV7M_SCB->shpr[vector - 4];
> } else {
> return vector - 4;
> }
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
> index b94366e07c..7f868fed79 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
> @@ -43,13 +43,13 @@
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> void _ARMV7M_Set_exception_priority_and_handler(
> - int index,
> - int priority,
> + int index,
> + int priority,
> ARMV7M_Exception_handler handler
> )
> {
> - _ARMV7M_Set_exception_priority( index, priority );
> - _ARMV7M_Set_exception_handler( index, handler );
> + _ARMV7M_Set_exception_priority(index, priority);
> + _ARMV7M_Set_exception_handler(index, handler);
> }
>
> #endif /* ARM_MULTILIB_ARCH_V7M */
> diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
> index 05136a47db..0cd7a4f28a 100644
> --- a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
> +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
> @@ -42,12 +42,12 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void _ARMV7M_Set_exception_priority( int vector, int priority )
> +void _ARMV7M_Set_exception_priority(int vector, int priority)
> {
> - if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
> - _ARMV7M_NVIC_Set_priority( ARMV7M_IRQ_OF_VECTOR( vector ), priority );
> + if ( _ARMV7M_Is_vector_an_irq(vector) ) {
> + _ARMV7M_NVIC_Set_priority(ARMV7M_IRQ_OF_VECTOR(vector), priority);
> } else if ( vector >= ARMV7M_VECTOR_MEM_MANAGE ) {
> - _ARMV7M_SCB->shpr [vector - 4] = (uint8_t) priority;
> + _ARMV7M_SCB->shpr[vector - 4] = (uint8_t) priority;
> }
> }
>
> diff --git a/cpukit/score/cpu/arm/armv7m-initialize.c b/cpukit/score/cpu/arm/armv7m-initialize.c
> index 0f47b49af7..1c9a66523b 100644
> --- a/cpukit/score/cpu/arm/armv7m-initialize.c
> +++ b/cpukit/score/cpu/arm/armv7m-initialize.c
> @@ -42,7 +42,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void _CPU_Initialize( void )
> +void _CPU_Initialize(void)
> {
> /*
> * The exception handler used to carry out the thead dispatching must have
> diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
> index ea168969ba..dfc125d545 100644
> --- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
> +++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
> @@ -43,7 +43,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
> +static void __attribute__((naked)) _ARMV7M_Thread_dispatch(void)
> {
> __asm__ volatile (
> "bl _Thread_Dispatch\n"
> @@ -53,7 +53,7 @@ static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
> );
> }
>
> -static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
> +static void _ARMV7M_Trigger_lazy_floating_point_context_save(void)
> {
> #ifdef ARM_MULTILIB_VFP
> __asm__ volatile (
> @@ -62,7 +62,7 @@ static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
> #endif
> }
>
> -void _ARMV7M_Pendable_service_call( void )
> +void _ARMV7M_Pendable_service_call(void)
> {
> Per_CPU_Control *cpu_self = _Per_CPU_Get();
>
> @@ -73,7 +73,7 @@ void _ARMV7M_Pendable_service_call( void )
> * this interrupt service may be delayed until interrupts are enable again.
> */
> if (
> - ( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0
> + (cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level) == 0
> ) {
> ARMV7M_Exception_frame *ef;
>
> @@ -84,29 +84,29 @@ void _ARMV7M_Pendable_service_call( void )
>
> ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
> --ef;
> - _ARMV7M_Set_PSP( (uint32_t) ef );
> + _ARMV7M_Set_PSP((uint32_t) ef);
>
> /*
> * According to "ARMv7-M Architecture Reference Manual" section B1.5.6
> * "Exception entry behavior" the return address is half-word aligned.
> */
> - ef->register_pc = (void *)
> - ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
> + ef->register_pc = (void *) ((uintptr_t) _ARMV7M_Thread_dispatch &
> + ~((uintptr_t) 1));
>
> ef->register_xpsr = 0x01000000U;
> }
> }
>
> -void _ARMV7M_Supervisor_call( void )
> +void _ARMV7M_Supervisor_call(void)
> {
> - Per_CPU_Control *cpu_self = _Per_CPU_Get();
> + Per_CPU_Control *cpu_self = _Per_CPU_Get();
> ARMV7M_Exception_frame *ef;
>
> _ARMV7M_Trigger_lazy_floating_point_context_save();
>
> ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
> ++ef;
> - _ARMV7M_Set_PSP( (uint32_t) ef );
> + _ARMV7M_Set_PSP((uint32_t) ef);
>
> cpu_self->isr_nest_level = 0;
>
> diff --git a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
> index 1490f6e219..04f7ab1749 100644
> --- a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
> +++ b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
> @@ -44,7 +44,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void _ARMV7M_Interrupt_service_enter( void )
> +void _ARMV7M_Interrupt_service_enter(void)
> {
> Per_CPU_Control *cpu_self = _Per_CPU_Get();
>
> @@ -52,7 +52,7 @@ void _ARMV7M_Interrupt_service_enter( void )
> ++cpu_self->isr_nest_level;
> }
>
> -void _ARMV7M_Interrupt_service_leave( void )
> +void _ARMV7M_Interrupt_service_leave(void)
> {
> Per_CPU_Control *cpu_self = _Per_CPU_Get();
>
> diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-get.c b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
> index cc2b674e13..48b11d923a 100644
> --- a/cpukit/score/cpu/arm/armv7m-isr-level-get.c
> +++ b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
> @@ -41,7 +41,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -uint32_t _CPU_ISR_Get_level( void )
> +uint32_t _CPU_ISR_Get_level(void)
> {
> return _ARMV7M_Get_basepri() != 0;
> }
> diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-set.c b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
> index 72c9684025..982c5df687 100644
> --- a/cpukit/score/cpu/arm/armv7m-isr-level-set.c
> +++ b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
> @@ -41,9 +41,9 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void _CPU_ISR_Set_level( uint32_t level )
> +void _CPU_ISR_Set_level(uint32_t level)
> {
> - _ARMV7M_Set_basepri( 0 );
> + _ARMV7M_Set_basepri(0);
> }
>
> #endif /* ARM_MULTILIB_ARCH_V7M */
> diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
> index c1e9eb70cb..a9e14ba1e6 100644
> --- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
> +++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
> @@ -51,12 +51,12 @@ void _CPU_ISR_install_vector(
> {
> uint32_t level;
>
> - _ISR_Local_disable( level );
> + _ISR_Local_disable(level);
> if ( old_handler != NULL ) {
> - *old_handler = _ARMV7M_Get_exception_handler( (int) vector );
> + *old_handler = _ARMV7M_Get_exception_handler((int) vector);
> }
> - _ARMV7M_Set_exception_handler( (int) vector, new_handler );
> - _ISR_Local_enable( level );
> + _ARMV7M_Set_exception_handler((int) vector, new_handler);
> + _ISR_Local_enable(level);
> }
>
> #endif /* ARM_MULTILIB_ARCH_V7M */
> diff --git a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
> index a9b59dec84..4c6d969f4f 100644
> --- a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
> +++ b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
> @@ -42,9 +42,7 @@
>
> #ifdef ARM_MULTILIB_ARCH_V7M
>
> -void __attribute__((naked)) _ARMV7M_Start_multitasking(
> - Context_Control *heir
> -)
> +void __attribute__((naked)) _ARMV7M_Start_multitasking(Context_Control *heir)
> {
> __asm__ volatile (
> /* Restore heir context */
> diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
> index 65f1ad2014..c7d7527dce 100644
> --- a/cpukit/score/cpu/arm/cpu.c
> +++ b/cpukit/score/cpu/arm/cpu.c
> @@ -61,8 +61,7 @@
> #endif
>
> RTEMS_STATIC_ASSERT(
> - offsetof( Context_Control, thread_id )
> - == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
> + offsetof(Context_Control, thread_id) == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
> ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
> );
>
> @@ -83,23 +82,23 @@ RTEMS_STATIC_ASSERT(
> #endif
>
> RTEMS_STATIC_ASSERT(
> - sizeof( CPU_Exception_frame ) == ARM_EXCEPTION_FRAME_SIZE,
> + sizeof(CPU_Exception_frame) == ARM_EXCEPTION_FRAME_SIZE,
> ARM_EXCEPTION_FRAME_SIZE
> );
>
> RTEMS_STATIC_ASSERT(
> - sizeof( CPU_Exception_frame ) % CPU_STACK_ALIGNMENT == 0,
> + sizeof(CPU_Exception_frame) % CPU_STACK_ALIGNMENT == 0,
> CPU_Exception_frame_alignment
> );
>
> RTEMS_STATIC_ASSERT(
> - offsetof( CPU_Exception_frame, register_sp )
> - == ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET,
> + offsetof(CPU_Exception_frame, register_sp) ==
> + ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET,
> ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET
> );
>
> RTEMS_STATIC_ASSERT(
> - sizeof( ARM_VFP_context ) == ARM_VFP_CONTEXT_SIZE,
> + sizeof(ARM_VFP_context) == ARM_VFP_CONTEXT_SIZE,
> ARM_VFP_CONTEXT_SIZE
> );
>
> @@ -107,12 +106,12 @@ RTEMS_STATIC_ASSERT(
>
> void _CPU_Context_Initialize(
> Context_Control *the_context,
> - void *stack_area_begin,
> - size_t stack_area_size,
> - uint32_t new_level,
> - void (*entry_point)( void ),
> - bool is_fp,
> - void *tls_area
> + void *stack_area_begin,
> + size_t stack_area_size,
> + uint32_t new_level,
> + void (*entry_point)(void),
> + bool is_fp,
> + void *tls_area
> )
> {
> (void) new_level;
> @@ -120,14 +119,14 @@ void _CPU_Context_Initialize(
> the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
> the_context->register_lr = (uint32_t) entry_point;
> the_context->isr_dispatch_disable = 0;
> - the_context->thread_id = (uint32_t) tls_area;
> + the_context->thread_id = (uint32_t) tls_area;
>
> if ( tls_area != NULL ) {
> - the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
> + the_context->thread_id = (uint32_t) _TLS_Initialize_area(tls_area);
> }
> }
>
> -void _CPU_ISR_Set_level( uint32_t level )
> +void _CPU_ISR_Set_level(uint32_t level)
> {
> uint32_t arm_switch_reg;
>
> @@ -144,7 +143,7 @@ void _CPU_ISR_Set_level( uint32_t level )
> );
> }
>
> -uint32_t _CPU_ISR_Get_level( void )
> +uint32_t _CPU_ISR_Get_level(void)
> {
> ARM_SWITCH_REGISTERS;
> uint32_t level;
> @@ -157,7 +156,7 @@ uint32_t _CPU_ISR_Get_level( void )
> : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
> );
>
> - return ( level & ARM_PSR_I ) != 0;
> + return (level & ARM_PSR_I) != 0;
> }
>
> void _CPU_ISR_install_vector(
> @@ -169,34 +168,34 @@ void _CPU_ISR_install_vector(
> #pragma GCC diagnostic push
> #pragma GCC diagnostic ignored "-Warray-bounds"
> /* Redirection table starts at the end of the vector table */
> - CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
> + CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
>
> - CPU_ISR_handler current_handler = table [vector];
> + CPU_ISR_handler current_handler = table[vector];
>
> /* The current handler is now the old one */
> - if (old_handler != NULL) {
> + if ( old_handler != NULL ) {
> *old_handler = current_handler;
> }
>
> /* Write only if necessary to avoid writes to a maybe read-only memory */
> - if (current_handler != new_handler) {
> - table [vector] = new_handler;
> + if ( current_handler != new_handler ) {
> + table[vector] = new_handler;
> }
> #pragma GCC diagnostic pop
> }
>
> -void _CPU_Initialize( void )
> +void _CPU_Initialize(void)
> {
> /* Do nothing */
> }
>
> #endif /* ARM_MULTILIB_ARCH_V4 */
>
> -void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
> +void _CPU_Fatal_halt(uint32_t source, CPU_Uint32ptr error)
> {
> ISR_Level level;
>
> - _CPU_ISR_Disable( level );
> + _CPU_ISR_Disable(level);
> (void) level;
>
> __asm__ volatile ("mov r0, %0\n"
> --
> 2.34.1
>
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