Possible minor bug in ARM A startup code. Clearing res1 instead of I bit in SCTLR.

[Philip Kirkpatrick]

While I was cleaning up the ZynqMP RPU port for a revised patch (should be
ready in a few hours) I noticed a possible minor bug in
`bsps/arm/shared/start/start.S` affecting ARM A profile parts.  Someone
familiar with ARM A parts, please check this.  Also for my own knowledge,
why is this done with 2 bic instructions instead of one?

Reference A53 TRM SCTLR register:
https://developer.arm.com/documentation/ddi0500/e/BABJAHDA

At line 401:
---
#if (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8
/*
* Set VBAR to the vector table in the start section and make sure
* SCTLR[M, I, A, C, V] are cleared.  Afterwards, exceptions are
* handled by RTEMS.
*/
ldr r0, =bsp_start_vector_table_begin
dsb
mcr p15, 0, r0, c12, c0, 0
mrc p15, 0, r0, c1, c0, 0
---
// Is 0x2800, clear V[13] and res1[11]
// Should be 0x3000, clear V[13] and I[12]
---
bic r1, r0, #0x2800
bic r1, r1, #0x7              // Clear C[2] A[1] and M[0] (this is fine)
mcr p15, 0, r1, c1, c0, 0
isb
---

-Phil
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