[PATCH rtems-libbsd 2/3] freebsd/cgem: Read clock frequency from device tree
Padmarao.Begari at microchip.com
Padmarao.Begari at microchip.com
Thu Mar 2 05:32:58 UTC 2023
Hi will,
> On Wed, 2023-03-01 at 08:20 -0600, Will wrote:
>
> On Tue, Feb 28, 2023 at 11:57 PM Padmarao Begari <
> padmarao.begari at microchip.com> wrote:
> > Read the clock frequency from the device tree and use it to
> > calculate the mdc clock divider for the MII bus if not found
> > then use default clock divider.
> > ---
> > freebsd/sys/dev/cadence/if_cgem.c | 39
> > ++++++++++++++++++++++++++++---
> > 1 file changed, 36 insertions(+), 3 deletions(-)
> >
> > diff --git a/freebsd/sys/dev/cadence/if_cgem.c
> > b/freebsd/sys/dev/cadence/if_cgem.c
> > index 2888a085..363a9717 100644
> > --- a/freebsd/sys/dev/cadence/if_cgem.c
> > +++ b/freebsd/sys/dev/cadence/if_cgem.c
> > @@ -135,6 +135,7 @@ struct cgem_softc {
> > uint32_t net_cfg_shadow;
> > int neednullqs;
> > int phy_contype;
> > + uint32_t pclk_rate;
> > #endif /* __rtems__ */
> > int ref_clk_num;
> > #ifndef __rtems__
> > @@ -1238,6 +1239,27 @@ cgem_get_phyaddr(phandle_t node, int
> > *phy_addr)
> > return (0);
> > }
> >
> > +static uint32_t cgem_mdc_clk_div(struct cgem_softc *sc)
> > +{
> > + uint32_t config;
> > + uint32_t pclk_hz = sc->pclk_rate;
> > +
> > + if (pclk_hz <= 20000000)
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_8;
> > + else if (pclk_hz <= 40000000)
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_16;
> > + else if (pclk_hz <= 80000000)
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_32;
> > + else if (pclk_hz <= 120000000)
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_48;
> > + else if (pclk_hz <= 160000000)
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_64;
> > + else
> > + config = CGEM_NET_CFG_MDC_CLK_DIV_96;
> > +
> > + return config;
> > +}
> > +
> >
>
> Enclose this in a #ifdef __rtems__ guard. I think the suggested style
> is to always use braces {} with if/else, even if it's a single line.
>
Ok, will update
Regards
Padmarao
> > /* Reset hardware. */
> > static void
> > cgem_reset(struct cgem_softc *sc)
> > @@ -1279,12 +1301,16 @@ cgem_reset(struct cgem_softc *sc)
> > sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_32;
> > }
> >
> > + if (sc->pclk_rate != 0) {
> > + sc->net_cfg_shadow |= cgem_mdc_clk_div(sc);
> > + } else {
> > #ifdef CGEM64
> > - sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_48;
> > + sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_48;
> > #else
> > - sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_64;
> > + sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_64;
> > #endif
> > - WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
> > + WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
> > + }
> > #endif /* __rtems__ */
> >
> > sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN;
> > @@ -2038,6 +2064,13 @@ cgem_attach(device_t dev)
> > #endif /* __rtems__ */
> > /* Get reference clock number and base divider from fdt. */
> > node = ofw_bus_get_node(dev);
> > +#ifdef __rtems__
> > + if (OF_getencprop(node, "clock-frequency", &cell,
> > sizeof(cell)) > 0)
> > + sc->pclk_rate = cell;
> > + else
> > + sc->pclk_rate = 0;
> > +#endif /* __rtems__ */
> > +
> > sc->ref_clk_num = 0;
> > if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell))
> > > 0)
> > sc->ref_clk_num = fdt32_to_cpu(cell);
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