[PATCH] score/arm: make MPU setup more generic

[Karel Gardas]

This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting PRIVDEFENA attribute
to control register. Compatibility with previous behavior and API
is preserved.

Sponsored-By:	Precidata
---
 cpukit/score/cpu/arm/include/rtems/score/armv7m.h | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
index 744dca26d3..cfd676cce7 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
@@ -701,7 +701,8 @@ static inline void _ARMV7M_MPU_Disable_region(
   mpu->rasr = 0;
 }
 
-static inline void _ARMV7M_MPU_Setup(
+static inline void _ARMV7M_MPU_Setup_with_ctrl(
+  uint32_t ctrl,
   const ARMV7M_MPU_Region_config *cfg,
   size_t cfg_count
 )
@@ -737,13 +738,21 @@ static inline void _ARMV7M_MPU_Setup(
     _ARMV7M_MPU_Disable_region(mpu, region);
   }
 
-  mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA;
+  mpu->ctrl = ctrl;
   scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA;
 
   _ARM_Data_synchronization_barrier();
   _ARM_Instruction_synchronization_barrier();
 }
 
+static inline void _ARMV7M_MPU_Setup(
+  const ARMV7M_MPU_Region_config *cfg,
+  size_t cfg_count
+)
+{
+  _ARMV7M_MPU_Setup_with_ctrl(ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA, cfg, cfg_count);
+}
+
 #endif /* ASM */
 
 #endif /* ARM_MULTILIB_ARCH_V7M */
-- 
2.25.1