[PATCH 24/34] bsp/leon3: Add LEON3_L2CACHE_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/start/cache.c                | 36 ++++++++++++++-----
 spec/build/bsps/sparc/leon3/grp.yml           |  2 ++
 .../build/bsps/sparc/leon3/optl2cachebase.yml | 19 ++++++++++
 3 files changed, 49 insertions(+), 8 deletions(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optl2cachebase.yml

diff --git a/bsps/sparc/leon3/start/cache.c b/bsps/sparc/leon3/start/cache.c
index ed6fb5733d..5049b7f81c 100644
--- a/bsps/sparc/leon3/start/cache.c
+++ b/bsps/sparc/leon3/start/cache.c
@@ -11,7 +11,13 @@
 
 #include <bsp/leon3.h>
 
+#if !defined(LEON3_L2CACHE_BASE)
 #include <grlib/ambapp.h>
+#endif
+
+#if !defined(LEON3_L2CACHE_BASE) || LEON3_L2CACHE_BASE != 0
+#define LEON3_MAYBE_HAS_L2CACHE
+#endif
 
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
@@ -23,6 +29,7 @@
 
 #define CPU_DATA_CACHE_ALIGNMENT 64
 
+#if !defined(LEON3_L2CACHE_BASE)
 static inline l2cache *get_l2c_regs(void)
 {
   struct ambapp_dev *adev;
@@ -42,7 +49,17 @@ static inline l2cache *get_l2c_regs(void)
 
   return (l2cache *) DEV_TO_AHB(adev)->start[1];
 }
+#endif
+
+static inline size_t get_l1_size(uint32_t l1_cfg)
+{
+  uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1;
+  uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10);
+
+  return ways * wsize;
+}
 
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
 static inline size_t get_l2_size(void)
 {
   l2cache *regs;
@@ -50,11 +67,15 @@ static inline size_t get_l2_size(void)
   unsigned ways;
   unsigned set_size;
 
+#if defined(LEON3_L2CACHE_BASE)
+  regs = (l2cache *) LEON3_L2CACHE_BASE;
+#else
   regs = get_l2c_regs();
 
   if (regs == NULL) {
     return 0;
   }
+#endif
 
   status = grlib_load_32(&regs->l2cs);
   ways = L2CACHE_L2CS_WAY_GET(status) + 1;
@@ -63,18 +84,11 @@ static inline size_t get_l2_size(void)
   return ways * set_size;
 }
 
-static inline size_t get_l1_size(uint32_t l1_cfg)
-{
-  uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1;
-  uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10);
-
-  return ways * wsize;
-}
-
 static inline size_t get_max_size(size_t a, size_t b)
 {
   return a < b ? b : a;
 }
+#endif
 
 static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg)
 {
@@ -82,14 +96,20 @@ static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg)
 
   switch (level) {
     case 0:
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
       size = get_max_size(get_l1_size(l1_cfg), get_l2_size());
+#else
+      size = get_l1_size(l1_cfg);
+#endif
       break;
     case 1:
       size = get_l1_size(l1_cfg);
       break;
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
     case 2:
       size = get_l2_size();
       break;
+#endif
     default:
       size = 0;
       break;
diff --git a/spec/build/bsps/sparc/leon3/grp.yml b/spec/build/bsps/sparc/leon3/grp.yml
index d044a6ca60..6d7a1b75c3 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -44,6 +44,8 @@ links:
   uid: optirqampts
 - role: build-dependency
   uid: optconirq
+- role: build-dependency
+  uid: optl2cachebase
 - role: build-dependency
   uid: optleon3smp
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optl2cachebase.yml b/spec/build/bsps/sparc/leon3/optl2cachebase.yml
new file mode 100644
index 0000000000..759198f827
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optl2cachebase.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+  value: 0x00000000
+- enabled-by: sparc/gr740
+  value: 0xf0000000
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: LEON3_L2CACHE_BASE
+description: |
+  This option defines the base address of the L2CACHE register block.
+type: build
-- 
2.35.3