Add Formal Verification chapter v4
Sebastian Huber
sebastian.huber at embedded-brains.de
Thu Sep 21 15:35:54 UTC 2023
On 21.09.23 17:28, Gedare Bloom wrote:
> I've taken a look and resolved / commented. We can leave some of the
> `sis` specific bits, with the understanding that hopefully the
> simulation target can be made more generic in the future. This could be
> a potential GSoC project for Prequalification to hook it up to
> `rtems-tools.git/tester` to make use of the capabilities we already have
> for running simulators.
The model based tests are not target-specific. You could run them with
any (simulator) BSP.
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