[PATCH] bsps/aarch64/cache: Clean up unused fuctions

Kinsey Moore kinsey.moore at oarcorp.com
Tue Jan 2 22:02:17 UTC 2024


When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added
to AArch64 cache management, it obsoleted the *_1_data/instruction_line
functions. These have been removed since they are no longer referenced.
The AArch64_instruction_cache_inner_shareable_invalidate_all function is
only used when RTEMS_SMP is defined, so only define it in that
circumstance.
---
 bsps/aarch64/shared/cache/cache.c | 29 ++---------------------------
 1 file changed, 2 insertions(+), 27 deletions(-)

diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c
index d6e0930038..be459d5083 100644
--- a/bsps/aarch64/shared/cache/cache.c
+++ b/bsps/aarch64/shared/cache/cache.c
@@ -63,15 +63,6 @@ void AArch64_data_cache_clean_and_invalidate_line(const void *d_addr)
   );
 }
 
-static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
-{
-  /* Flush the Data cache */
-  AArch64_data_cache_clean_and_invalidate_line( d_addr );
-
-  /* Wait for L1 flush to complete */
-  _AARCH64_Data_synchronization_barrier();
-}
-
 static inline void
 _CPU_cache_flush_data_range(
   const void *d_addr,
@@ -105,15 +96,6 @@ static inline void AArch64_data_cache_invalidate_line(const void *d_addr)
   );
 }
 
-static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
-{
-  /* Invalidate the data cache line */
-  AArch64_data_cache_invalidate_line( d_addr );
-
-  /* Wait for L1 invalidate to complete */
-  _AARCH64_Data_synchronization_barrier();
-}
-
 static inline void
 _CPU_cache_invalidate_data_range(
   const void *d_addr,
@@ -152,15 +134,6 @@ static inline void AArch64_instruction_cache_invalidate_line(const void *i_addr)
   __builtin___clear_cache((void *)i_addr, ((char *)i_addr) + sizeof(void*) - 1);
 }
 
-static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
-{
-  /* Invalidate the Instruction cache line */
-  AArch64_instruction_cache_invalidate_line( d_addr );
-
-  /* Wait for L1 invalidate to complete */
-  _AARCH64_Data_synchronization_barrier();
-}
-
 static inline void
 _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
 {
@@ -376,6 +349,7 @@ static inline void _CPU_cache_disable_data(void)
   rtems_interrupt_local_enable(level);
 }
 
+#ifdef RTEMS_SMP
 static inline
 void AArch64_instruction_cache_inner_shareable_invalidate_all(void)
 {
@@ -386,6 +360,7 @@ void AArch64_instruction_cache_inner_shareable_invalidate_all(void)
     : "memory"
   );
 }
+#endif /* RTEMS_SMP */
 
 static inline void AArch64_instruction_cache_invalidate(void)
 {
-- 
2.39.2



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