[PATCH 2/7] Duplicated csb740 directory to beagleboneblack directory for BBB port
Jarielle Catbagan
jcatbagan93 at gmail.com
Fri Jun 19 21:33:15 UTC 2015
---
ports/beagleboneblack/.vimrc | 13 +
ports/beagleboneblack/CSB740_boot.ldt | 63 +
ports/beagleboneblack/CSB740_ramtst.ldt | 59 +
ports/beagleboneblack/Makefile | 129 ++
ports/beagleboneblack/_vimrc | 13 +
ports/beagleboneblack/ad7843.c | 334 +++
ports/beagleboneblack/ad7843.h | 35 +
ports/beagleboneblack/ads7846.c | 180 ++
ports/beagleboneblack/ads7846.h | 56 +
ports/beagleboneblack/bashrc | 12 +
ports/beagleboneblack/bdi2000.cfg | 188 ++
ports/beagleboneblack/config.h | 202 ++
ports/beagleboneblack/cpu.h | 25 +
ports/beagleboneblack/cpu_gpio.h | 113 +
ports/beagleboneblack/cpu_i2c.c | 322 +++
ports/beagleboneblack/cpu_i2c.h | 269 +++
ports/beagleboneblack/cpuio.c | 313 +++
ports/beagleboneblack/cpuio.h | 76 +
ports/beagleboneblack/etherdev.c | 241 ++
ports/beagleboneblack/fbidemo | 163 ++
ports/beagleboneblack/font8x16.h | 3679 +++++++++++++++++++++++++++++++
ports/beagleboneblack/gdbregs.c | 1 +
ports/beagleboneblack/lcd_lut.h | 289 +++
ports/beagleboneblack/nand740.c | 333 +++
ports/beagleboneblack/omap3530.h | 497 +++++
ports/beagleboneblack/omap3530_gpio.c | 329 +++
ports/beagleboneblack/omap3530_iomux.c | 530 +++++
ports/beagleboneblack/omap3530_iomux.h | 1077 +++++++++
ports/beagleboneblack/omap3530_lcd.c | 342 +++
ports/beagleboneblack/omap3530_lcd.h | 75 +
ports/beagleboneblack/omap3530_mem.h | 184 ++
ports/beagleboneblack/omap3530_sdmmc.c | 505 +++++
ports/beagleboneblack/ram_reset.S | 211 ++
ports/beagleboneblack/regnames.c | 1 +
ports/beagleboneblack/rom_reset.S | 418 ++++
ports/beagleboneblack/target_version.h | 17 +
ports/beagleboneblack/tfsdev.h | 31 +
ports/beagleboneblack/xcmddcl.h | 34 +
ports/beagleboneblack/xcmdtbl.h | 19 +
39 files changed, 11378 insertions(+)
create mode 100755 ports/beagleboneblack/.vimrc
create mode 100644 ports/beagleboneblack/CSB740_boot.ldt
create mode 100644 ports/beagleboneblack/CSB740_ramtst.ldt
create mode 100644 ports/beagleboneblack/Makefile
create mode 100644 ports/beagleboneblack/_vimrc
create mode 100644 ports/beagleboneblack/ad7843.c
create mode 100644 ports/beagleboneblack/ad7843.h
create mode 100644 ports/beagleboneblack/ads7846.c
create mode 100644 ports/beagleboneblack/ads7846.h
create mode 100644 ports/beagleboneblack/bashrc
create mode 100644 ports/beagleboneblack/bdi2000.cfg
create mode 100644 ports/beagleboneblack/config.h
create mode 100644 ports/beagleboneblack/cpu.h
create mode 100644 ports/beagleboneblack/cpu_gpio.h
create mode 100644 ports/beagleboneblack/cpu_i2c.c
create mode 100644 ports/beagleboneblack/cpu_i2c.h
create mode 100644 ports/beagleboneblack/cpuio.c
create mode 100644 ports/beagleboneblack/cpuio.h
create mode 100644 ports/beagleboneblack/etherdev.c
create mode 100644 ports/beagleboneblack/fbidemo
create mode 100644 ports/beagleboneblack/font8x16.h
create mode 100644 ports/beagleboneblack/gdbregs.c
create mode 100644 ports/beagleboneblack/lcd_lut.h
create mode 100644 ports/beagleboneblack/nand740.c
create mode 100644 ports/beagleboneblack/omap3530.h
create mode 100644 ports/beagleboneblack/omap3530_gpio.c
create mode 100644 ports/beagleboneblack/omap3530_iomux.c
create mode 100644 ports/beagleboneblack/omap3530_iomux.h
create mode 100644 ports/beagleboneblack/omap3530_lcd.c
create mode 100644 ports/beagleboneblack/omap3530_lcd.h
create mode 100644 ports/beagleboneblack/omap3530_mem.h
create mode 100644 ports/beagleboneblack/omap3530_sdmmc.c
create mode 100644 ports/beagleboneblack/ram_reset.S
create mode 100644 ports/beagleboneblack/regnames.c
create mode 100644 ports/beagleboneblack/rom_reset.S
create mode 100644 ports/beagleboneblack/target_version.h
create mode 100644 ports/beagleboneblack/tfsdev.h
create mode 100644 ports/beagleboneblack/xcmddcl.h
create mode 100644 ports/beagleboneblack/xcmdtbl.h
diff --git a/ports/beagleboneblack/.vimrc b/ports/beagleboneblack/.vimrc
new file mode 100755
index 0000000..2a127e5
--- /dev/null
+++ b/ports/beagleboneblack/.vimrc
@@ -0,0 +1,13 @@
+" Very basic VIM startup file
+"
+" Set tab stop to 4 characters:
+set ts=4
+
+" Turn off syntax-sensitive coloring:
+" syntax off
+
+" Enable C-style indentation:
+" set cindent
+
+" Disable the highlighting of search items:
+set nohlsearch
diff --git a/ports/beagleboneblack/CSB740_boot.ldt b/ports/beagleboneblack/CSB740_boot.ldt
new file mode 100644
index 0000000..c8bc089
--- /dev/null
+++ b/ports/beagleboneblack/CSB740_boot.ldt
@@ -0,0 +1,63 @@
+/* CSB740_boot.ld:
+ * This is the memory map file used for the boot-flash based version
+ * of MicroMonitor. The only value that should be considered adjustable
+ * here is the base address of the 'dram' memory block.
+ *
+ */
+MEMORY
+{
+ rom : org = ROMBASE, len = ROMLEN
+ dram : org = DRAMBASE, len = DRAMLEN
+}
+
+SECTIONS
+{
+ .text :
+ {
+ boot_base = .;
+ rom_reset.o(.text)
+ *(.glue_7t)
+ *(.glue_7)
+ } >rom
+
+ .data :
+ {
+ *(.data)
+ } >rom
+
+ .sdata :
+ {
+ *(.sdata)
+ } >rom
+
+ .sdata2 :
+ {
+ *(.sdata2)
+ } >rom
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.str1.4)
+ } >rom
+
+ .got :
+ {
+ *(.got)
+ } >rom
+
+ .bss :
+ {
+ bss_start = .;
+ atag_space = .;
+ . += ATAGSIZE;
+ end_atag_space = .;
+ *(.bss) *(COMMON)
+ } >dram
+
+ .sbss :
+ {
+ *(.sbss)
+ bss_end = .;
+ } >dram
+}
diff --git a/ports/beagleboneblack/CSB740_ramtst.ldt b/ports/beagleboneblack/CSB740_ramtst.ldt
new file mode 100644
index 0000000..76fbce4
--- /dev/null
+++ b/ports/beagleboneblack/CSB740_ramtst.ldt
@@ -0,0 +1,59 @@
+etheraddr = MACADDRBASE;
+alt_tfsdevtbl_base = ALTTFSDEVTBLBASE;
+
+MEMORY
+{
+ rom : org = RAMTSTROMBASE, len = RAMTSTROMLEN
+}
+
+SECTIONS
+{
+ .text :
+ {
+ boot_base = .;
+ ram_reset.o(.text)
+ *(.glue_7t)
+ *(.glue_7)
+ } >rom
+
+ .data :
+ {
+ *(.data)
+ } >rom
+
+ .sdata :
+ {
+ *(.sdata)
+ } >rom
+
+ .sdata2 :
+ {
+ *(.sdata2)
+ } >rom
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.str1.4)
+ } >rom
+
+ .got :
+ {
+ *(.got)
+ } >rom
+
+ .bss :
+ {
+ bss_start = .;
+ atag_space = .;
+ . += ATAGSIZE;
+ end_atag_space = .;
+ *(.bss) *(COMMON)
+ } >rom
+
+ .sbss :
+ {
+ *(.sbss)
+ bss_end = .;
+ } >rom
+}
diff --git a/ports/beagleboneblack/Makefile b/ports/beagleboneblack/Makefile
new file mode 100644
index 0000000..3a350c6
--- /dev/null
+++ b/ports/beagleboneblack/Makefile
@@ -0,0 +1,129 @@
+###############################################################################
+#
+# CSB740 board makefile.
+#
+#
+PLATFORM = CSB740
+TOPDIR = $(UMONTOP)
+TGTDIR = csb740
+CPUTYPE = arm
+FILETYPE = elf
+
+# Using tools installed by "sudo apt-get install gcc-arm-none-eabi"...
+ABIDIR = /usr/lib/gcc/arm-none-eabi/4.8.2
+LIBABIDIR = -L $(ABIDIR)
+TOOL_PREFIX = /usr/bin/arm-none-eabi
+
+COMMON_AFLAGS = -c -D PLATFORM_$(PLATFORM)=1 -D ASSEMBLY_ONLY
+CUSTOM_CFLAGS = -mcpu=arm1136j-s -O2 -isystem $(ABIDIR)/include -Wno-char-subscripts
+
+
+###############################################################################
+#
+# Memory map configuration:
+# The following variables are used to establish the system's memory map.
+#
+BOOTROMBASE=0x08000000
+BOOTROMLEN=0x100000
+BOOTRAMBASE=0x80000000
+BOOTRAMLEN=0x100000
+RAMTSTROMBASE=0x80100000
+RAMTSTROMLEN=0x100000
+ATAGSIZE=0x1000
+
+# These next two hard-coded values are used by the ramtst version of
+# uMon to allow it to know where these flash-based structures are located.
+MACADDRBASE=0x08000020
+ALTTFSDEVTBLBASE=0x08000040
+
+include $(TOPDIR)/target/make/common.make
+
+# Build each variable from a list of individual filenames...
+#
+LOCSSRC =
+CPUSSRC = vectors_arm.S
+LOCCSRC = ad7843.c cpuio.c etherdev.c nand740.c omap3530_gpio.c \
+ omap3530_lcd.c omap3530_sdmmc.c
+COMCSRC = arp.c cast.c cache.c chario.c cmdtbl.c \
+ docmd.c dhcp_00.c dhcpboot.c dns.c edit.c env.c ethernet.c \
+ flash.c gdb.c icmp.c if.c ledit_vt100.c monprof.c \
+ fbi.c font.c mprintf.c memcmds.c malloc.c moncom.c memtrace.c \
+ misccmds.c misc.c nand.c password.c redirect.c \
+ reg_cache.c sbrk.c sd.c \
+ start.c struct.c symtbl.c syslog.c tcpstuff.c tfs.c tfsapi.c \
+ tfsclean1.c tfscli.c tfsloader.c tfslog.c tftp.c timestuff.c \
+ tsi.c xmodem.c
+CPUCSRC = ldatags.c except_arm.c misc_arm.c strace_arm.c
+IODEVSRC = smsc911x.c uart16550.c fb_draw.c
+FLASHSRC = s29gl512n_16x1.c
+
+
+include $(TOPDIR)/target/make/objects.make
+
+OBJS = $(LOCSOBJ) $(CPUSOBJ) $(LOCCOBJ) $(CPUCOBJ) $(COMCOBJ) \
+ $(FLASHOBJ) $(IODEVOBJ)
+
+#########################################################################
+#
+# Targets...
+
+# boot:
+# The default target is "boot", a shortcut to $(BUILDDIR)/boot.$(FILETYPE).
+# This builds the bootflash image that can be used by 'newmon' to
+# load a new version onto an already running system.
+#
+boot: $(BUILDDIR)/boot.$(FILETYPE)
+ @echo Boot version of uMon built under $(BUILDDIR) ...
+ @ls $(BUILDDIR)/boot*
+
+# ramtst:
+# A shortcut to $(BUILDDIR)/ramtst.$(FILETYPE). This is a version of uMon
+# that resides strictly in RAM and is used for two main purposes:
+# 1. To test new monitor features prior to burning the boot flash.
+# 2. To be downloaded into the RAM space of a board that has no programmed
+# boot flash. This provides a running monitor that can then accept
+# an incoming bootflash image using 'newmon'.
+#
+ramtst: $(BUILDDIR)/ramtst.$(FILETYPE)
+ @echo Ram-resident test version of uMon built under $(BUILDDIR) ...
+ @ls $(BUILDDIR)/ramtst*
+
+$(BUILDDIR)/boot.$(FILETYPE): $(BUILDDIR) $(OBJS) libz.a \
+ libg.a makefile
+ $(CC) $(ASMFLAGS) -o rom_reset.o rom_reset.S
+ $(MAKE_MONBUILT)
+ sed -e s/ROMBASE/$(BOOTROMBASE)/ -e s/ROMLEN/$(BOOTROMLEN)/ \
+ -e s/DRAMBASE/$(BOOTRAMBASE)/ -e s/DRAMLEN/$(BOOTRAMLEN)/ -e s/ATAGSIZE/$(ATAGSIZE)/ \
+ $(PLATFORM)_$(@F:.$(FILETYPE)=.ldt) > $(PLATFORM)_$(@F:.$(FILETYPE)=.ld)
+ $(LINK) -e coldstart $(OBJS) monbuilt.o libz.a \
+ libg.a $(LIBABIDIR) $(LIBGCC)
+ $(MAKE_BINARY)
+ $(MAKE_GNUSYMS)
+
+$(BUILDDIR)/ramtst.$(FILETYPE): $(BUILDDIR) $(OBJS) libz.a \
+ libg.a makefile
+ $(CC) $(ASMFLAGS) -o ram_reset.o ram_reset.S
+ $(MAKE_MONBUILT)
+ sed -e s/RAMTSTROMBASE/$(RAMTSTROMBASE)/ \
+ -e s/RAMTSTROMLEN/$(RAMTSTROMLEN)/ -e s/ATAGSIZE/$(ATAGSIZE)/ \
+ -e s/MACADDRBASE/$(MACADDRBASE)/ -e s/ALTTFSDEVTBLBASE/$(ALTTFSDEVTBLBASE)/ \
+ $(PLATFORM)_$(@F:.$(FILETYPE)=.ldt) > $(PLATFORM)_$(@F:.$(FILETYPE)=.ld)
+
+ $(LINK) -e coldstart $(OBJS) monbuilt.o libz.a libg.a $(LIBGCC)
+ $(MAKE_BINARY)
+ $(MAKE_GNUSYMS)
+
+include $(TOPDIR)/target/make/rules.make
+
+
+#########################################################################
+#
+# Miscellaneous...
+cscope_local:
+ ls rom_reset.S ram_reset.S >cscope.files
+ ls $(FLASHDIR)/s29gl512n_16x1.c >>cscope.files
+ ls $(FLASHDIR)/s29gl512n_16x1.h >>cscope.files
+
+help_local:
+
+varcheck:
diff --git a/ports/beagleboneblack/_vimrc b/ports/beagleboneblack/_vimrc
new file mode 100644
index 0000000..2a127e5
--- /dev/null
+++ b/ports/beagleboneblack/_vimrc
@@ -0,0 +1,13 @@
+" Very basic VIM startup file
+"
+" Set tab stop to 4 characters:
+set ts=4
+
+" Turn off syntax-sensitive coloring:
+" syntax off
+
+" Enable C-style indentation:
+" set cindent
+
+" Disable the highlighting of search items:
+set nohlsearch
diff --git a/ports/beagleboneblack/ad7843.c b/ports/beagleboneblack/ad7843.c
new file mode 100644
index 0000000..79e37ba
--- /dev/null
+++ b/ports/beagleboneblack/ad7843.c
@@ -0,0 +1,334 @@
+//==========================================================================
+//
+// ad7843.c
+//
+// Author(s): Michael Kelly - Cogent Computer Systems, Inc.
+// Date: 03/06/03
+// Description: AD7843 Interface routines for CSB740
+// Modified from MC9328mxl version to use SPI1
+//
+//==========================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+#include "omap3530.h"
+#include "cpu_gpio.h"
+#include "ad7843.h"
+#include "cli.h"
+#include "umongpio.h"
+
+//--------------------------------------------------------------------------
+// function prototypes
+//
+int ads_init(void);
+int ads_rd(uchar ads_ctl);
+
+extern void udelay(int delay);
+
+#ifdef AD7843_GPIOMODE
+
+// After several days trying to get the OMAP's SPI3 controller to interface
+// to the AD7843, I gave up and implemented the protocol with GPIO...
+// SPI_CS: GPIO_91
+// SPI_CLK: GPIO_88
+// SPI_MOSI: GPIO_89
+// SPI_MISO: GPIO_90
+
+#define clrSpiCs() GPIO3_REG(GPIO_DATAOUT) &= ~BIT27
+#define setSpiCs() GPIO3_REG(GPIO_DATAOUT) |= BIT27
+#define clrSpiClk() GPIO3_REG(GPIO_DATAOUT) &= ~BIT24
+#define setSpiClk() GPIO3_REG(GPIO_DATAOUT) |= BIT24
+#define clrSpiMosi() GPIO3_REG(GPIO_DATAOUT) &= ~BIT25
+#define setSpiMosi() GPIO3_REG(GPIO_DATAOUT) |= BIT25
+#define getSpiMiso() (GPIO3_REG(GPIO_DATAIN) & BIT26) ? 1 : 0
+
+
+// ads_rd():
+// A bit-banged implementation of the SPI access for AD7843...
+// Slow and steady gets the job done!
+//
+int
+ads_rd(uchar ads_ctl)
+{
+ ushort mask, val;
+
+ clrSpiClk();
+ clrSpiCs();
+
+ for(mask = 0x80;mask != 0;mask >>= 1) {
+ if (ads_ctl & mask)
+ setSpiMosi();
+ else
+ clrSpiMosi();
+
+ setSpiClk();
+ clrSpiClk();
+ }
+
+ val = 0;
+ for(mask = 0x8000;mask != 0;mask >>= 1) {
+ setSpiClk();
+ if (getSpiMiso())
+ val |= mask;
+ clrSpiClk();
+ }
+
+ clrSpiClk();
+ setSpiCs();
+ return(val);
+}
+
+int
+ads_init(void)
+{
+ GPIO3_REG(GPIO_OE) &= ~(BIT27 | BIT25 | BIT24); // 0 = out
+ GPIO3_REG(GPIO_OE) |= BIT26;
+ setSpiCs();
+ clrSpiClk();
+ clrSpiMosi();
+ return(0);
+}
+
+#else
+
+//--------------------------------------------------------------------------
+// ads_init()/ads_rd():
+//
+// This routine sets up the OMAP3530 SPI3 port. It also turns on
+// the AD7843 pen interrupt via a dummy read. We are using CS0 on SPI3.
+// Can't get this to work. Signals look good on scope, but we're not
+// able to read the data back; hence the need for a GPIO version (above).
+
+int
+ads_rd(uchar ads_ctl)
+{
+ volatile ulong rxval;
+
+ SPI3_REG(SPI_IRQSTATUS) = 0x0003777f;
+ SPI3_REG(SPI_IRQENABLE) = 0x0000007f;
+ SPI3_REG(SPI_CH0_CTRL) = 0x00000001; // Enable SPI3 Channel 0
+
+ // We have this OMAP3530 SPI ctrlr set up in 24-bit data mode, full
+ // duplex transmit/receive. So, put the byte to be transferred in the
+ // upper 8 bits of the 24-bit word, then read back the next 16 bits...
+ SPI3_REG(SPI_TXD0) = ads_ctl << 16;
+
+ // Wait for the receive channel to be full...
+ while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_RX0_FULL));
+
+ SPI3_REG(SPI_IRQSTATUS) = 0x0003777f;
+
+ // Read the value...
+ rxval = SPI3_REG(SPI_RXD0);
+
+ SPI3_REG(SPI_CH0_CTRL) = 0x00000000; // Disable SPI3 Channel 0
+
+// if (rxval)
+// printf("%08x\n",rxval);
+
+ return (rxval);
+}
+
+int
+ads_init()
+{
+ unsigned long conf;
+
+
+ // Soft reset...
+ SPI3_REG(SPI_SYSCONFIG) = 0x00000002;
+
+ // Wait for reset done...
+ while((SPI3_REG(SPI_SYSSTATUS) & 1) == 0);
+
+ // Configure chan zero of SPI3...
+ SPI3_REG(SPI_IRQSTATUS) = 0x0003777f;
+ SPI3_REG(SPI_IRQENABLE) = 0x0000007f;
+ SPI3_REG(SPI_MODULCTRL) = 0x00000000; // Master, auto CS generation
+ SPI3_REG(SPI_CH0_CTRL) = 0x00000001; // Enable SPI3 Channel 0
+
+ conf = SPI_CH_CONF_DPE0
+ | SPI_CH_CONF_TRM_TR
+ | SPI_CH_CONF_WL(23) // 24-bit data mode
+ | SPI_CH_CONF_EPOL // CS is active low
+ | SPI_CH_CONF_SB_POL //
+ | SPI_CH_CONF_CLKD(9); // divide by 512 = 93Khz
+
+ SPI3_REG(SPI_CH0_CONF) = conf;
+
+ // enable the AD7843 so it can generate a touch interrupt.
+ // this consists of reading any channel, but setting the
+ // power down mode in the control byte to 00b. note we
+ // flush the returned data
+
+ if (ads_rd(AD7843_S | AD7843_ADD_DFR_Y | AD7843_PD_MOD0) == -1)
+ {
+ printf("Error returned from ads_rd(0x%02x)!\n", (AD7843_S | AD7843_ADD_DFR_Y | AD7843_PD_MOD0));
+ return -1;
+ }
+
+ return 0;
+}
+#endif
+
+
+//--------------------------------------------------------------------------
+char *adsHelp[] = {
+ "Screen touch demo using AD7843 and OMAP3530 SPI port.",
+ "",
+ "Detect screen touches and display the x,y values via",
+ "the AD7843 and OMAP3530 SPI port.",
+ 0
+};
+
+int ads(int argc, char *argv[])
+{
+ uchar c;
+ int pen, i;
+ //int last_x, last_y;
+ int sum_x, sum_y, average_x, average_y;
+
+ // init the SPI and AD7843
+ if (ads_init() == -1)
+ {
+ printf("Error intializing AD7843!\n");
+ return (CMD_FAILURE);
+ }
+
+ printf("Waiting for Touch (Press \'X\' to end test)...\n");
+
+ pen = 0;
+ while (1)
+ {
+ if (gotachar())
+ {
+ c = getchar();
+ if ((c == 'X') || (c == 'x')) goto done;
+ if (c == 'L') {
+ printf("In ads_rd loop...\n");
+ while(1)
+ ads_rd(AD7843_S | AD7843_PD_MOD0 | AD7843_ADD_DFR_X);
+ }
+ }
+ if (GPIO_tst(PIRQ) == 0)
+ {
+ printf("Pen Down....\n");
+ pen = 1;
+ //last_x = last_y = 0;
+ while(GPIO_tst(PIRQ) == 0) // keep reading until touch goes away
+ {
+ sum_x = sum_y = 0;
+
+ // display every 4 samples
+ for (i = 0; i < 64 ; i++)
+ {
+ sum_x += ads_rd(AD7843_S | AD7843_PD_MOD0 | AD7843_ADD_DFR_X);
+ sum_y += ads_rd(AD7843_S | AD7843_PD_MOD0 | AD7843_ADD_DFR_Y);
+ }
+ average_x = sum_x/4;
+ average_y = sum_y/4;
+
+ //if ((average_x != last_x) || (average_y != last_y))
+ printf("X = %04d, Y = %04d\n", average_x, average_y);
+
+ //last_x = average_x;
+ //last_y = average_y;
+
+ } // while pen is down
+ }
+ if (pen)
+ {
+ printf("Pen Up....\n");
+ pen = 0;
+ }
+
+ }
+
+done:
+ return(CMD_SUCCESS);
+}
+
+
+/* The next four functions are required for the "scribble" feature in
+ * the FBI command to work...
+ */
+#include "tsi.h"
+
+#define TOUCH_MAX_YVAL 32760
+#define TOUCH_MAX_XVAL 30752
+
+/* tsi_init():
+ * Used to initialize the touch screen interface.
+ */
+int
+tsi_init(void)
+{
+ return(ads_init());
+}
+
+/* tsi_active():
+ * Return 1 if the screen is being touched, else 0.
+ */
+int
+tsi_active(void)
+{
+ if (GPIO_tst(PIRQ) == 0)
+ return(1);
+ return(0);
+}
+
+/* tsi_getx()/tsi_gety():
+ * Return the current 'x' or 'y' position detected by the touch screen.
+ * Notice that these functions return a value that is relative to the
+ * frame-buffer coordinates, not raw the coordinates generated by the
+ * touch-screen hardware.
+ * This requires not only that the incoming value from the AD7843 be
+ * normalized to the range of the X/Y coordinates of the frame buffer,
+ * but it also requires that the 'Y' coordinate be adjusted to be from
+ * top-down, not bottom up.
+ */
+int
+tsi_getx(void)
+{
+ int i, val, tot, stot, tmp;
+
+ tot = stot = 0;
+
+ /* Attempt 8 samples, then average...
+ */
+ for(i=0;i<8;i++) {
+ tmp = ads_rd(AD7843_S | AD7843_PD_MOD0 | AD7843_ADD_DFR_X);
+ if ((tmp > 0) && (tmp < TOUCH_MAX_XVAL)) {
+ tot += tmp;
+ stot++;
+ }
+ }
+ tot /= stot;
+
+ val = tot / (TOUCH_MAX_XVAL/PIXELS_PER_ROW);
+ return(val);
+}
+
+int
+tsi_gety(void)
+{
+ int i, val, tot, stot, tmp;
+
+ tot = stot = 0;
+
+ /* Attempt 8 samples, then average...
+ */
+ for(i=0;i<8;i++) {
+ tmp = ads_rd(AD7843_S | AD7843_PD_MOD0 | AD7843_ADD_DFR_Y);
+ if ((tmp > 0) && (tmp < TOUCH_MAX_YVAL)) {
+ tot += tmp;
+ stot++;
+ }
+ }
+ tot /= stot;
+
+ val = PIXELS_PER_COL - (tot/(TOUCH_MAX_YVAL/PIXELS_PER_COL));
+ return(val);
+}
diff --git a/ports/beagleboneblack/ad7843.h b/ports/beagleboneblack/ad7843.h
new file mode 100644
index 0000000..f4a0b71
--- /dev/null
+++ b/ports/beagleboneblack/ad7843.h
@@ -0,0 +1,35 @@
+//==========================================================================
+//
+// ad7843.h
+//
+// Author(s): Michael Kelly, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 03/06/03
+// Description: This file contains register offsets and bit defines
+// for the Analog Devices AD7843 Touch Screen Controller
+//
+
+//
+// Bit positions for AD7843 Control byte
+//
+#define AD7843_S 0x80 // Start bit, always 1
+#define AD7843_8BIT 0x08 // 0 = 12-bit conversion, 1 = 8-bits
+#define AD7843_SER 0x04 // 0 = Differential, 1 = Single ended
+
+// Address select defines for Single-Ended mode
+#define AD7843_ADD_SER_Y (AD7843_SER | (0x1 << 4)) // Y position measurement
+#define AD7843_ADD_SER_IN3 (AD7843_SER | (0x2 << 4)) // auxillary input 1 measurement
+#define AD7843_ADD_SER_X (AD7843_SER | (0x5 << 4)) // X position measurement
+#define AD7843_ADD_SER_IN4 (AD7843_SER | (0x6 << 4)) // auxillary input 2 measurement
+
+// Address select defines for Differential mode
+#define AD7843_ADD_DFR_Y (0x1 << 4) // Y position measurement
+#define AD7843_ADD_DFR_X (0x5 << 4) // X position measurement
+
+// Power Down Modes
+#define AD7843_PD_MOD0 0x0 // low-power mode, no power-up delay, *IRQ is enabled
+#define AD7843_PD_MOD1 0x1 // same as low-power mode, except *IRQ is disabled
+#define AD7843_PD_MOD2 0x2 // device on, *IRQ is enabled
+#define AD7843_PD_MOD3 0x3 // device on, *IRQ is disabled
+
+//#define AD7843_GPIOMODE
diff --git a/ports/beagleboneblack/ads7846.c b/ports/beagleboneblack/ads7846.c
new file mode 100644
index 0000000..e3b2a68
--- /dev/null
+++ b/ports/beagleboneblack/ads7846.c
@@ -0,0 +1,180 @@
+//==========================================================================
+//
+// ads7846.c
+//
+// Author(s): Michael Kelly - Cogent Computer Systems, Inc.
+// Date: 03/06/03
+// Description: ADS7846 Interface routines for CSB740
+// Modified from MC9328mxl version to use SPI1
+//
+//==========================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+#include "omap3530.h"
+#include "cpu_gpio.h"
+#include "ads7846.h"
+#include "cli.h"
+#include "umongpio.h"
+
+//--------------------------------------------------------------------------
+// function prototypes
+//
+int ads_init(void);
+int ads_rd(uchar ads_ctl);
+
+extern void udelay(int delay);
+
+//--------------------------------------------------------------------------
+// ads_init()
+//
+// This routine sets up the OMAP3530 SPI3 port in Microwire mode
+// (8 bit control, 16 bit data, 24 bit total). It also turns on
+// the ADS7843 pen interrupt via a dummy read. Note that we assume
+// that PERCLK2 is 12Mhz (HCLK/4). We are using CS0 on SPI3.
+//
+int ads_init()
+{
+ volatile uchar temp;
+
+
+ SPI3_REG(SPI_CH0_CTRL) = 0x00; // Disable SPI3 Channel 0
+
+ SPI3_REG(SPI_CH0_CONF) = SPI_CH_CONF_CLKG
+ | SPI_CH_CONF_DPE0 // no transmission on SPI3_MISO
+ | SPI_CH_CONF_WL(7) // 8-bit data mode
+ | SPI_CH_CONF_EPOL // CS is active low
+// | SPI_CH_CONF_SB_POL //
+// | SPI_CH_CONF_SBE //
+ | SPI_CH_CONF_CLKD(9); // divide by 512 = 93Khz
+// | SPI_CH_CONF_PHA; // Data is latched on even numbered edges
+// | SPI_CH_CONF_POL; // SPI clock is active low
+
+ SPI3_REG(SPI_MODULCTRL) = 0x0; // Functional mode, Master, and auto CS generation
+
+ SPI3_REG(SPI_CH0_CTRL) = 0x01; // Enable SPI3 Channel 0
+
+ // enable the ADS7846 so it can generate a touch interrupt.
+ // this consists of reading any channel, but setting the
+ // power down mode in the control byte to 00b. note we
+ // flush the returned data
+ //ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_ADD_DFR_X);
+ ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_8BIT | ADS7846E_ADD_DFR_Y);
+// ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_ADD_DFR_Y);
+ temp = SPI3_REG(SPI_RXD0);
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+int ads_rd(uchar ads_ctl)
+{
+ int timeout = 100;
+ volatile uchar temp0, temp1;
+
+ // the OMAP3530 only handles up to 16-bits per transfer
+ // so we send 8-bits at a time to get our total of 24
+
+// SPI3_REG(SPI_TXD0) = ads_ctl;
+// udelay(10);
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_TX0_EMPTY));
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_RX0_FULL));
+// temp0 = SPI3_REG(SPI_RXD0);
+//
+// SPI3_REG(SPI_TXD0) = 0;
+// udelay(10);
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_TX0_EMPTY));
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_RX0_FULL));
+// temp0 = SPI3_REG(SPI_RXD0);
+//
+// SPI3_REG(SPI_TXD0) = 0;
+// udelay(10);
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_TX0_EMPTY));
+// while (!(SPI3_REG(SPI_IRQSTATUS) & SPI_RX0_FULL));
+// temp1 = SPI3_REG(SPI_RXD0);
+
+ SPI3_REG(SPI_TXD0) = ads_ctl;
+ udelay(10);
+ while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_TX0_EMPTY));
+ while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_RX0_FULL));
+ temp0 = SPI3_REG(SPI_RXD0);
+
+ SPI3_REG(SPI_TXD0) = 0;
+ udelay(10);
+ while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_TX0_EMPTY));
+ while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_RX0_FULL));
+ temp0 = SPI3_REG(SPI_RXD0);
+
+// SPI3_REG(SPI_TXD0) = 0;
+// udelay(10);
+// while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_TX0_EMPTY));
+// while (!(SPI3_REG(SPI_CH0_STAT) & SPI_CH_RX0_FULL));
+// temp1 = SPI3_REG(SPI_RXD0);
+ temp1 = 0;
+ return ((temp0 << 8) | temp1);
+}
+
+//--------------------------------------------------------------------------
+char *adsHelp[] = {
+ "Screen touch demo using ADS7846 and OMAP3530 SPI port.",
+ "",
+ 0
+};
+
+int ads(int argc, char *argv[])
+{
+ uchar c;
+ int pen, i;
+ int average_x, average_y;
+
+ // init the SPI and ADS7846
+ if (ads_init() == -1)
+ {
+ printf("Error intializing ADS7846!\n");
+ return (CMD_FAILURE);
+ }
+
+ printf("Waiting for Touch (Press \'X\' to end test)...\n");
+
+ pen = 0;
+ while (1)
+ {
+ if (gotachar())
+ {
+ c = getchar();
+ if ((c == 'X') || (c == 'x')) goto done;
+ }
+ if (GPIO_tst(PIRQ) == 0)
+ {
+ printf("Pen Down....\n");
+ pen = 1;
+ while(GPIO_tst(PIRQ) == 0) // keep reading until touch goes away
+ {
+ average_x = 0;
+ average_y = 0;
+
+ // display every 256 samples (less if pen is down a short time)
+ for (i = 0; i < 256 ; i++)
+ {
+// average_x += ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_ADD_DFR_X);
+// average_y += ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_ADD_DFR_Y);
+ average_x += ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_8BIT | ADS7846E_ADD_DFR_X);
+ average_y += ads_rd(ADS7846E_S | ADS7846E_PD_ADC | ADS7846E_8BIT | ADS7846E_ADD_DFR_Y);
+ }
+ printf("X = %04d, Y = %04d\n", average_x/i, average_y/i);
+
+ } // while pen is down
+ }
+ if (pen)
+ {
+ printf("Pen Up....\n");
+ pen = 0;
+ }
+
+ }
+
+done:
+ return(CMD_SUCCESS);
+}
diff --git a/ports/beagleboneblack/ads7846.h b/ports/beagleboneblack/ads7846.h
new file mode 100644
index 0000000..9ee33dc
--- /dev/null
+++ b/ports/beagleboneblack/ads7846.h
@@ -0,0 +1,56 @@
+//==========================================================================
+//
+// ads7846.h
+//
+// Author(s): Michael Kelly, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 03/06/03
+// Description: This file contains register offsets and bit defines
+// for the TI ADS7846 Touch Screen Controller
+//
+
+//
+// Bit positions for ADS7846E Control byte
+//
+#define ADS7846E_S 0x80 // Start bit, always 1
+#define ADS7846E_8BIT 0x08 // 0 = 12-bit conversion, 1 = 8-bits
+#define ADS7846E_SER 0x04 // 0 = Differential, 1 = Single ended
+
+//
+// Address select defines for single ended mode (or'ed with the single ended select bit)
+//
+// USE FOR ADS7846
+//#define ADS7846E_ADD_SER_TEMP0 (ADS7846E_SER | (0x0 << 4)) // temperature measurement 1
+//#define ADS7846E_ADD_SER_Y (ADS7846E_SER | (0x1 << 4)) // Y position measurement
+//#define ADS7846E_ADD_SER_BAT (ADS7846E_SER | (0x2 << 4)) // battery input measurement
+//#define ADS7846E_ADD_SER_Z1 (ADS7846E_SER | (0x3 << 4)) // pressure measurement 1
+//#define ADS7846E_ADD_SER_Z2 (ADS7846E_SER | (0x4 << 4)) // pressure measurement 2
+//#define ADS7846E_ADD_SER_X (ADS7846E_SER | (0x5 << 4)) // X position measurement
+//#define ADS7846E_ADD_SER_AUX (ADS7846E_SER | (0x6 << 4)) // auxillary input measurement
+//#define ADS7846E_ADD_SER_TEMP1 (ADS7846E_SER | (0x7 << 4)) // temperature measurement 2
+
+// USE FOR ADS7843
+//#define ADS7846E_ADD_SER_TEMP0 (ADS7846E_SER | (0x0 << 4)) // temperature measurement 1
+#define ADS7846E_ADD_SER_Y (ADS7846E_SER | (0x1 << 4)) // Y position measurement
+//#define ADS7846E_ADD_SER_BAT (ADS7846E_SER | (0x2 << 4)) // battery input measurement
+//#define ADS7846E_ADD_SER_Z1 (ADS7846E_SER | (0x2 << 4)) // pressure measurement 1
+//#define ADS7846E_ADD_SER_Z2 (ADS7846E_SER | (0x6 << 4)) // pressure measurement 2
+#define ADS7846E_ADD_SER_X (ADS7846E_SER | (0x5 << 4)) // X position measurement
+//#define ADS7846E_ADD_SER_AUX (ADS7846E_SER | (0x6 << 4)) // auxillary input measurement
+//#define ADS7846E_ADD_SER_TEMP1 (ADS7846E_SER | (0x7 << 4)) // temperature measurement 2
+
+//
+// Address select defines for differential mode
+//
+#define ADS7846E_ADD_DFR_X (0x1 << 4) // Y position measurement
+//#define ADS7846E_ADD_DFR_Z1 (0x2 << 4) // pressure measurement 1
+//#define ADS7846E_ADD_DFR_Z2 (0x6 << 4) // pressure measurement 2
+#define ADS7846E_ADD_DFR_Y (0x5 << 4) // X position measurement
+
+//
+// Power Down Modes
+//
+#define ADS7846E_PD_LPWR 0x0 // low-power mode, no power-up delay, *IRQ is enabled
+#define ADS7846E_PD_REF 0x1 // 2.5V reference off, ADC on, requires delay before conversion
+#define ADS7846E_PD_ADC 0x2 // ADC off, REF on, no delay required
+#define ADS7846E_PD_IRQ 0x3 // device on, but *IRQ is disabled
diff --git a/ports/beagleboneblack/bashrc b/ports/beagleboneblack/bashrc
new file mode 100644
index 0000000..b329597
--- /dev/null
+++ b/ports/beagleboneblack/bashrc
@@ -0,0 +1,12 @@
+PS1=CSB740:
+export TITLE="COGENT CSB740 ARM Monitor Development"
+export UMONTOP=../../umon_main
+export tools=$UMONTOP/host
+export target=$UMONTOP/target
+export cpu=$target/cpu
+export zlib=$target/zlib
+export com=$target/common
+export misc=$target/misc
+export make=$target/make
+export flash=$target/flash
+export dev=$target/dev
diff --git a/ports/beagleboneblack/bdi2000.cfg b/ports/beagleboneblack/bdi2000.cfg
new file mode 100644
index 0000000..93a82cf
--- /dev/null
+++ b/ports/beagleboneblack/bdi2000.cfg
@@ -0,0 +1,188 @@
+; bdiGDB configuration for TI OMAP3430 ES1.0
+; ------------------------------------------
+;
+; To halt the core as soon as possible after power-up,
+; select EMU1=1,EMU0=0 (Wait In Reset mode WIR).
+;
+; Commands supported in the SCANINIT and SCANPOST strings:
+;
+; I<n>=<...b2b1b0> write IR, b0 is first scanned
+; D<n>=<...b2b1b0> write DR, b0 is first scanned
+; n : the number of bits 1..256
+; bx : a data byte, two hex digits
+; W<n> wait for n (decimal) micro seconds
+; T1 assert TRST
+; T0 release TRST
+; R1 assert RESET
+; R0 release RESET
+; CH<n> clock TCK n (decimal) times with TMS high
+; CL<n> clock TCK n (decimal) times with TMS low
+;
+;
+[INIT]
+WREG CPSR 0x000001D3 ;select ARM / supervisor mode
+
+WM32 0x48314048 0x0000aaaa ;disable watchdog WDT2
+WM32 0x48314048 0x00005555 ;disable watchdog WDT2
+
+WGPR 11 0x40200020 ;set frame pointer to free RAM
+WM32 0x40200020 0x40200028 ;dummy stack frame
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Initialize Pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+WM32 0x48002170 0x01190019 ; Enable UART2 RX and TX
+WM32 0x48002a18 0x0018010f ; Enable SYS_CLKOUT1
+WM32 0x480021e0 0x0018010f ; Enable SYS_CLKOUT2
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Initialize Clocks
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;WM32 0x48306d70 0x00000000 ; disable sys_clk1
+;WM32 0x4830729C 0x00000006 ; set polarity
+WM32 0x48306814 0x00000000 ; Enable Interface clock to be Free running
+WM32 0x48004e10 0x00000001 ; Enable L3_ICLK and L4_ICLK
+WM32 0x48004a30 0x00006000 ; Enable Auto Clock for UART1 and UART2
+;WM32 0x48004d70 0x00000000 ; Enable source for SYS_CLKOUT2
+;WM32 0x48004d70 0x00000080 ; Enable SYS_CLKOUT2
+WM32 0x48004a00 0xc3fffe01 ; Turn on all available module clocks
+WM32 0x48004a10 0x7ffffedb ; Turn on all available peripheral clocks
+;WM32 0x48306d70 0x00000080 ; enable sys_clk1
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Initialize CS0
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+WM32 0x6E000010 0x08 ; Set No-idle, Normal Mode, CLK free running
+WM32 0x6E000078 0x00000C48 ; Config7
+WM32 0x6E000060 0x00001200 ; Config1
+WM32 0x6E000064 0x000f0f01 ; Config2
+WM32 0x6E000068 0x00020201 ; Config3
+WM32 0x6E00006C 0x0C060C06 ; Config4
+WM32 0x6E000070 0x01131F1F ; Config5
+WM32 0x6E000074 0x0F030000 ; Config6
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Initialize DDR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;/* SDRAM software reset */
+;/* No idle ack and RESET enable */
+;__raw_writel(0x1A, SDRC_REG(SYSCONFIG));
+WM32 0x6D000010 0x0000001A ; reset DDR
+;sdelay(100);
+DELAY 100
+;/* No idle ack and RESET disable */
+;__raw_writel(0x18, SDRC_REG(SYSCONFIG));
+WM32 0x6D000010 0x00000018 ; release reset
+DELAY 100
+;
+;/* SDRC Sharing register */
+;/* 32-bit SDRAM on data lane [31:0] - CS0 */
+;/* pin tri-stated = 1 */
+;__raw_writel(0x00000100, SDRC_REG(SHARING));
+WM32 0x6D000044 0x00000100
+;
+;/* ----- SDRC Registers Configuration --------- */
+;/* SDRC_MCFG0 register */
+;__raw_writel(0x02584099, SDRC_REG(MCFG_0));
+WM32 0x6D000080 0x02584099
+;
+;/* SDRC_RFR_CTRL0 register */
+;__raw_writel(0x54601, SDRC_REG(RFR_CTRL_0));
+WM32 0x6D0000a4 0x00054601
+;
+;/* SDRC_ACTIM_CTRLA0 register */
+;__raw_writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
+WM32 0x6D00009c 0xA29DB4C6
+;
+;/* SDRC_ACTIM_CTRLB0 register */
+;__raw_writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
+WM32 0x6D0000A0 0x00012214
+;
+;/* Disble Power Down of CKE due to 1 CKE on combo part */
+;__raw_writel(0x00000081, SDRC_REG(POWER));
+WM32 0x6D000070 0x00000081
+;
+;/* SDRC_MANUAL command register */
+;/* NOP command */
+;__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
+WM32 0x6D0000A8 0x00000000
+;
+;/* Precharge command */
+;__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
+WM32 0x6D0000A8 0x00000001
+;
+;/* Auto-refresh command */
+;__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+WM32 0x6D0000A8 0x00000002
+;
+;/* Auto-refresh command */
+;__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
+WM32 0x6D0000A8 0x00000002
+;
+;/* SDRC MR0 register Burst length=4 */
+;__raw_writel(0x00000032, SDRC_REG(MR_0));
+WM32 0x6D000084 0x00000032
+;
+;/* SDRC DLLA control register */
+;__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
+WM32 0x6D000060 0x0000000A
+
+[TARGET]
+CPUTYPE OMAP3430
+CLOCK 1 ; JTAG clock
+POWERUP 2000 ; power-up delay
+TRST PUSHPULL ; TRST driver type (OPENDRAIN | PUSHPULL)
+RESET HARD ; NONE | HARD <n> (ms)
+STARTUP HALT ; let boot code setup the system
+;STARTUP RUN ; let boot code setup the system
+ENDIAN LITTLE ; memory model (LITTLE | BIG)
+;MEMACCESS CORE 10 ; memory access via core (8 TCK's access delay)
+MEMACCESS AHB 8 ; memory access via AHB (64 TCK's access delay)
+;VECTOR CATCH 0x1B ; catch Abort, Undef, Reset
+
+SCANPRED 1 6 ; count for ICEPick TAP
+SCANSUCC 1 8 ; Xilinx
+
+; Configure ICEPick module to make Cortex-A8 DAP-TAP visible
+SCANINIT t1:w1000:t0:w1000: ; toggle TRST,
+SCANINIT ch10:w1000: ; clock TCK with TMS high and wait
+SCANINIT i6=07:d8=89:i6=02: ; connect and select router
+SCANINIT d32=81000080: ; IP control: KeepPowered
+SCANINIT d32=a3002048: ; TAP3: DebugConnect, ForcePower, ForceActive
+SCANINIT d32=81000081: ; IP control: KeepPowered, SysReset
+SCANINIT d32=a3002148: ; enable TAP3
+SCANINIT cl10:i10=ffff ; clock 10 times in RTI, scan bypass
+
+;assert SysSeset after debugger has setup
+;SCANPOST i10=ffff: ; scan bypass
+;SCANPOST i10=002f: ; IP(router) - TAP3(bypass)
+;SCANPOST d33=0102000102: ; IP control = SysReset
+;SCANPOST i10=ffff ; scan bypass
+
+[HOST]
+IP 192.168.1.3
+FILE build_csb740\ramtst.elf
+FORMAT ELF
+LOAD MANUAL ;load file MANUAL or AUTO after reset
+PROMPT CSB740_>
+TELNET NOECHO
+
+[FLASH]
+WORKSPACE 0x80001000 ;workspace at 0x1000
+CHIPSIZE 0x4000000
+CHIPTYPE MIRRORX16
+BUSWIDTH 16
+FILE build_csb740\boot.bin
+FORMAT BIN 0x08000000
+ERASE 0x08000000
+ERASE 0x08020000
+ERASE 0x08040000
+ERASE 0x08060000
+ERASE 0x08080000
+
+[REGS]
+FILE C:\els\abatron\arm11\regOMAP3430.def
diff --git a/ports/beagleboneblack/config.h b/ports/beagleboneblack/config.h
new file mode 100644
index 0000000..8a05ff1
--- /dev/null
+++ b/ports/beagleboneblack/config.h
@@ -0,0 +1,202 @@
+/*
+ * Monitor configuration file for CSB740
+ *
+ * Adapted by Luis Torrico, Cogent Computer Systems, Inc.
+ * email: luis at cogcomp.com
+ *
+ *
+ * General notice:
+ * This code is part of a boot-monitor package developed as a generic base
+ * platform for embedded system designs. As such, it is likely to be
+ * distributed to various projects beyond the control of the original
+ * author. Please notify the author of any enhancements made or bugs found
+ * so that all may benefit from the changes. In addition, notification back
+ * to the author will allow the new user to pick up changes that may have
+ * been made by other users after this version of the code was distributed.
+ *
+ * Author: Ed Sutter
+ * email: esutter at lucent.com
+ * phone: 908-582-2351
+ */
+
+/*
+ * The target_putchar() function also drops the character at the
+ * LCD...
+ */
+//#define MORE_PUTCHAR lcd_putchar
+//#define CONSOLE_UART_BASE (OMAP35XX_L4_IO_BASE+0x6C000)
+#define CONSOLE_UART_BASE 0x4806C000
+
+#define SIO_STEP 4
+#define IEN_DEFAULT 0x40
+#define MCTL_DEFAULT 0x01
+
+#define TIMER_TICKS_PER_MSEC 545000
+
+/* DEFAULT_ETHERADD & DEFAULT_IPADD:
+ * Refer to notes in ethernet.c function EthernetStartup() for details
+ * regarding the use of these definitions.
+ * DEFAULT_IPADD could be set to "DHCP" or "BOOTP" as well.
+ */
+#define DEFAULT_ETHERADD "00:30:23:40:00:" // Cogent Block
+#define DEFAULT_IPADD "192.168.254.110"
+
+#define CPU_LE
+
+// override the app ram base to set it to 2Mbyte. This reserves space
+// for umon and the LCD controller buffer
+#define APPRAMBASE_OVERRIDE 0x80400000
+
+// Establish a user defined function to be called when uMon
+// prints out the startup banner...
+// If this is defined, then the output similar to the following will
+// be printed just above the uMon header...
+// Silicon ID: 1.0
+// CPU Rev: 2, Variant: 1
+// CM Rev: 1.0, PRM Rev: 1.0
+// #define USR_HEADER_FUNC show_revision
+
+/* Defining DONT_CENTER_MONHEADER eliminates the automatic centering
+ * of the monitor's startup banner...
+ */
+#define DONT_CENTER_MONHEADER
+
+/* XBUFCNT & RBUFCNT:
+ * Number of transmit and receive buffers allocated to ethernet.
+ * The total of XBUFCNT+RBUFCNT should not exceed MAXEBDS
+ */
+#define XBUFCNT 8
+#define RBUFCNT 8
+#define XBUFSIZE 2048
+#define RBUFSIZE 2048
+
+/* LOOPS_PER_SECOND:
+ * Approximately the size of a loop that will cause a 1-second delay.
+ * This can be guestimated or modified with the sleep -c command at the
+ * monitor command line.
+ */
+#define LOOPS_PER_SECOND 15000
+
+#define INCLUDE_NANDCMD 0
+
+#if INCLUDE_NANDCMD
+/* Needed for NAND to work with TFSRAM:
+ */
+#define NAND_TFS_BASE 0x10000 // base of TFS in NAND
+
+#define FLASHRAM_BASE 0x80300000
+#define FLASHRAM_END 0x8037ffff
+#define FLASHRAM_SECTORSIZE 0x00010000
+#define FLASHRAM_SPARESIZE FLASHRAM_SECTORSIZE
+#define FLASHRAM_BANKNUM 1
+#define FLASHRAM_SECTORCOUNT 8
+#endif
+
+/* Flash bank configuration:
+ */
+#ifdef FLASHRAM_BASE
+#define FLASHBANKS 2
+#else
+#define FLASHBANKS 1
+#endif
+#define SINGLE_FLASH_DEVICE 1
+#define FLASH_COPY_TO_RAM 1
+#define FLASH_BANK0_BASE_ADDR 0x08000000
+#define FLASH_PROTECT_RANGE "0-2"
+#define FLASH_BANK0_WIDTH 2
+#define FLASH_LARGEST_SECTOR 0x20000
+#define FLASH_LOOP_TIMEOUT 10000000
+#define BUFFERED_WRITE
+
+/* TFS definitions:
+ * TFSSTART: Base address in FLASH at which TFS starts.
+ * TFSEND: End address of TFS in FLASH.
+ * TFSSPARE: Location of sector that is used as the spare sector
+ * by TFS for defragmentation.
+ * TFSSPARESIZE: Size of the spare sector used by TFS for defragmentation.
+ * TFSSECTORCOUNT: Number of eraseable sectors that TFS covers, not including
+ * the TFSSPARE sector.
+ */
+#define TFSSPARESIZE FLASH_LARGEST_SECTOR
+#define TFS_DEVTOT 1
+#define TFSSTART (FLASH_BANK0_BASE_ADDR+0x060000)
+//#define TFSEND (FLASH_BANK0_BASE_ADDR+0x007dffff) // 8MB Flash
+#define TFSEND (FLASH_BANK0_BASE_ADDR+0x00edffff) // 16MB Flash
+//#define TFSEND (FLASH_BANK0_BASE_ADDR+0x03dfffff) // 64MB Flash
+#define TFSSPARE (TFSEND+1)
+#define TFSSECTORCOUNT ((TFSSPARE-TFSSTART)/0x20000)
+#define TFS_EBIN_ELFMSBIN 1
+#define TFS_VERBOSE_STARTUP 1
+#define TFS_ALTDEVTBL_BASE &alt_tfsdevtbl_base
+
+/* Specify CPU/PLATFORM type and name so that common code can be used
+ * for a similar cpu, on different platforms.
+ * The 'TYPE' definition is used for ifdefs in the code and the 'NAME'
+ * is used for printfs in the code.
+ */
+#define CPU_TYPE OMAP3530
+#define CPU_NAME "TI OMAP3530 Cortex-A8"
+#define PLATFORM_TYPE CSB740
+#define PLATFORM_NAME "Cogent CSB740"
+
+/* Specify the size of the memory block (in monitor space) that is to be
+ * allocated to malloc in the monitor. Note that this size can be dynamically
+ * increased using the heap extension option in the heap command.
+ */
+#define ALLOCSIZE (64*1024)
+#define MONSTACKSIZE (16*1024)
+
+// Cogent specific options
+#define INCLUDE_I2C 0
+#define INCLUDE_LCD 1
+
+/* Specify inclusion of subsystems within the monitor here.
+ * Refer to comments in common/monitor/inc_check.h for details on
+ * each of these macros.
+ */
+
+#define INCLUDE_MEMTRACE 1
+#define INCLUDE_MEMCMDS 1
+#define INCLUDE_EDIT 1
+#define INCLUDE_DISASSEMBLER 0
+#define INCLUDE_UNZIP 1
+#define INCLUDE_ETHERNET 1
+#define INCLUDE_ICMP 1
+#define INCLUDE_TFTP 1
+#define INCLUDE_DHCPBOOT 1
+#define INCLUDE_TFS 1
+#define INCLUDE_TFSCLI 1
+#define INCLUDE_TFSAPI 1
+#define INCLUDE_TFSSCRIPT 1
+#define INCLUDE_TFSSYMTBL 1
+#define INCLUDE_XMODEM 1
+#define INCLUDE_LINEEDIT 1
+#define INCLUDE_EE 0
+#define INCLUDE_FLASH 1
+#define INCLUDE_STRACE 1
+#define INCLUDE_CAST 0
+#define INCLUDE_STRUCT 1
+#define INCLUDE_REDIRECT 1
+#define INCLUDE_QUICKMEMCPY 1
+#define INCLUDE_PROFILER 1
+#define INCLUDE_BBC 0
+#define INCLUDE_STOREMAC 1
+#define INCLUDE_SHELLVARS 1
+#define INCLUDE_MALLOC 1
+#define INCLUDE_PORTCMD 0
+#define INCLUDE_SYSLOG 1
+#define INCLUDE_HWTMR 1
+#define INCLUDE_VERBOSEHELP 1
+#define INCLUDE_GDB 1
+#define INCLUDE_USRLVL 0
+#define INCLUDE_JFFS2 0
+#define INCLUDE_JFFS2ZLIB 0
+#define INCLUDE_FBI 1
+#define INCLUDE_TSI 1
+#define INCLUDE_SD 0
+#define INCLUDE_DNS 1
+
+/* Inclusion of this next file will make sure that all of the above
+ * inclusions are legal; and warn/adjust where necessary.
+ */
+#include "inc_check.h"
diff --git a/ports/beagleboneblack/cpu.h b/ports/beagleboneblack/cpu.h
new file mode 100644
index 0000000..ddedd7b
--- /dev/null
+++ b/ports/beagleboneblack/cpu.h
@@ -0,0 +1,25 @@
+/* cpu.h:
+ General notice:
+ This code is part of a boot-monitor package developed as a generic base
+ platform for embedded system designs. As such, it is likely to be
+ distributed to various projects beyond the control of the original
+ author. Please notify the author of any enhancements made or bugs found
+ so that all may benefit from the changes. In addition, notification back
+ to the author will allow the new user to pick up changes that may have
+ been made by other users after this version of the code was distributed.
+
+ Author: Ed Sutter
+ email: esutter at lucent.com
+ phone: 908-582-2351
+
+*/
+#include "omap3530.h"
+
+#define RESETMACRO() \
+{ \
+ WD2_REG(WD_WCRR) = 0xfffffff0; \
+ WD2_REG(WD_WSPR) = 0x0000bbbb; \
+ while(*(volatile unsigned long *)(WD2_BASE_ADD + WD_WWPS)); \
+ WD2_REG(WD_WSPR) = 0x00004444; \
+ while(1); \
+}
diff --git a/ports/beagleboneblack/cpu_gpio.h b/ports/beagleboneblack/cpu_gpio.h
new file mode 100644
index 0000000..cf071db
--- /dev/null
+++ b/ports/beagleboneblack/cpu_gpio.h
@@ -0,0 +1,113 @@
+
+//=============================================================================
+//
+// cpu_gpio.h
+//
+// CPU/Board Specific GPIO assignments
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Date: 05/12/2008
+// Description: This file contains the GPIOIO usage for the CSB733
+//
+//
+//=============================================================================
+
+// PORT 1 - Virtual GPIO Bits 0-31
+#define PORT1_VBIT 0
+// Signal Bit Dir Active Usage
+
+// Define initial direction (0 = output) and value
+#define PORT1_OE 0xFFFFFFFF
+// Define data value
+#define PORT1_DR 0
+
+// -----------------------------------------------------------------------------------------------
+// PORT 2
+#define PORT2_VBIT 32
+// Signal Bit Dir Active Usage
+#define N_RDY_BIT BIT30 // In High NAND Ready
+#define N_RDY PORT2_VBIT + 30
+#define LCD_BKL_BIT BIT26 // Out High LCD Backlight Enable
+#define LCD_BKL PORT2_VBIT + 26
+#define EXP_INT_BIT BIT25 // In Low Expansion Interrupt
+#define EXP_INT PORT2_VBIT + 25
+
+// Define initial direction (0 = output) and value
+#define PORT2_OE ~(LCD_BKL_BIT)
+// Define data value
+#define PORT2_DR (LCD_BKL_BIT)
+
+// -----------------------------------------------------------------------------------------------
+// PORT 3
+#define PORT3_VBIT 64
+
+// Signal Bit Dir Active Usage
+#define GPIO7_BIT BIT28 // In High Set as GPIO Input, pulled high. Shared with SPI1_CS1
+#define GPIO7 PORT3_VBIT + 28
+#define SPI3_CS0_BIT BIT27 // In High SPI3_CS0
+#define SPI3_CS0 PORT3_VBIT + 27
+#define E_INT_BIT BIT1 // In Low LAN9211 Interrupt
+#define E_INT PORT3_VBIT + 1
+
+// Define initial direction (0 = output) and value
+#define PORT3_OE ~(SPI3_CS0_BIT)
+// Define data value
+#define PORT3_DR SPI3_CS0_BIT
+
+// -----------------------------------------------------------------------------------------------
+// PORT 4
+#define PORT4_VBIT 96
+
+// Signal Bit Dir Active Usage
+#define PIRQ_BIT BIT31 // In Low Touch Interrupt from ADS7843
+#define PIRQ PORT4_VBIT + 31
+#define I2C_INT_BIT BIT30 // In Low I2C Interrupt
+#define I2C_INT PORT4_VBIT + 30
+
+// Define initial direction (0 = output) and value
+#define PORT4_OE 0xFFFFFFFF
+// Define data value
+#define PORT4_DR 0
+
+// -----------------------------------------------------------------------------------------------
+// PORT 5
+#define PORT5_VBIT 128
+
+// Signal Bit Dir Active Usage
+#define U_SEL_BIT BIT12 // Out N/A Selects between USB Host or Device
+#define U_SEL PORT5_VBIT + 12
+#define GPIO1_BIT BIT1 // In High Push button on CSB703
+#define GPIO1 PORT5_VBIT + 1
+#define GPIO0_BIT BIT0 // Out N/A LED on CSB703
+#define GPIO0 PORT5_VBIT + 0
+
+// Define initial direction (0 = output) and value
+#define PORT5_OE ~(U_SEL_BIT | GPIO0_BIT)
+// Define data value
+#define PORT5_DR (U_SEL_BIT | GPIO0_BIT)
+
+// -----------------------------------------------------------------------------------------------
+// PORT 6
+#define PORT6_VBIT 160
+
+// Signal Bit Dir Active Usage
+#define GPIO9_BIT BIT25 // In High Set as GPIO Input, pulled high.
+#define GPIO9 PORT6_VBIT + 25
+#define GPIO8_BIT BIT24 // In High Set as GPIO Input, pulled high.
+#define GPIO8 PORT6_VBIT + 24
+#define GPIO2_BIT BIT22 // In High Set as GPIO Input, pulled high.
+#define GPIO2 PORT6_VBIT + 22
+#define GPIO3_BIT BIT21 // In High Set as GPIO Input, pulled high.
+#define GPIO3 PORT6_VBIT + 21
+#define GPIO4_BIT BIT20 // In High Set as GPIO Input, pulled high.
+#define GPIO4 PORT6_VBIT + 20
+#define GPIO5_BIT BIT19 // In High Set as GPIO Input, pulled high.
+#define GPIO5 PORT6_VBIT + 19
+#define GPIO6_BIT BIT17 // In High Set as GPIO Input, pulled high.
+#define GPIO6 PORT6_VBIT + 17
+
+// Define initial direction (0 = output) and value
+#define PORT6_OE 0xFFFFFFFF
+// Define data value
+#define PORT6_DR 0
+
diff --git a/ports/beagleboneblack/cpu_i2c.c b/ports/beagleboneblack/cpu_i2c.c
new file mode 100644
index 0000000..53c3ebb
--- /dev/null
+++ b/ports/beagleboneblack/cpu_i2c.c
@@ -0,0 +1,322 @@
+//==========================================================================
+//
+// cpu_i2c.c
+//
+// Author(s): Michael Kelly - Cogent Computer Systems, Inc.
+// Date: 03/26/2003
+// Description: Generic IIC Routines - requires I2C_SCL and I2C_SDA to
+// be defined in cpu_gpio.h
+//
+//==========================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+#include "cli.h"
+#include "cpu_gpio.h"
+#include "cpu_gpio.h"
+#include "umongpio.h"
+
+//--------------------------------------------------------------------------
+// function prototypes
+//
+ulong i2c_init(void);
+ulong i2c_wr_device(uchar dev, uchar reg, uchar data);
+ulong i2c_rd_device(uchar dev, uchar reg, uchar *data);
+ulong i2c_wr_byte(uchar data);
+uchar i2c_rd_byte(void);
+void i2c_start(void);
+void i2c_stop(void);
+int i2c(int argc,char *argv[]);
+
+extern void udelay(int delay);
+
+//--------------------------------------------------------------------------
+// I2C Macros
+//
+#define I2C_SCL_CLR GPIO_out(I2C_SCL)
+#define I2C_SCL_SET GPIO_in(I2C_SCL)
+
+#define I2C_SDA_CLR GPIO_out(I2C_SDA)
+#define I2C_SDA_SET GPIO_in(I2C_SDA)
+
+#define I2C_SCL_RD GPIO_tst(I2C_SCL)
+#define I2C_SDA_RD GPIO_tst(I2C_SDA)
+
+#define I2C_DELAY udelay(1000)
+
+//--------------------------------------------------------------------------
+// i2c_init()
+//
+// I2C is a shared bus. We drive a low by setting the SCL/SDA GPIO as
+// an output. We must preset a 0 in the GPIO output bit so the line will
+// go low whenever we make it an output. For a high, we make the GPIO an
+// input, thus letting the external pullup to pull the line high.
+//
+ulong i2c_init()
+{
+ GPIO_out(I2C_SCL);
+ GPIO_clr(I2C_SCL);
+ GPIO_in(I2C_SCL);
+
+ GPIO_out(I2C_SDA);
+ GPIO_clr(I2C_SDA);
+ GPIO_in(I2C_SDA);
+
+ return 0;
+
+}
+
+//--------------------------------------------------------------------------
+// i2c_wr_device()
+//
+// This function writes an 8-bit value to the I2C device at the requested
+// register.
+//
+ulong i2c_wr_device(uchar dev, uchar reg, uchar data)
+{
+
+ // issue a start command
+ i2c_start();
+
+ // write the 7-bit device address with write = 0
+ if(i2c_wr_byte((dev << 1) & 0xfe)){
+ return -1;
+ }
+ // Write the 8-bit register address
+ if(i2c_wr_byte(reg)){
+ return -1;
+ }
+ // Write the 8-bit data value
+ if(i2c_wr_byte(data)){
+ return -1;
+ }
+
+ // issue a stop
+ i2c_stop();
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_rd_device()
+//
+// This function reads an 8-bit value from the I2C device at the requested
+// register.
+//
+ulong i2c_rd_device(uchar dev, uchar reg, uchar *data)
+{
+
+ // issue a start command
+ i2c_start();
+
+ // write the 7-bit device address with write = 0
+ if(i2c_wr_byte((dev << 1) & 0xfe)){
+ return -1;
+ }
+ // Write the 8-bit register address
+ if(i2c_wr_byte(reg)){
+ return -1;
+ }
+ // repeat the start command
+ i2c_start();
+ // write the 7-bit device address again plus data direction (read = 1)
+ if(i2c_wr_byte((dev << 1) | 0x01)){
+ return -1;
+ }
+ *data = i2c_rd_byte();
+
+ // issue a stop
+ i2c_stop();
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_wr_byte()
+//
+// This function writes an 8-bit value to the I2C bus, MSB first.
+// Data is written by changing SDA during SCL low, then bringing
+// SCL high. SCL is returned low to setup for the next transition.
+//
+ulong i2c_wr_byte(uchar data)
+{
+
+ int i;
+
+ for (i = 0; i < 8; i++){
+ if (data & 0x80) {
+ // write a 1 bit
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ else {
+ // write a 0 bit
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ data = data << 1;
+ }
+ // Release SDA, bring SCL high, then read SDA.
+ // A low indicates an acknowledge.
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ if(I2C_SDA_RD){ // a high means no ack
+ // re-enable SDA for output
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ return -1;
+ }
+
+ I2C_SCL_CLR;
+ I2C_DELAY;
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_rd_byte()
+//
+// This function reads an 8-bit data value from the I2C bus, MSB first.
+// Data is read from SDA after each low to high SCL transition.
+//
+uchar i2c_rd_byte()
+{
+
+ int i;
+ uchar volatile data;
+
+ data = 0;
+
+ for (i = 0; i < 8; i++){
+ data = data << 1;
+ data = data & 0xfe;
+ // clock the data out of the slave
+ I2C_SCL_SET;
+ I2C_DELAY;
+ // check it
+ if (I2C_SDA_RD){
+ data = data | 0x01;
+ }
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ // generate an extra SCL transition
+ // The slave generates no acknowledge for reads.
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+
+ return data;
+}
+
+
+//--------------------------------------------------------------------------
+// i2c_start()
+//
+// This function issues an I2C start command which is a high to low
+// transition on SDA while SCL is high.
+//
+void i2c_start()
+{
+
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ I2C_SDA_SET;
+ I2C_DELAY;
+}
+
+//--------------------------------------------------------------------------
+// i2c_stop()
+//
+// This function issues an I2C stop command which is a low to high
+// transition on SDA while SCL is high.
+//
+void i2c_stop()
+{
+
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+}
+
+char *i2cHelp[] = {
+ " This command allows the user to read ",
+ " and write devices on the i2c bus. \n ",
+ " Usage:",
+ " i2c -[w] {device} {register} {val/count}",
+ " Options...",
+ " -w write val to device/register",
+ " no options, read from device/register up to count",
+ 0
+};
+
+int i2c(int argc,char *argv[])
+{
+ int i, opt;
+ int write = 0;
+ uchar dev, reg, data, count;
+
+ while ((opt=getopt(argc,argv,"w")) != -1) {
+ if (opt == 'w') write = 1;
+ }
+
+ // make sure we have the right number of paramters
+ if (argc < (optind+3))
+ return(CMD_PARAM_ERROR);
+
+ dev = (uchar) strtoul(argv[optind],(char **)0,0);
+ reg = (uchar) strtoul(argv[optind+1],(char **)0,0);
+
+ // 3rd arg is the data value if it's a write, count if it's a read
+ data = (uchar) strtoul(argv[optind+2],(char **)0,0);
+ count = data;
+ // do it
+ if (write)
+ {
+ printf("Writing 0x%02x to Device 0x%02x @ Register 0x%02x.\n", data, dev, reg);
+ if(i2c_wr_device(dev, reg, data))
+ {
+ printf("I2C Bus Failure - Check Paramters!\n");
+ return (CMD_FAILURE);
+ }
+ }
+ else
+ {
+ for (i = 0; i < count; i++)
+ {
+ printf("Read Device 0x%02x, Register 0x%02x = ", dev, reg + i);
+ if(i2c_rd_device(dev, reg + i, &data))
+ {
+ printf("I2C Bus Failure - Check Paramters!\n");
+ return (CMD_FAILURE);
+ }
+ printf("0x%02x.\n", data);
+ }
+ }
+ return(CMD_SUCCESS);
+}
+
diff --git a/ports/beagleboneblack/cpu_i2c.h b/ports/beagleboneblack/cpu_i2c.h
new file mode 100644
index 0000000..779ee67
--- /dev/null
+++ b/ports/beagleboneblack/cpu_i2c.h
@@ -0,0 +1,269 @@
+//==========================================================================
+//
+// cpu_i2c.c
+//
+// Author(s): Michael Kelly - Cogent Computer Systems, Inc.
+// Date: 03/30/2002
+// Description: CSB272 - 405GP Single Board IIC Routines
+//
+//==========================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+
+//--------------------------------------------------------------------------
+// some 405GP I2C register and bit defines
+//
+#define I2C_XCTL *(vulong *)(0xef60050f) // extended control register
+#define I2C_XCTL_SRST 0x01000000 // Soft Reset Bit - must be set
+ // to 1 to use direct control
+
+#define I2C_DCTL *(vulong *)(0xef600510) // direct control of IIC bits
+#define I2C_DCTL_SDA_OUT 0x08000000 // SDA Out, 0 = drive low, 1 = tri-state
+#define I2C_DCTL_SCL_OUT 0x04000000 // SCL Out, 0 = drive low, 1 = tri-state
+#define I2C_DCTL_SDA_IN 0x02000000 // SDA In, Direct Read
+#define I2C_DCTL_SCL_IN 0x01000000 // SCL In, Direct Read
+
+//--------------------------------------------------------------------------
+// Low level I2C Macros
+//
+#define I2C_SCL_CLR I2C_DCTL &= ~(I2C_DCTL_SCL_OUT)
+#define I2C_SCL_SET I2C_DCTL |= (I2C_DCTL_SCL_OUT)
+
+#define I2C_SDA_CLR I2C_DCTL &= ~(I2C_DCTL_SDA_OUT)
+#define I2C_SDA_SET I2C_DCTL |= (I2C_DCTL_SDA_OUT)
+
+#define I2C_SDA_RD I2C_DCTL & I2C_DCTL_SDA_IN
+#define I2C_SCL_RD I2C_DCTL & I2C_DCTL_SCL_IN
+
+#define I2C_DELAY udelay(100)
+
+//--------------------------------------------------------------------------
+// function prototypes
+//
+ulong i2c_init(void);
+ulong i2c_wr_device(uchar dev, uchar reg, uchar data);
+ulong i2c_rd_device(uchar dev, uchar reg, uchar *data);
+ulong i2c_wr_byte(uchar data);
+uchar i2c_rd_byte(void);
+void i2c_start(void);
+void i2c_stop(void);
+
+extern void udelay(int delay);
+
+extern ulong sed_disp_mode;
+
+//--------------------------------------------------------------------------
+// i2c_init()
+//
+// Initialize the I2C registers for direct I2C control
+ulong i2c_init()
+{
+ // place the automatic I2C logic in reset
+ I2C_XCTL |= I2C_XCTL_SRST;
+
+ // Set the SCL and SDA outputs into tristate
+ I2C_DCTL |= (I2C_DCTL_SDA_OUT | I2C_DCTL_SCL_OUT);
+
+ return 0;
+
+}
+
+//--------------------------------------------------------------------------
+// i2c_wr_device()
+//
+// This function writes an 8-bit value to the I2C device at the requested
+// register.
+//
+ulong i2c_wr_device(uchar dev, uchar reg, uchar data)
+{
+
+ // issue a start command
+ i2c_start();
+
+ // write the 7-bit device address with write = 0
+ if(i2c_wr_byte((dev << 1) & 0xfe)){
+ return -1;
+ }
+ // Write the 8-bit register address
+ if(i2c_wr_byte(reg)){
+ return -1;
+ }
+ // Write the 8-bit data value
+ if(i2c_wr_byte(data)){
+ return -1;
+ }
+
+ // issue a stop
+ i2c_stop();
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_rd_device()
+//
+// This function reads an 8-bit value from the I2C device at the requested
+// register.
+//
+ulong i2c_rd_device(uchar dev, uchar reg, uchar *data)
+{
+
+ // issue a start command
+ i2c_start();
+
+ // write the 7-bit device address with write = 0
+ if(i2c_wr_byte((dev << 1) & 0xfe)){
+ return -1;
+ }
+ // Write the 8-bit register address
+ if(i2c_wr_byte(reg)){
+ return -1;
+ }
+ // repeat the start command
+ i2c_start();
+ // write the 7-bit device address again plus data direction (read = 1)
+ if(i2c_wr_byte((dev << 1) | 0x01)){
+ return -1;
+ }
+ *data = i2c_rd_byte();
+
+ // issue a stop
+ i2c_stop();
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_wr_byte()
+//
+// This function writes an 8-bit value to the I2C bus, MSB first.
+// Data is written by changing SDA during SCL low, then bringing
+// SCL high. SCL is returned low to setup for the next transition.
+//
+ulong i2c_wr_byte(uchar data)
+{
+
+ int i;
+
+ for (i = 0; i < 8; i++){
+ if (data & 0x80) {
+ // write a 1 bit
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ else {
+ // write a 0 bit
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ data = data << 1;
+ }
+ // Release SDA, bring SCL high, then read SDA.
+ // A low indicates an acknowledge.
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ if(I2C_SDA_RD){ // a high means no ack
+ // re-enable SDA for output
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ return -1;
+ }
+
+ I2C_SCL_CLR;
+ I2C_DELAY;
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// i2c_rd_byte()
+//
+// This function reads an 8-bit data value from the I2C bus, MSB first.
+// Data is read from SDA after each low to high SCL transition.
+//
+uchar i2c_rd_byte()
+{
+
+ int i;
+ uchar volatile data;
+
+ data = 0;
+
+ for (i = 0; i < 8; i++){
+ data = data << 1;
+ data = data & 0xfe;
+ // clock the data out of the slave
+ I2C_SCL_SET;
+ I2C_DELAY;
+ // check it
+ if (I2C_SDA_RD){
+ data = data | 0x01;
+ }
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ }
+ // generate an extra SCL transition
+ // The slave generates no acknowledge for reads.
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+
+ return data;
+}
+
+
+//--------------------------------------------------------------------------
+// i2c_start()
+//
+// This function issues an I2C start command which is a high to low
+// transition on SDA while SCL is high.
+//
+void i2c_start()
+{
+
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+ I2C_SDA_SET;
+ I2C_DELAY;
+}
+
+//--------------------------------------------------------------------------
+// i2c_stop()
+//
+// This function issues an I2C stop command which is a low to high
+// transition on SDA while SCL is high.
+//
+void i2c_stop()
+{
+
+ I2C_SDA_CLR;
+ I2C_DELAY;
+ I2C_SCL_SET;
+ I2C_DELAY;
+ I2C_SDA_SET;
+ I2C_DELAY;
+ I2C_SCL_CLR;
+ I2C_DELAY;
+}
+
+
diff --git a/ports/beagleboneblack/cpuio.c b/ports/beagleboneblack/cpuio.c
new file mode 100644
index 0000000..0a9a262
--- /dev/null
+++ b/ports/beagleboneblack/cpuio.c
@@ -0,0 +1,313 @@
+//=============================================================================
+//
+// cpuio.c
+//
+// CPU/Board Specific IO
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Date: 12/04/2008
+// Description: This file contains the IO functions required by Micro Monitor
+// that are unique to the CSB740
+//
+//
+//=============================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "ether.h"
+#include "stddefs.h"
+#include "warmstart.h"
+#include "omap3530.h"
+#include "omap3530_mem.h"
+#include "cpu_gpio.h"
+#include "fb_draw.h"
+#include "uart16550.h"
+#include "umongpio.h"
+#include "ad7843.h"
+
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+
+extern ulong i2c_init(void);
+extern ulong getpsr(void);
+extern void putpsr(ulong);
+
+uchar bcolor=0; // vga black
+
+/******************************************************
+// Delay for some usecs. - Not accurate, assumes ROM mode
+// and no Cache
+ ******************************************************/
+void udelay(int delay)
+{
+ volatile int i;
+ for ( i = LOOPS_PER_USEC * delay; i ; i--);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WD_WWPS);
+ } while (pending);
+}
+
+/******************************************************
+// getUARTDivisor is called from UART16550.c
+ ******************************************************/
+int
+getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
+{
+ *lo = ((48000000/16)/baud) & 0x00ff;
+ *hi = (((48000000/16)/baud) & 0xff00) >> 8;
+ return(0);
+}
+
+/******************************************************
+// Set pads (pins) to correct mode. Refer to section 7.4.4
+ in TI omap35xx_tech_ref_manual for bit defines.
+ ******************************************************/
+void pads_init()
+{
+ // Set up chip selects
+ SCM_REG(PADCONFS_GPMC_NCS3) = 0x00180018; // NCS3[15:0], NCS4[31:16]
+ SCM_REG(PADCONFS_GPMC_NCS5) = 0x011C0018; // NCS5[15:0], EXP_INTX[31:16]
+
+ // Set LCD_BKL_X to output, pullup enabled, mode 4
+ // Set LCLK to output, no pull-type and disabled, mode 0
+ SCM_REG(PADCONFS_GPMC_NCS7) = 0x0000001C; // LCD_BKL_X[15:0], LCLK(or GPIO_59)[31:16]
+
+ // Set LCD pads to outputs, pull-type = up, pullud disabled, mode 0
+ SCM_REG(PADCONFS_DSS_PCLK) = 0x00100010; // LCD_PCLK_X[15:0], LCD_HS_X[31:16]
+ SCM_REG(PADCONFS_DSS_VSYNC) = 0x00100010; // LCD_VS_X[15:0], LCD_OE_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA0) = 0x00100010; // LCD_B0_X[15:0], LCD_B1_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA2) = 0x00100010; // LCD_B2_X[15:0], LCD_B3_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA4) = 0x00100010; // LCD_B4_X[15:0], LCD_B5_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA6) = 0x00100010; // LCD_G0_X[15:0], LCD_G1_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA8) = 0x00100010; // LCD_G2_X[15:0], LCD_G3_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA10) = 0x00100010; // LCD_G4_X[15:0], LCD_G5_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA12) = 0x00100010; // LCD_R0_X[15:0], LCD_R1_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA14) = 0x00100010; // LCD_R2_X[15:0], LCD_R3_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA16) = 0x00100010; // LCD_R4_X[15:0], LCD_R5_X[31:16]
+
+ // Set D_TXD for output and D_RXD for input. Set both to pullup enabled and mode 1
+ SCM_REG(PADCONFS_MCBSP3_CLKX) = 0x01190019; // D_TXD[15:0], D_RXD[31:16]
+
+#ifdef AD7843_GPIOMODE
+ // Depending on AD7843_GPIOMODE setting, we either configure the SPI
+ // interface to the AD7843 as a real SPI device using the OMAP's SPI
+ // controller, or we set it up with GPIO bits...
+ SCM_REG(PADCONFS_DSS_DATA18) = 0x00040004;
+ SCM_REG(PADCONFS_DSS_DATA20) = 0x00040104;
+#else
+ SCM_REG(PADCONFS_DSS_DATA18) = 0x0002011A; // SPI1_CLK_X[15:0], SPI1_MOSI_X[31:16]
+ SCM_REG(PADCONFS_DSS_DATA20) = 0x001A011A; // SPI1_MISO_X[15:0], *SPI1_CS0_X[31:16]
+#endif
+
+ // Set PIRQ for ADS7843 touch interrupt. Set both to pullup enabled and mode 4
+ SCM_REG(PADCONFS_MMC1_DAT4) = 0x01040104; // *I2C_INT_X[15:0], *PIRQ_X[31:16]
+
+ // GPIO1 is the push button on CSB703(set as input), GPIO0 is is LED on CSB703(set as output)
+ SCM_REG(PADCONFS_MMC1_DAT6) = 0x01040004; // GPIO0_X[15:0], GPIO1_X[31:16]
+
+ // Set E_INT* to be an input in GPIO mode
+ SCM_REG(PADCONFS_GPMC_WAIT2) = 0x011C011f; // NA[15:0], E_INTX[31:16]
+
+ // Set SYS_CLKOUT1 for USB_CLK
+ SCM_REG(PADCONFS_SYS_OFF_MODE) = 0x0000010f; // OFF_MODE_X[15:0], SYS_CLKOUT1[31:16]
+
+ // Set SYS_CLKOUT2 for debug purposes
+ SCM_REG(PADCONFS_SYS_NIRQ) = 0x0000011f; // FIQ[15:0], SYS_CLK2[31:16]
+
+}
+
+int
+devInit(int baud)
+{
+ // Initialize pads
+ pads_init();
+
+ // Disable MPU Watchdog WDT2
+ WD2_REG(WD_WSPR) = 0x0000aaaa;
+ wait_for_command_complete(WD2_BASE_ADD);
+ WD2_REG(WD_WSPR) = 0x00005555;
+
+ // Initialize GPIO
+ GPIO_init();
+
+ // Setup UART pins to UART mode before calling InitUART from uart16550.c
+ UART2_REG(UART_MDR1) = 0x0000;
+ // Initialize the UART
+ InitUART(baud);
+
+ // Setup CS0 for 110ns Spansion Flash
+ GPMC_REG(GPMC_CS0_CONFIG7) = 0x00000c48; // Base addr 0x08000000, 64M
+ GPMC_REG(GPMC_CS0_CONFIG1) = 0x00001210;
+ //GPMC_REG(GPMC_CS0_CONFIG5) = 0x00080808; // Config5
+
+ // Setup CS4 for LAN9211, on the CSB740 it is refered to as CS2
+ // and mapped to E_CS
+ GPMC_REG(GPMC_CS4_CONFIG7) = 0x00000F6C; // Base addr 0x2C000000, 16M
+ GPMC_REG(GPMC_CS4_CONFIG1) = 0x00001200;
+
+ return 0;
+}
+
+/* Referring to table 25-10 of the TRM, install
+ * the RAM exception vectors...
+ */
+void
+ram_vector_install(void)
+{
+ extern unsigned long abort_data;
+ extern unsigned long abort_prefetch;
+ extern unsigned long undefined_instruction;
+ extern unsigned long software_interrupt;
+ extern unsigned long interrupt_request;
+ extern unsigned long fast_interrupt_request;
+ extern unsigned long not_assigned;
+
+ *(ulong **)0x4020ffe4 = &undefined_instruction;
+ *(ulong **)0x4020ffe8 = &software_interrupt;
+ *(ulong **)0x4020ffec = &abort_prefetch;
+ *(ulong **)0x4020fff0 = &abort_data;
+ *(ulong **)0x4020fff4 = ¬_assigned;
+ *(ulong **)0x4020fff8 = &interrupt_request;
+ *(ulong **)0x4020fffc = &fast_interrupt_request;
+}
+
+void
+initCPUio()
+{
+ volatile unsigned register cntens;
+ volatile unsigned register usren;
+ volatile unsigned register pmnc;
+
+ ram_vector_install();
+
+ /* Do this stuff to enable the cycle counter
+ * (for use by target_timer)...
+ */
+ /* Allow user mode to have access to performance monitor registers:
+ */
+ asm volatile (" MRC p15, 0, %0, c9, c14, 0" : "=r" (usren));
+ usren |= 1;
+ asm volatile (" MCR p15, 0, %0, c9, c14, 0" : : "r" (usren));
+
+ /* Enable all counters, and reset Cycle counter...
+ */
+ asm volatile (" MRC p15, 0, %0, c9, c12, 0" : "=r" (pmnc));
+ pmnc |= 5;
+ asm volatile (" MCR p15, 0, %0, c9, c12, 0" : : "r" (pmnc));
+
+ /* Enable all performance counter registers...
+ */
+ asm volatile (" MRC p15, 0, %0, c9, c12, 1" : "=r" (cntens));
+ cntens |= 0x8000000f;
+ asm volatile (" MCR p15, 0, %0, c9, c12, 1" : : "r" (cntens));
+}
+
+/* target_reset():
+ * Set the counter to 16 ticks before trigger, then enable the
+ * watchdog timer (WDT2) and wait...
+ */
+void
+target_reset(void)
+{
+ // Preload the count-up register...
+ WD2_REG(WD_WCRR) = 0xfffffff0;
+
+ // Start MPU Watchdog WDT2
+ WD2_REG(WD_WSPR) = 0x0000bbbb;
+ wait_for_command_complete(WD2_BASE_ADD);
+ WD2_REG(WD_WSPR) = 0x00004444;
+
+ // Now just wait...
+ while(1);
+}
+
+void
+intsrestore(psr)
+ulong psr;
+{
+ putpsr(psr);
+}
+
+/*
+ * Read the program status register (CPSR)
+ * and set the FIQ and IRQ bits.
+ */
+ulong
+intsoff(void)
+{
+ ulong psr;
+
+ psr = getpsr();
+
+ /*
+ * Set bit 6, bit 7 to disable interrupts.
+ */
+ putpsr(psr | 0x000000c0);
+ return(psr);
+}
+
+/* show_revision():
+ * Called when the system banner is printed...
+ */
+void
+show_revision(int center)
+{
+ int (*pfunc)(char *, ...);
+ volatile unsigned register main_id;
+ volatile unsigned register silicon_id;
+
+ if (center)
+ pfunc = cprintf;
+ else
+ pfunc = printf;
+
+ asm(" MRC p15, 0, %0, c0, c0, 0" : "=r" (main_id));
+ asm(" MRC p15, 1, %0, c0, c0, 7" : "=r" (silicon_id));
+
+ pfunc("Silicon ID: %d.%d\n",
+ ((silicon_id & 0xf0)>>4),(silicon_id & 0xf));
+
+ pfunc("CPU Rev: %d, Variant: %d\n",
+ main_id & 0xf,(main_id & 0x00f00000) >> 20);
+
+ pfunc("CM Rev: %d.%d, PRM Rev: %d.%d\n",
+ CM_REV_MAJ(),CM_REV_MIN(),PRM_REV_MAJ(),PRM_REV_MIN());
+}
+
+/* target_timer():
+ * Used in conjunction with INCLUDE_HWTMR and TIMER_TICKS_PER_MSEC
+ * to set up a hardware based time base.
+ */
+unsigned long
+target_timer(void)
+{
+ volatile unsigned register ccr;
+
+ asm(" MRC p15, 0, %0, c9, c13, 0" : "=r" (ccr));
+
+ return(ccr);
+}
+
+/* cacheInitForTarget():
+ Enable instruction cache only...
+*/
+void
+cacheInitForTarget()
+{
+ asm(" MRC p15, 0, r0, c1, c0, 0");
+ asm(" ORR r0, r0, #0x1000"); /* bit 12 is ICACHE enable*/
+ asm(" MCR p15, 0, r0, c1, c0, 0");
+
+ /* Flush instruction cache */
+ asm(" MCR p15, 0, r0, c7, c5, 0");
+}
+
diff --git a/ports/beagleboneblack/cpuio.h b/ports/beagleboneblack/cpuio.h
new file mode 100644
index 0000000..64ff49c
--- /dev/null
+++ b/ports/beagleboneblack/cpuio.h
@@ -0,0 +1,76 @@
+//=============================================================================
+//
+// cpuio.h
+//
+// CPU/Board Specific IO
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Date: 05-16-2008
+// Description: This file contains the IO functions required by Micro Monitor
+// that are unique to each CPU/Board combination
+//
+//
+// cpuio.h for the CSB740 OMAP3530 Cortex-A8
+//
+//=============================================================================
+
+// board specific defines for micro monitor
+#define DEFAULT_BAUD_RATE 38400
+#define MON_CPU_CLOCK 400000000
+
+#define LOOPS_PER_USEC 5
+
+#define BASE_OF_NAND 0x1000
+#define SIZE_OF_NAND 0x100000
+
+// SMSC LAN9211 Ethernet
+#define SMSC911X_BASE_ADDRESS 0x2C000000 // CS4 on OMAP3530 but we call it CS2
+
+// LCD Defines
+//
+// The LCD frame buffer is fixed at 0x80200000, which is 2Mbyte from the
+// beginning of SDRAM space. Note that we access it 16-bits at a time.
+
+#define LCD_BUF_ADD 0x80200000
+#define LCD_BUF(_x_) *(vushort *)(LCD_BUF_ADD + _x_) // Frame Buffer
+#define USE_FONT8X8
+#define LCD_GET_PIXEL_ADD(_X_, _Y_) (((_Y_ * PIXELS_PER_ROW) + _X_)*2)
+
+// defines for the display geometry - OSD043TN24 480x272 TFT
+// (some of these defines are also used by uMon's frame buffer interface)
+#define PIXELS_PER_ROW 480 //
+#define PIXELS_PER_COL 272 //
+#define BITS_PER_PIXEL 16 //
+#define PIXFMT_IS_RGB565 1
+#define FBDEV_SETSTART fbdev_setstart
+#define FRAME_BUFFER_BASE_ADDR LCD_BUF_ADD
+#define LCD_H_WIDTH 41 // pulse width in pixels
+#define LCD_H_FRONT 2 // front porch (sync to enable)
+#define LCD_H_BACK 2 // back porch (enable to sync)
+#define LCD_V_WIDTH 10 // pulse width in lines
+#define LCD_V_FRONT 2 // front porch (sync to enable)
+#define LCD_V_BACK 2 // back porch (enable to sync)
+//#define LCD_PCD 2 // LCD PERCLK3 = 32Mhz/PCD +1 = Pixel Clock ~ 4Mhz
+
+#define TOP 1
+#define BOTTOM (PIXELS_PER_COL-1)
+#define LEFT 0
+#define RIGHT (PIXELS_PER_ROW-1)
+#define CENTER_X (PIXELS_PER_ROW/2)
+#define CENTER_Y (PIXELS_PER_COL/2)
+
+#define ROWS_PER_SCREEN 17
+#define COLS_PER_SCREEN 60
+
+#define LCD_BG_DEF 9
+#define LCD_FG_DEF 15
+
+#define LCD_FB_SIZE(_depth_) (((PIXELS_PER_COL * PIXELS_PER_ROW) * _depth_) / 8)
+
+#define LCD_ROW_SIZE(_depth_) ((PIXELS_PER_ROW * _depth_) / 8)
+
+#define LCD_GET_ADD(_row_, _col_, _depth_) (((((_row_ * PIXELS_PER_ROW) * FONT_HEIGHT) \
+ + (_col_ * FONT_WIDTH)) \
+ * _depth_) / 8)
+
+
diff --git a/ports/beagleboneblack/etherdev.c b/ports/beagleboneblack/etherdev.c
new file mode 100644
index 0000000..690d21b
--- /dev/null
+++ b/ports/beagleboneblack/etherdev.c
@@ -0,0 +1,241 @@
+//=============================================================================
+//
+// etherdev.c
+//
+// Ethernet Abstraction Layer for Micro Monitor
+//
+// Author(s): Michael Kelly, Cogent Computer Systems, Inc.
+// Contributors: Luis Torrico, Cogent Computer Systems, Inc.
+// Date: 05-26-2002
+// Modified: 06-26-2007
+// Description: This file contains the interface layer between Micro Monitor
+// and the Ethernet driver for the LAN921x on the CSB733.
+//
+//=============================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+#include "ether.h"
+
+extern void smsc911x_reset(void);
+extern ushort smsc911x_rx(uchar *pktbuf);
+extern int smsc911x_init(void);
+extern ulong smsc911x_tx(ulong txbuf, ulong length);
+extern void smsc911x_enable_promiscuous_reception(void);
+extern void smsc911x_disable_promiscuous_reception(void);
+extern void smsc911x_enable_multicast_reception(void);
+extern void smsc911x_disable_multicast_reception(void);
+extern void smsc911x_enable_broadcast_reception(void);
+extern void smsc911x_disable_broadcast_reception(void);
+
+ulong tx_buf[400];
+
+#if INCLUDE_ETHERNET
+
+/*
+ * enreset():
+ * Reset the PHY and MAC.
+ */
+void
+enreset(void)
+{
+ smsc911x_reset();
+}
+
+/*
+ * eninit():
+ * This would include establishing buffer descriptor tables and
+ * all the support code that will be used by the ethernet device.
+ *
+ * It can be assumed at this point that the array uchar BinEnetAddr[6]
+ * contains the 6-byte MAC address.
+ *
+ * Return 0 if successful; else -1.
+ */
+int
+eninit(void)
+{
+ return smsc911x_init();
+
+}
+
+int
+EtherdevStartup(int verbose)
+{
+ /* Initialize local device error counts (if any) here. */
+ /* OPT_ADD_CODE_HERE */
+
+ /* Put ethernet controller in reset: */
+ enreset();
+
+ /* Initialize controller: */
+ eninit();
+
+ return(0);
+}
+
+/* disablePromiscuousReception():
+ * Provide the code that disables promiscuous reception.
+ */
+void
+disablePromiscuousReception(void)
+{
+ smsc911x_disable_promiscuous_reception();
+}
+
+/* enablePromiscuousReception():
+ * Provide the code that enables promiscuous reception.
+ */
+void
+enablePromiscuousReception(void)
+{
+ smsc911x_enable_promiscuous_reception();
+}
+
+/* disableBroadcastReception():
+ * Provide the code that disables broadcast reception.
+ */
+void
+disableBroadcastReception(void)
+{
+ smsc911x_disable_broadcast_reception();
+}
+
+/* enableBroadcastReception():
+ * Provide the code that enables broadcast reception.
+ */
+void
+enableBroadcastReception(void)
+{
+ smsc911x_enable_broadcast_reception();
+}
+
+void
+disableMulticastReception(void)
+{
+ smsc911x_disable_multicast_reception();
+}
+
+void
+enableMulticastReception(void)
+{
+ smsc911x_enable_multicast_reception();
+}
+
+
+/*
+ * enselftest():
+ * Run a self test of the ethernet device(s). This can be stubbed
+ * with a return(1).
+ * Return 1 if success; else -1 if failure.
+ */
+int
+enselftest(int verbose)
+{
+ return(1);
+}
+
+/* ShowEtherdevStats():
+ * This function is used to display device-specific stats (error counts
+ * usually).
+ */
+void
+ShowEtherdevStats(void)
+{
+ /* OPT_ADD_CODE_HERE */
+}
+
+/* getXmitBuffer():
+ * Return a pointer to the buffer that is to be used for transmission of
+ * the next packet. Since the monitor's driver is EXTREMELY basic,
+ * there will only be one packet ever being transmitted. No need to queue
+ * up transmit packets.
+ */
+uchar *
+getXmitBuffer(void)
+{
+ return((uchar *) tx_buf);
+}
+
+/* sendBuffer():
+ * Send out the packet assumed to be built in the buffer returned by the
+ * previous call to getXmitBuffer() above.
+ */
+int
+sendBuffer(int length)
+{
+ ulong temp32;
+
+ if (length < 64)
+ length = 64;
+
+ if (EtherVerbose & SHOW_OUTGOING)
+ printPkt((struct ether_header *)tx_buf,length,ETHER_OUTGOING);
+
+ // tell the cs8900a to send the tx buffer pointed to by tx_buf
+ temp32 = smsc911x_tx((ulong)tx_buf, (ulong)length);
+
+ EtherXFRAMECnt++;
+ if (temp32) {
+ return -1;
+ }
+ else {
+ return 0;
+ }
+}
+
+/* DisableEtherdev():
+ * Fine as it is...
+ */
+void
+DisableEtherdev(void)
+{
+ enreset();
+}
+
+/* extGetIpAdd():
+ * If there was some external mechanism (other than just using the
+ * IPADD shell variable established in the monrc file) for retrieval of
+ * the board's IP address, then do it here...
+ */
+char *
+extGetIpAdd(void)
+{
+ return((char *)0);
+}
+
+/* extGetEtherAdd():
+ * If there was some external mechanism (other than just using the
+ * ETHERADD shell variable established in the monrc file) for retrieval of
+ * the board's MAC address, then do it here...
+ */
+char *
+extGetEtherAdd(void)
+{
+ return((char *)0);
+}
+
+/*
+ * polletherdev():
+ * Called continuously by the monitor (ethernet.c) to determine if there
+ * is any incoming ethernet packets.
+ */
+int
+polletherdev(void)
+{
+ ulong pktbuf[RBUFSIZE/4];
+ int pktlen, pktcnt = 0;
+
+ pktlen = smsc911x_rx((uchar *)pktbuf);
+
+ if(pktlen) {
+ pktcnt = 1;
+ EtherRFRAMECnt++;
+ processPACKET((struct ether_header *)pktbuf, pktlen);
+ }
+ return(pktcnt);
+}
+
+#endif
diff --git a/ports/beagleboneblack/fbidemo b/ports/beagleboneblack/fbidemo
new file mode 100644
index 0000000..1a9e21c
--- /dev/null
+++ b/ports/beagleboneblack/fbidemo
@@ -0,0 +1,163 @@
+# This is a useful demo script to show off some of the functionality
+# of uMon's FBI interface...
+# It expects to find two files: fb/splash.bin and fb/umon1 that are
+# assumed to be two frame-buffer formatted images.
+#
+echo "Image file \#1: \c"
+read IMAGEFILE1
+echo "Image file \#2: \c"
+read IMAGEFILE2
+set FBICOLOR 0x005500
+
+fbi font 0 1 1 0xf0f0f0 0x101010
+fbi consolemode off
+fbi fill $IMAGEFILE1
+sleep 2
+
+fbi -t1 color $FBICOLOR
+fbi font 0 4 4 -- transparent
+fbi -o 1,0 print "MicroMonitor"
+fbi font 0 2 2 -- --
+fbi -o 7,3 print "(aka uMon)"
+fbi -o 2,5 print "FBI:"
+fbi -o 2,6 print "Frame Buffer Interface"
+fbi -o 2,7 print "***** Demo *****"
+sleep 2
+
+fbi -t2 color $FBICOLOR
+fbi font 0 1 1 -- --
+fbi -o 5,1 print "print small"
+sleep 1
+fbi font 0 3 3 -- --
+fbi -o 5,1 print "or..."
+sleep 1
+fbi font 0 7 7 -- --
+fbi -o 1,1 print "large"
+sleep 2
+
+fbi -t3 color $FBICOLOR
+fbi font 0 2 4 -- --
+sleep 1
+fbi -o 8,1 print "Independent"
+fbi -o 8,2 print " x & y"
+fbi -o 8,3 print "dimensions..."
+sleep 1
+
+fbi -t1 color $FBICOLOR
+fbi font 0 5 1 -- --
+fbi -o 1,1 print "print wide"
+sleep 1
+fbi font 0 3 3 -- --
+fbi -o 3,3 print "or..."
+sleep 1
+fbi font 0 2 18 -- --
+fbi -o 15,0 print "tall"
+sleep 2
+
+fbi -t2 color $FBICOLOR
+fbi font 0 3 3 -- --
+fbi -o 3,2 print "or"
+sleep 1
+fbi -o 3,4 print "mix it up..."
+sleep 1
+
+fbi -t3 color $FBICOLOR
+fbi font 0 1 1 -- --
+fbi -o 0,1 print 1
+fbi font 0 1 2 -- --
+fbi print 2
+fbi font 0 1 3 -- --
+fbi print 3
+fbi font 0 1 4 -- --
+fbi print 4
+fbi font 0 1 5 -- --
+fbi print 5
+fbi font 0 1 6 -- --
+fbi print 6
+fbi font 0 1 7 -- --
+fbi print 7
+fbi font 0 1 8 -- --
+fbi print 8
+fbi font 0 1 9 -- --
+fbi print 9
+fbi font 0 2 9 -- --
+fbi -o 5,1 print 0
+fbi font 0 2 8 -- --
+fbi -o 6,1 print 9
+fbi font 0 3 7 -- --
+fbi -o 5,1 print 8
+fbi font 0 4 6 -- --
+fbi -o 5,1 print 7
+fbi font 0 5 5 -- --
+fbi -o 5,1 print 6
+fbi font 0 6 4 -- --
+fbi -o 5,1 print 5
+fbi font 0 7 3 -- --
+fbi -o 5,1 print 4
+fbi font 0 8 2 -- --
+fbi -o 5,1 print 3
+fbi font 0 9 1 -- --
+fbi -o 5,1 print 2
+fbi font 0 10 1 -- --
+fbi -o 5,0 print 1
+sleep 4
+
+fbi -t1 color $FBICOLOR
+fbi font 0 3 3 -- --
+fbi -o 3,1 print "or"
+sleep 1
+fbi -o 3,3 print "console mode..."
+fbi -o 3,4 print "(normal font)"
+sleep 2
+
+fbi font 0 1 1 -- --
+fbi consolemode on
+echo uMON\>
+sleep 1
+tfs ls
+echo uMON\>
+sleep 1
+tfs cat monrc
+echo uMON\>
+sleep 1
+fbi consolemode off
+
+fbi -t2 color $FBICOLOR
+fbi font 0 3 3 -- --
+fbi consolemode on
+fbi -o 3,1 print "or"
+sleep 1
+fbi -o 3,3 print "console mode..."
+fbi -o 3,4 print "(taller font)"
+sleep 2
+fbi consolemode off
+
+fbi font 0 1 2 -- --
+fbi consolemode on
+echo uMON\>
+sleep 1
+tfs ls
+echo uMON\>
+sleep 1
+tfs cat monrc
+echo uMON\>
+sleep 1
+fbi font 0 1 1 -- --
+fbi consolemode off
+
+
+# SPLASHLOOPINIT:
+set TTYPE 1
+
+# SPLASHLOOP:
+if $TTYPE gt 3 goto SPLASHLOOPINIT
+if -tgc exit
+fbi -t $TTYPE fill $IMAGEFILE1
+if -tgc exit
+sleep 2
+if -tgc exit
+fbi -t $TTYPE fill $IMAGEFILE2
+set TTYPE=$TTYPE+1
+sleep 2
+if -tgc exit
+goto SPLASHLOOP
diff --git a/ports/beagleboneblack/font8x16.h b/ports/beagleboneblack/font8x16.h
new file mode 100644
index 0000000..808c9e4
--- /dev/null
+++ b/ports/beagleboneblack/font8x16.h
@@ -0,0 +1,3679 @@
+//------------------------------------------------------------------------
+// font8x16.h
+//
+// Simple 8 x 16 font printable characters only. To lookoup, subtract
+// FIRST_CHAR from the character, multiply x FONT_HEIGHT and get the next
+// FONT_WIDTH bytes.
+//
+// 10.03.2003 : added font8x16 def.
+
+#define FONT_WIDTH 8
+#define FONT_HEIGHT 16
+#define FIRST_CHAR 0x20
+#define LAST_CHAR 0x7f
+#define CURSOR_ON 0x7F
+#define CURSOR_OFF 0x20
+
+#if 0
+const uchar fonttbl[] = {
+/* 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 */
+/* 0x20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x21 ! */ 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
+/* 0x22 " */ 0x00, 0x00, 0x48, 0x48, 0x48, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x23 # */ 0x00, 0x00, 0x00, 0x44, 0x44, 0xfe, 0x44, 0x44, 0x44, 0xfe, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00,
+/* 0x24 $ */ 0x00, 0x10, 0x10, 0x7c, 0x92, 0x90, 0x90, 0x7c, 0x12, 0x12, 0x92, 0x7c, 0x10, 0x10, 0x00, 0x00,
+/* 0x25 % */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x94, 0x68, 0x10, 0x2c, 0x52, 0x8c, 0x00, 0x00, 0x00, 0x00,
+/* 0x26 & */ 0x00, 0x00, 0x00, 0x38, 0x44, 0x44, 0x38, 0x56, 0x8c, 0x88, 0x8c, 0x76, 0x00, 0x00, 0x00, 0x00,
+/* 0x27 ' */ 0x00, 0x00, 0x10, 0x10, 0x10, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x28 ( */ 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00,
+/* 0x29 ) */ 0x00, 0x00, 0x00, 0x20, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x20, 0x00, 0x00, 0x00, 0x00,
+/* 0x2a * */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x28, 0xfe, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2b + */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0xfe, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2c , */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x10, 0x20, 0x00, 0x00,
+/* 0x2d - */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x2e . */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
+/* 0x2f / */ 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x30 0 */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x46, 0x4a, 0x52, 0x62, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x31 1 */ 0x00, 0x00, 0x00, 0x08, 0x18, 0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
+/* 0x32 2 */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x02, 0x04, 0x18, 0x20, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x00, 0x00,
+/* 0x33 3 */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x02, 0x02, 0x1c, 0x02, 0x02, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x34 4 */ 0x00, 0x00, 0x00, 0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00,
+/* 0x35 5 */ 0x00, 0x00, 0x00, 0x7e, 0x40, 0x40, 0x7c, 0x02, 0x02, 0x02, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x36 6 */ 0x00, 0x00, 0x00, 0x1c, 0x20, 0x40, 0x40, 0x7c, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x37 7 */ 0x00, 0x00, 0x00, 0x7e, 0x42, 0x02, 0x04, 0x08, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+/* 0x38 8 */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x42, 0x3c, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x39 9 */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x42, 0x3e, 0x02, 0x02, 0x04, 0x38, 0x00, 0x00, 0x00, 0x00,
+/* 0x3a : */ 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3b ; */ 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x30, 0x30, 0x10, 0x20, 0x00, 0x00, 0x00,
+/* 0x3c < */ 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, 0x20, 0x40, 0x20, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00,
+/* 0x3d = */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x3e > */ 0x00, 0x00, 0x00, 0x40, 0x20, 0x10, 0x08, 0x04, 0x08, 0x10, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00,
+/* 0x3f ? */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x04, 0x08, 0x08, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
+/* 0x40 @ */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x4e, 0x52, 0x52, 0x4e, 0x40, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x41 A */ 0x00, 0x00, 0x00, 0x18, 0x24, 0x42, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x42 B */ 0x00, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x42, 0x7c, 0x42, 0x42, 0x42, 0x7c, 0x00, 0x00, 0x00, 0x00,
+/* 0x43 C */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x40, 0x40, 0x40, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x44 D */ 0x00, 0x00, 0x00, 0x78, 0x44, 0x42, 0x42, 0x42, 0x42, 0x42, 0x44, 0x78, 0x00, 0x00, 0x00, 0x00,
+/* 0x45 E */ 0x00, 0x00, 0x00, 0x7e, 0x40, 0x40, 0x40, 0x78, 0x40, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x00, 0x00,
+/* 0x46 F */ 0x00, 0x00, 0x00, 0x7e, 0x40, 0x40, 0x40, 0x78, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+/* 0x47 G */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x40, 0x40, 0x40, 0x4e, 0x42, 0x46, 0x3a, 0x00, 0x00, 0x00, 0x00,
+/* 0x48 H */ 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x7e, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x49 I */ 0x00, 0x00, 0x00, 0x1c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, 0x00,
+/* 0x4a J */ 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x4b K */ 0x00, 0x00, 0x00, 0x42, 0x42, 0x44, 0x48, 0x70, 0x48, 0x44, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x4c L */ 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x00, 0x00,
+/* 0x4d M */ 0x00, 0x00, 0x00, 0x82, 0xc6, 0xaa, 0x92, 0x92, 0x82, 0x82, 0x82, 0x82, 0x00, 0x00, 0x00, 0x00,
+/* 0x4e N */ 0x00, 0x00, 0x00, 0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x4f O */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x50 P */ 0x00, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x42, 0x7c, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+/* 0x51 Q */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x42, 0x42, 0x42, 0x4a, 0x4a, 0x3c, 0x04, 0x06, 0x00, 0x00,
+/* 0x52 R */ 0x00, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x42, 0x7c, 0x44, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x53 S */ 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x20, 0x18, 0x04, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x54 T */ 0x00, 0x00, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+/* 0x55 U */ 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x56 V */ 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, 0x00, 0x00, 0x00, 0x00,
+/* 0x57 W */ 0x00, 0x00, 0x00, 0x82, 0x82, 0x82, 0x82, 0x92, 0x92, 0xba, 0x6c, 0x44, 0x00, 0x00, 0x00, 0x00,
+/* 0x58 X */ 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x24, 0x18, 0x24, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x59 Y */ 0x00, 0x00, 0x00, 0x82, 0x82, 0x82, 0x44, 0x38, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+/* 0x5a Z */ 0x00, 0x00, 0x00, 0x7e, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x40, 0x7e, 0x00, 0x00, 0x00, 0x00,
+/* 0x5b [ */ 0x00, 0x00, 0x00, 0x3c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x5c \ */ 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5d ] */ 0x00, 0x00, 0x00, 0x3c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x5e ^ */ 0x00, 0x10, 0x28, 0x44, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x5f _ */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
+/* 0x60 ` */ 0x00, 0x00, 0x10, 0x10, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x61 a */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x3e, 0x42, 0x42, 0x3e, 0x00, 0x00, 0x00, 0x00,
+/* 0x62 b */ 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x7c, 0x42, 0x42, 0x42, 0x42, 0x7c, 0x00, 0x00, 0x00, 0x00,
+/* 0x63 c */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x42, 0x40, 0x40, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x64 d */ 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x3e, 0x42, 0x42, 0x42, 0x42, 0x3e, 0x00, 0x00, 0x00, 0x00,
+/* 0x65 e */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x42, 0x7e, 0x40, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x66 f */ 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x20, 0x78, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00,
+/* 0x67 g */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x42, 0x42, 0x42, 0x3e, 0x02, 0x42, 0x3c, 0x00, 0x00,
+/* 0x68 h */ 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x5c, 0x62, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x69 i */ 0x00, 0x00, 0x00, 0x08, 0x08, 0x00, 0x18, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, 0x00,
+/* 0x6a j */ 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x22, 0x22, 0x1c, 0x00, 0x00,
+/* 0x6b k */ 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x42, 0x44, 0x78, 0x44, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x6c l */ 0x00, 0x00, 0x00, 0x18, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, 0x00,
+/* 0x6d m */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0xee, 0x92, 0x92, 0x92, 0x82, 0x00, 0x00, 0x00, 0x00,
+/* 0x6e n */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x62, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x6f o */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x42, 0x42, 0x42, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x70 p */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x42, 0x42, 0x42, 0x7c, 0x40, 0x40, 0x40, 0x00, 0x00,
+/* 0x71 q */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x42, 0x42, 0x42, 0x3e, 0x02, 0x02, 0x03, 0x00, 0x00,
+/* 0x72 r */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5c, 0x62, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+/* 0x73 s */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x42, 0x38, 0x04, 0x42, 0x3c, 0x00, 0x00, 0x00, 0x00,
+/* 0x74 t */ 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x10, 0x10, 0x0c, 0x00, 0x00, 0x00, 0x00,
+/* 0x75 u */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x46, 0x3a, 0x00, 0x00, 0x00, 0x00,
+/* 0x76 v */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x14, 0x08, 0x00, 0x00, 0x00, 0x00,
+/* 0x77 w */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x92, 0x92, 0xba, 0x6c, 0x44, 0x00, 0x00, 0x00, 0x00,
+/* 0x78 x */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x24, 0x18, 0x18, 0x24, 0x42, 0x00, 0x00, 0x00, 0x00,
+/* 0x79 y */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x42, 0x42, 0x42, 0x3e, 0x02, 0x04, 0x78, 0x00, 0x00,
+/* 0x7a z */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x04, 0x08, 0x10, 0x20, 0x7e, 0x00, 0x00, 0x00, 0x00,
+/* 0x7b { */ 0x00, 0x00, 0x00, 0x06, 0x08, 0x08, 0x08, 0x30, 0x08, 0x08, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00,
+/* 0x7c | */ 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+/* 0x7d } */ 0x00, 0x00, 0x00, 0x60, 0x10, 0x10, 0x10, 0x0c, 0x10, 0x10, 0x10, 0x60, 0x00, 0x00, 0x00, 0x00,
+/* 0x7e ~ */ 0x00, 0x00, 0x00, 0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 0x7f */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x28, 0x44, 0x82, 0x82, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+#else
+
+const uchar fonttbl[] = {
+
+
+/* Character (0x20):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ! (0x21):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | **** |
+ | **** |
+ | **** |
+ | **** |
+ | ** |
+ | ** |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x3c,
+0x3c,
+0x3c,
+0x3c,
+0x18,
+0x18,
+0x00,
+0x18,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character " (0x22):
+ ht=16, width=8
+ +--------+
+ | |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | * * |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x36,
+0x36,
+0x36,
+0x36,
+0x14,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character # (0x23):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |******* |
+ | ** ** |
+ | ** ** |
+ |******* |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x6c,
+0x6c,
+0x6c,
+0xfe,
+0x6c,
+0x6c,
+0xfe,
+0x6c,
+0x6c,
+0x6c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character $ (0x24):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ***** |
+ |** ** |
+ |** |
+ | **** |
+ | **** |
+ | ** |
+ |** ** |
+ | ***** |
+ | ** |
+ | ** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x18,
+0x7c,
+0xc6,
+0xc0,
+0x78,
+0x3c,
+0x06,
+0xc6,
+0x7c,
+0x18,
+0x18,
+0x00,
+0x00,
+
+/* Character % (0x25):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** * |
+ | ** ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x62,
+0x66,
+0x0c,
+0x18,
+0x30,
+0x66,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character & (0x26):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** ** |
+ | *** |
+ | ** |
+ | *** ** |
+ | ****** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | *** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x38,
+0x6c,
+0x38,
+0x30,
+0x76,
+0x7e,
+0xcc,
+0xcc,
+0xcc,
+0x76,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ' (0x27):
+ ht=16, width=8
+ +--------+
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x0c,
+0x0c,
+0x0c,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ( (0x28):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x0c,
+0x18,
+0x30,
+0x30,
+0x30,
+0x30,
+0x30,
+0x30,
+0x18,
+0x0c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ) (0x29):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x30,
+0x18,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x18,
+0x30,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character * (0x2a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** ** |
+ | *** |
+ |******* |
+ | *** |
+ | ** ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x6c,
+0x38,
+0xfe,
+0x38,
+0x6c,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character + (0x2b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | ****** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x18,
+0x18,
+0x7e,
+0x18,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character , (0x2c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x0c,
+0x18,
+0x00,
+0x00,
+0x00,
+
+/* Character - (0x2d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character . (0x2e):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x18,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character / (0x2f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | * |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** |
+ |* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x02,
+0x06,
+0x0c,
+0x18,
+0x30,
+0x60,
+0xc0,
+0x80,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 0 (0x30):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** *** |
+ |** **** |
+ |**** ** |
+ |*** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xce,
+0xde,
+0xf6,
+0xe6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 1 (0x31):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | **** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ****** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x78,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x7e,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 2 (0x32):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** ** |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0x06,
+0x0c,
+0x18,
+0x30,
+0x60,
+0xc6,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 3 (0x33):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ | ** |
+ | ** |
+ | **** |
+ | ** |
+ | ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0x06,
+0x06,
+0x3c,
+0x06,
+0x06,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 4 (0x34):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | *** |
+ | **** |
+ | ** ** |
+ |** ** |
+ |** ** |
+ |******* |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x0c,
+0x1c,
+0x3c,
+0x6c,
+0xcc,
+0xcc,
+0xfe,
+0x0c,
+0x0c,
+0x1e,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 5 (0x35):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |******* |
+ |** |
+ |** |
+ |** |
+ |****** |
+ | ** |
+ | ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfe,
+0xc0,
+0xc0,
+0xc0,
+0xfc,
+0x06,
+0x06,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 6 (0x36):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** |
+ |** |
+ |****** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc0,
+0xc0,
+0xfc,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 7 (0x37):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |******* |
+ |** ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfe,
+0xc6,
+0x06,
+0x0c,
+0x18,
+0x30,
+0x30,
+0x30,
+0x30,
+0x30,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 8 (0x38):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character 9 (0x39):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ****** |
+ | ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7e,
+0x06,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character : (0x3a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ; (0x3b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x0c,
+0x18,
+0x00,
+0x00,
+0x00,
+
+/* Character < (0x3c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x0c,
+0x18,
+0x30,
+0x60,
+0xc0,
+0x60,
+0x30,
+0x18,
+0x0c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character = (0x3d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ |******* |
+ | |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xfe,
+0x00,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character > (0x3e):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x60,
+0x30,
+0x18,
+0x0c,
+0x06,
+0x0c,
+0x18,
+0x30,
+0x60,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ? (0x3f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0x0c,
+0x18,
+0x18,
+0x18,
+0x00,
+0x18,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character @ (0x40):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** **** |
+ |** **** |
+ |** **** |
+ |** *** |
+ |** |
+ | ****** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xde,
+0xde,
+0xde,
+0xdc,
+0xc0,
+0x7e,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character A (0x41):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |******* |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x38,
+0x6c,
+0xc6,
+0xc6,
+0xc6,
+0xfe,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character B (0x42):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |****** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ***** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |****** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfc,
+0x66,
+0x66,
+0x66,
+0x7c,
+0x66,
+0x66,
+0x66,
+0x66,
+0xfc,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character C (0x43):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | **** |
+ | ** ** |
+ |** * |
+ |** |
+ |** |
+ |** |
+ |** |
+ |** * |
+ | ** ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x3c,
+0x66,
+0xc2,
+0xc0,
+0xc0,
+0xc0,
+0xc0,
+0xc2,
+0x66,
+0x3c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character D (0x44):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |***** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xf8,
+0x6c,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0x6c,
+0xf8,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character E (0x45):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |******* |
+ | ** ** |
+ | ** |
+ | ** * |
+ | ***** |
+ | ** * |
+ | ** |
+ | ** |
+ | ** ** |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfe,
+0x66,
+0x60,
+0x64,
+0x7c,
+0x64,
+0x60,
+0x60,
+0x66,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character F (0x46):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |******* |
+ | ** ** |
+ | ** |
+ | ** * |
+ | ***** |
+ | ** * |
+ | ** |
+ | ** |
+ | ** |
+ |**** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfe,
+0x66,
+0x60,
+0x64,
+0x7c,
+0x64,
+0x60,
+0x60,
+0x60,
+0xf0,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character G (0x47):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** |
+ |** |
+ |** |
+ |** *** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc0,
+0xc0,
+0xc0,
+0xce,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character H (0x48):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |******* |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xfe,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character I (0x49):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | **** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x3c,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x3c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character J (0x4a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | **** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** ** |
+ |** ** |
+ | *** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x3c,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0xd8,
+0xd8,
+0x70,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character K (0x4b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |**** |
+ |**** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xcc,
+0xd8,
+0xf0,
+0xf0,
+0xd8,
+0xcc,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character L (0x4c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |**** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** * |
+ | ** ** |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xf0,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x62,
+0x66,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character M (0x4d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |*** *** |
+ |*** *** |
+ |******* |
+ |** * ** |
+ |** * ** |
+ |** * ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xee,
+0xee,
+0xfe,
+0xd6,
+0xd6,
+0xd6,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character N (0x4e):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |*** ** |
+ |*** ** |
+ |**** ** |
+ |** **** |
+ |** *** |
+ |** *** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xe6,
+0xe6,
+0xf6,
+0xde,
+0xce,
+0xce,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character O (0x4f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character P (0x50):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |****** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ***** |
+ | ** |
+ | ** |
+ | ** |
+ |**** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfc,
+0x66,
+0x66,
+0x66,
+0x66,
+0x7c,
+0x60,
+0x60,
+0x60,
+0xf0,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character Q (0x51):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** * ** |
+ |** * ** |
+ | ***** |
+ | ** |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xd6,
+0xd6,
+0x7c,
+0x06,
+0x00,
+0x00,
+0x00,
+
+/* Character R (0x52):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |****** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ***** |
+ | **** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |*** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfc,
+0x66,
+0x66,
+0x66,
+0x7c,
+0x78,
+0x6c,
+0x66,
+0x66,
+0xe6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character S (0x53):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** |
+ |** |
+ | *** |
+ | *** |
+ | ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc0,
+0xc0,
+0x70,
+0x1c,
+0x06,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character T (0x54):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ****** |
+ | * ** * |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7e,
+0x5a,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x3c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character U (0x55):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character V (0x56):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ** ** |
+ | *** |
+ | * |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x6c,
+0x38,
+0x10,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character W (0x57):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** * ** |
+ |** * ** |
+ |** * ** |
+ |******* |
+ |*** *** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xd6,
+0xd6,
+0xd6,
+0xfe,
+0xee,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character X (0x58):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ** ** |
+ | *** |
+ | *** |
+ | ** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0x6c,
+0x38,
+0x38,
+0x6c,
+0xc6,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character Y (0x59):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | **** |
+ | ** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0x3c,
+0x18,
+0x18,
+0x18,
+0x3c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character Z (0x5a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |******* |
+ |** ** |
+ |* ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** * |
+ |** ** |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xfe,
+0xc6,
+0x86,
+0x0c,
+0x18,
+0x30,
+0x60,
+0xc2,
+0xc6,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character [ (0x5b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x60,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character \ (0x5c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ |* |
+ |** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | * |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x80,
+0xc0,
+0x60,
+0x30,
+0x18,
+0x0c,
+0x06,
+0x02,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ] (0x5d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ***** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x7c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ^ (0x5e):
+ ht=16, width=8
+ +--------+
+ | |
+ | * |
+ | *** |
+ | ** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x10,
+0x38,
+0x6c,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character _ (0x5f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ |********|
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xff,
+0x00,
+0x00,
+
+/* Character ` (0x60):
+ ht=16, width=8
+ +--------+
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x18,
+0x18,
+0x18,
+0x0c,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character a (0x61):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | **** |
+ | ** |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** *** |
+ | *** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x78,
+0x0c,
+0x7c,
+0xcc,
+0xcc,
+0xdc,
+0x76,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character b (0x62):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |*** |
+ | ** |
+ | ** |
+ | ***** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |****** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xe0,
+0x60,
+0x60,
+0x7c,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0xfc,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character c (0x63):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** |
+ |** |
+ |** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc0,
+0xc0,
+0xc0,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character d (0x64):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** |
+ | ** |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ****** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x1c,
+0x0c,
+0x0c,
+0x7c,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0x7e,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character e (0x65):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |******* |
+ |** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xfe,
+0xc0,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character f (0x66):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** ** |
+ | ** |
+ | ** |
+ |****** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x1c,
+0x36,
+0x30,
+0x30,
+0xfc,
+0x30,
+0x30,
+0x30,
+0x30,
+0x78,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character g (0x67):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | *** ** |
+ |** *** |
+ |** ** |
+ |** ** |
+ |** *** |
+ | *** ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x76,
+0xce,
+0xc6,
+0xc6,
+0xce,
+0x76,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+
+/* Character h (0x68):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |*** |
+ | ** |
+ | ** |
+ | ***** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ |*** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xe0,
+0x60,
+0x60,
+0x7c,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0xe6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character i (0x69):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x18,
+0x00,
+0x38,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x3c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character j (0x6a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |** ** |
+ |** ** |
+ | **** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x0c,
+0x0c,
+0x00,
+0x1c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0x0c,
+0xcc,
+0xcc,
+0x78,
+0x00,
+0x00,
+
+/* Character k (0x6b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ |*** |
+ | ** |
+ | ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | **** |
+ | ** ** |
+ | ** ** |
+ |*** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0xe0,
+0x60,
+0x60,
+0x66,
+0x66,
+0x6c,
+0x78,
+0x6c,
+0x66,
+0xe6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character l (0x6c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | *** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x1c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character m (0x6d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ** ** |
+ |******* |
+ |** * ** |
+ |** * ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x6c,
+0xfe,
+0xd6,
+0xd6,
+0xc6,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character n (0x6e):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** *** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xdc,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0x66,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character o (0x6f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character p (0x70):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** *** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ** ** |
+ | ***** |
+ | ** |
+ | ** |
+ |**** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xdc,
+0x66,
+0x66,
+0x66,
+0x66,
+0x7c,
+0x60,
+0x60,
+0xf0,
+0x00,
+0x00,
+
+/* Character q (0x71):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | *** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ***** |
+ | ** |
+ | ** |
+ | **** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x76,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0x7c,
+0x0c,
+0x0c,
+0x1e,
+0x00,
+0x00,
+
+/* Character r (0x72):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** *** |
+ | ** ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ |**** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xdc,
+0x66,
+0x60,
+0x60,
+0x60,
+0x60,
+0xf0,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character s (0x73):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | ***** |
+ |** ** |
+ |** |
+ | ***** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x7c,
+0xc6,
+0xc0,
+0x7c,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character t (0x74):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ |****** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** ** |
+ | *** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x30,
+0x30,
+0x30,
+0xfc,
+0x30,
+0x30,
+0x30,
+0x30,
+0x36,
+0x1c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character u (0x75):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | *** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0xcc,
+0x76,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character v (0x76):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ | ** ** |
+ | *** |
+ | * |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0x6c,
+0x38,
+0x10,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character w (0x77):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** * ** |
+ |** * ** |
+ |** * ** |
+ |******* |
+ | ** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xd6,
+0xd6,
+0xd6,
+0xfe,
+0x6c,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character x (0x78):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** ** |
+ |** ** |
+ | ** ** |
+ | *** |
+ | ** ** |
+ |** ** |
+ |** ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xc6,
+0xc6,
+0x6c,
+0x38,
+0x6c,
+0xc6,
+0xc6,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character y (0x79):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** ** |
+ |** *** |
+ | *** ** |
+ | ** |
+ |** ** |
+ | ***** |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xc6,
+0xc6,
+0xc6,
+0xc6,
+0xce,
+0x76,
+0x06,
+0xc6,
+0x7c,
+0x00,
+0x00,
+
+/* Character z (0x7a):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ |******* |
+ |* ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** * |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0xfe,
+0x86,
+0x0c,
+0x18,
+0x30,
+0x62,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character { (0x7b):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | *** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x0e,
+0x18,
+0x18,
+0x18,
+0x70,
+0x18,
+0x18,
+0x18,
+0x18,
+0x0e,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character | (0x7c):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x18,
+0x18,
+0x18,
+0x18,
+0x00,
+0x18,
+0x18,
+0x18,
+0x18,
+0x18,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character } (0x7d):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | *** |
+ | ** |
+ | ** |
+ | ** |
+ | ** |
+ | *** |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x70,
+0x18,
+0x18,
+0x18,
+0x0e,
+0x18,
+0x18,
+0x18,
+0x18,
+0x70,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character ~ (0x7e):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | *** ** |
+ |** *** |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x76,
+0xdc,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+/* Character (0x7f):
+ ht=16, width=8
+ +--------+
+ | |
+ | |
+ | |
+ | |
+ | |
+ | * |
+ | *** |
+ | *** |
+ | ** ** |
+ | ** ** |
+ |******* |
+ | |
+ | |
+ | |
+ | |
+ | |
+ +--------+ */
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x10,
+0x38,
+0x38,
+0x6c,
+0x6c,
+0xfe,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+};
+
+#endif
+
+//#define font8x16 fonttbl
diff --git a/ports/beagleboneblack/gdbregs.c b/ports/beagleboneblack/gdbregs.c
new file mode 100644
index 0000000..7930f9c
--- /dev/null
+++ b/ports/beagleboneblack/gdbregs.c
@@ -0,0 +1 @@
+#include "gdbregs_arm.c"
diff --git a/ports/beagleboneblack/lcd_lut.h b/ports/beagleboneblack/lcd_lut.h
new file mode 100644
index 0000000..9b074f6
--- /dev/null
+++ b/ports/beagleboneblack/lcd_lut.h
@@ -0,0 +1,289 @@
+//------------------------------------------------------------------------
+// lcd_lut.h: Lookup Table Values
+//
+
+uchar lcd_lut[256][3] = {
+// RED, GREEN, BLUE // Entry
+ { 0x0, 0x0, 0x0, }, // 00
+ { 0x0, 0x0, 0xA, }, // 01
+ { 0x0, 0xA, 0x0, }, // 02
+ { 0x0, 0xA, 0xA, }, // 03
+ { 0xA, 0x0, 0x0, }, // 04
+ { 0xA, 0x0, 0xA, }, // 05
+ { 0xA, 0xA, 0x0, }, // 06
+ { 0xA, 0xA, 0xA, }, // 07
+ { 0x5, 0x5, 0x5, }, // 08
+ { 0x5, 0x5, 0xF, }, // 09
+ { 0x5, 0xF, 0x5, }, // 0A
+ { 0x5, 0xF, 0xF, }, // 0B
+ { 0xF, 0x5, 0x5, }, // 0C
+ { 0xF, 0x5, 0xF, }, // 0D
+ { 0xF, 0xF, 0x5, }, // 0E
+ { 0xF, 0xF, 0xF, }, // 0F
+ { 0x0, 0x0, 0x0, }, // 10
+ { 0x1, 0x1, 0x1, }, // 11
+ { 0x2, 0x2, 0x2, }, // 12
+ { 0x2, 0x2, 0x2, }, // 13
+ { 0x3, 0x3, 0x3, }, // 14
+ { 0x4, 0x4, 0x4, }, // 15
+ { 0x5, 0x5, 0x5, }, // 16
+ { 0x6, 0x6, 0x6, }, // 17
+ { 0x7, 0x7, 0x7, }, // 18
+ { 0x8, 0x8, 0x8, }, // 19
+ { 0x9, 0x9, 0x9, }, // 1A
+ { 0xA, 0xA, 0xA, }, // 1B
+ { 0xB, 0xB, 0xB, }, // 1C
+ { 0xC, 0xC, 0xC, }, // 1D
+ { 0xE, 0xE, 0xE, }, // 1E
+ { 0xF, 0xF, 0xF, }, // 1F
+ { 0x0, 0x0, 0xF, }, // 20
+ { 0x4, 0x0, 0xF, }, // 21
+ { 0x7, 0x0, 0xF, }, // 22
+ { 0xB, 0x0, 0xF, }, // 23
+ { 0xF, 0x0, 0xF, }, // 24
+ { 0xF, 0x0, 0xB, }, // 25
+ { 0xF, 0x0, 0x7, }, // 26
+ { 0xF, 0x0, 0x4, }, // 27
+ { 0xF, 0x0, 0x0, }, // 28
+ { 0xF, 0x4, 0x0, }, // 29
+ { 0xF, 0x7, 0x0, }, // 2A
+ { 0xF, 0xB, 0x0, }, // 2B
+ { 0xF, 0xF, 0x0, }, // 2C
+ { 0xB, 0xF, 0x0, }, // 2D
+ { 0x7, 0xF, 0x0, }, // 2E
+ { 0x4, 0xF, 0x0, }, // 2F
+ { 0x0, 0xF, 0x0, }, // 30
+ { 0x0, 0xF, 0x4, }, // 31
+ { 0x0, 0xF, 0x7, }, // 32
+ { 0x0, 0xF, 0xB, }, // 33
+ { 0x0, 0xF, 0xF, }, // 34
+ { 0x0, 0xB, 0xF, }, // 35
+ { 0x0, 0x7, 0xF, }, // 36
+ { 0x0, 0x4, 0xF, }, // 37
+ { 0x7, 0x7, 0xF, }, // 38
+ { 0x9, 0x7, 0xF, }, // 39
+ { 0xB, 0x7, 0xF, }, // 3A
+ { 0xD, 0x7, 0xF, }, // 3B
+ { 0xF, 0x7, 0xF, }, // 3C
+ { 0xF, 0x7, 0xD, }, // 3D
+ { 0xF, 0x7, 0xB, }, // 3E
+ { 0xF, 0x7, 0x9, }, // 3F
+ { 0xF, 0x7, 0x7, }, // 40
+ { 0xF, 0x9, 0x7, }, // 41
+ { 0xF, 0xB, 0x7, }, // 42
+ { 0xF, 0xD, 0x7, }, // 43
+ { 0xF, 0xF, 0x7, }, // 44
+ { 0xD, 0xF, 0x7, }, // 45
+ { 0xB, 0xF, 0x7, }, // 46
+ { 0x9, 0xF, 0x7, }, // 47
+ { 0x7, 0xF, 0x7, }, // 48
+ { 0x7, 0xF, 0x9, }, // 49
+ { 0x7, 0xF, 0xB, }, // 4A
+ { 0x7, 0xF, 0xD, }, // 4B
+ { 0x7, 0xF, 0xF, }, // 4C
+ { 0x7, 0xD, 0xF, }, // 4D
+ { 0x7, 0xB, 0xF, }, // 4E
+ { 0x7, 0x9, 0xF, }, // 4F
+ { 0xB, 0xB, 0xF, }, // 50
+ { 0xC, 0xB, 0xF, }, // 51
+ { 0xD, 0xB, 0xF, }, // 52
+ { 0xE, 0xB, 0xF, }, // 53
+ { 0xF, 0xB, 0xF, }, // 54
+ { 0xF, 0xB, 0xE, }, // 55
+ { 0xF, 0xB, 0xD, }, // 56
+ { 0xF, 0xB, 0xC, }, // 57
+ { 0xF, 0xB, 0xB, }, // 58
+ { 0xF, 0xC, 0xB, }, // 59
+ { 0xF, 0xD, 0xB, }, // 5A
+ { 0xF, 0xE, 0xB, }, // 5B
+ { 0xF, 0xF, 0xB, }, // 5C
+ { 0xE, 0xF, 0xB, }, // 5D
+ { 0xD, 0xF, 0xB, }, // 5E
+ { 0xC, 0xF, 0xB, }, // 5F
+ { 0xB, 0xF, 0xB, }, // 60
+ { 0xB, 0xF, 0xC, }, // 61
+ { 0xB, 0xF, 0xD, }, // 62
+ { 0xB, 0xF, 0xE, }, // 63
+ { 0xB, 0xF, 0xF, }, // 64
+ { 0xB, 0xE, 0xF, }, // 65
+ { 0xB, 0xD, 0xF, }, // 66
+ { 0xB, 0xC, 0xF, }, // 67
+ { 0x0, 0x0, 0x7, }, // 68
+ { 0x1, 0x0, 0x7, }, // 69
+ { 0x3, 0x0, 0x7, }, // 6A
+ { 0x5, 0x0, 0x7, }, // 6B
+ { 0x7, 0x0, 0x7, }, // 6C
+ { 0x7, 0x0, 0x5, }, // 6D
+ { 0x7, 0x0, 0x3, }, // 6E
+ { 0x7, 0x0, 0x1, }, // 6F
+ { 0x7, 0x0, 0x0, }, // 70
+ { 0x7, 0x1, 0x0, }, // 71
+ { 0x7, 0x3, 0x0, }, // 72
+ { 0x7, 0x5, 0x0, }, // 73
+ { 0x7, 0x7, 0x0, }, // 74
+ { 0x5, 0x7, 0x0, }, // 75
+ { 0x3, 0x7, 0x0, }, // 76
+ { 0x1, 0x7, 0x0, }, // 77
+ { 0x0, 0x7, 0x0, }, // 78
+ { 0x0, 0x7, 0x1, }, // 79
+ { 0x0, 0x7, 0x3, }, // 7A
+ { 0x0, 0x7, 0x5, }, // 7B
+ { 0x0, 0x7, 0x7, }, // 7C
+ { 0x0, 0x5, 0x7, }, // 7D
+ { 0x0, 0x3, 0x7, }, // 7E
+ { 0x0, 0x1, 0x7, }, // 7F
+ { 0x3, 0x3, 0x7, }, // 80
+ { 0x4, 0x3, 0x7, }, // 81
+ { 0x5, 0x3, 0x7, }, // 82
+ { 0x6, 0x3, 0x7, }, // 83
+ { 0x7, 0x3, 0x7, }, // 84
+ { 0x7, 0x3, 0x6, }, // 85
+ { 0x7, 0x3, 0x5, }, // 86
+ { 0x7, 0x3, 0x4, }, // 87
+ { 0x7, 0x3, 0x3, }, // 88
+ { 0x7, 0x4, 0x3, }, // 89
+ { 0x7, 0x5, 0x3, }, // 8A
+ { 0x7, 0x6, 0x3, }, // 8B
+ { 0x7, 0x7, 0x3, }, // 8C
+ { 0x6, 0x7, 0x3, }, // 8D
+ { 0x5, 0x7, 0x3, }, // 8E
+ { 0x4, 0x7, 0x3, }, // 8F
+ { 0x3, 0x7, 0x3, }, // 90
+ { 0x3, 0x7, 0x4, }, // 91
+ { 0x3, 0x7, 0x5, }, // 92
+ { 0x3, 0x7, 0x6, }, // 93
+ { 0x3, 0x7, 0x7, }, // 94
+ { 0x3, 0x6, 0x7, }, // 95
+ { 0x3, 0x5, 0x7, }, // 96
+ { 0x3, 0x4, 0x7, }, // 97
+ { 0x5, 0x5, 0x7, }, // 98
+ { 0x5, 0x5, 0x7, }, // 99
+ { 0x6, 0x5, 0x7, }, // 9A
+ { 0x6, 0x5, 0x7, }, // 9B
+ { 0x7, 0x5, 0x7, }, // 9C
+ { 0x7, 0x5, 0x6, }, // 9D
+ { 0x7, 0x5, 0x6, }, // 9E
+ { 0x7, 0x5, 0x5, }, // 9F
+ { 0x7, 0x5, 0x5, }, // A0
+ { 0x7, 0x5, 0x5, }, // A1
+ { 0x7, 0x6, 0x5, }, // A2
+ { 0x7, 0x6, 0x5, }, // A3
+ { 0x7, 0x7, 0x5, }, // A4
+ { 0x6, 0x7, 0x5, }, // A5
+ { 0x6, 0x7, 0x5, }, // A6
+ { 0x5, 0x7, 0x5, }, // A7
+ { 0x5, 0x7, 0x5, }, // A8
+ { 0x5, 0x7, 0x5, }, // A9
+ { 0x5, 0x7, 0x6, }, // AA
+ { 0x5, 0x7, 0x6, }, // AB
+ { 0x5, 0x7, 0x7, }, // AC
+ { 0x5, 0x6, 0x7, }, // AD
+ { 0x5, 0x6, 0x7, }, // AE
+ { 0x5, 0x5, 0x7, }, // AF
+ { 0x0, 0x0, 0x4, }, // B0
+ { 0x1, 0x0, 0x4, }, // B1
+ { 0x2, 0x0, 0x4, }, // B2
+ { 0x3, 0x0, 0x4, }, // B3
+ { 0x4, 0x0, 0x4, }, // B4
+ { 0x4, 0x0, 0x3, }, // B5
+ { 0x4, 0x0, 0x2, }, // B6
+ { 0x4, 0x0, 0x1, }, // B7
+ { 0x4, 0x0, 0x0, }, // B8
+ { 0x4, 0x1, 0x0, }, // B9
+ { 0x4, 0x2, 0x0, }, // BA
+ { 0x4, 0x3, 0x0, }, // BB
+ { 0x4, 0x4, 0x0, }, // BC
+ { 0x3, 0x4, 0x0, }, // BD
+ { 0x2, 0x4, 0x0, }, // BE
+ { 0x1, 0x4, 0x0, }, // BF
+ { 0x0, 0x4, 0x0, }, // C0
+ { 0x0, 0x4, 0x1, }, // C1
+ { 0x0, 0x4, 0x2, }, // C2
+ { 0x0, 0x4, 0x3, }, // C3
+ { 0x0, 0x4, 0x4, }, // C4
+ { 0x0, 0x3, 0x4, }, // C5
+ { 0x0, 0x2, 0x4, }, // C6
+ { 0x0, 0x1, 0x4, }, // C7
+ { 0x2, 0x2, 0x4, }, // C8
+ { 0x2, 0x2, 0x4, }, // C9
+ { 0x3, 0x2, 0x4, }, // CA
+ { 0x3, 0x2, 0x4, }, // CB
+ { 0x4, 0x2, 0x4, }, // CC
+ { 0x4, 0x2, 0x3, }, // CD
+ { 0x4, 0x2, 0x3, }, // CE
+ { 0x4, 0x2, 0x2, }, // CF
+ { 0x4, 0x2, 0x2, }, // D0
+ { 0x4, 0x2, 0x2, }, // D1
+ { 0x4, 0x3, 0x2, }, // D2
+ { 0x4, 0x3, 0x2, }, // D3
+ { 0x4, 0x4, 0x2, }, // D4
+ { 0x3, 0x4, 0x2, }, // D5
+ { 0x3, 0x4, 0x2, }, // D6
+ { 0x2, 0x4, 0x2, }, // D7
+ { 0x2, 0x4, 0x2, }, // D8
+ { 0x2, 0x4, 0x2, }, // D9
+ { 0x2, 0x4, 0x3, }, // DA
+ { 0x2, 0x4, 0x3, }, // DB
+ { 0x2, 0x4, 0x4, }, // DC
+ { 0x2, 0x3, 0x4, }, // DD
+ { 0x2, 0x3, 0x4, }, // DE
+ { 0x2, 0x2, 0x4, }, // DF
+ { 0x2, 0x2, 0x4, }, // E0
+ { 0x3, 0x2, 0x4, }, // E1
+ { 0x3, 0x2, 0x4, }, // E2
+ { 0x3, 0x2, 0x4, }, // E3
+ { 0x4, 0x2, 0x4, }, // E4
+ { 0x4, 0x2, 0x3, }, // E5
+ { 0x4, 0x2, 0x3, }, // E6
+ { 0x4, 0x2, 0x3, }, // E7
+ { 0x4, 0x2, 0x2, }, // E8
+ { 0x4, 0x3, 0x2, }, // E9
+ { 0x4, 0x3, 0x2, }, // EA
+ { 0x4, 0x3, 0x2, }, // EB
+ { 0x4, 0x4, 0x2, }, // EC
+ { 0x3, 0x4, 0x2, }, // ED
+ { 0x3, 0x4, 0x2, }, // EE
+ { 0x3, 0x4, 0x2, }, // EF
+ { 0x2, 0x4, 0x2, }, // F0
+ { 0x2, 0x4, 0x3, }, // F1
+ { 0x2, 0x4, 0x3, }, // F2
+ { 0x2, 0x4, 0x3, }, // F3
+ { 0x2, 0x4, 0x4, }, // F4
+ { 0x2, 0x3, 0x4, }, // F5
+ { 0x2, 0x3, 0x4, }, // F6
+ { 0x2, 0x3, 0x4, }, // F7
+ { 0x0, 0x0, 0x0, }, // F8
+ { 0x0, 0x0, 0x0, }, // F9
+ { 0x0, 0x0, 0x0, }, // FA
+ { 0x0, 0x0, 0x0, }, // FB
+ { 0x0, 0x0, 0x0, }, // FC
+ { 0x0, 0x0, 0x0, }, // FD
+ { 0x0, 0x0, 0x0, }, // FE
+ { 0x0, 0x0, 0x0, }, // FF
+};
+
+// 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the
+// LCD Interface, while the LSB of GREEN is loaded as 0
+//#define RED_SUBPIXEL(n) (n & 0x1f) << 11
+//#define GREEN_SUBPIXEL(n) (n & 0x1f) << 6
+//#define BLUE_SUBPIXEL(n) (n & 0x1f) << 0
+
+// define a simple VGA style 16-color pallette
+//#define LU_BLACK RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)
+//#define LU_BLUE RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)
+//#define LU_GREEN RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)
+//#define LU_CYAN RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)
+//#define LU_RED RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)
+//#define LU_VIOLET RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)
+//#define LU_YELLOW RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)
+//#define LU_GREY RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)
+//#define LU_WHITE RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17)
+//#define LU_BRT_BLUE RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)
+//#define LU_BRT_GREEN RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)
+//#define LU_BRT_CYAN RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)
+//#define LU_BRT_RED RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)
+//#define LU_BRT_VIOLET RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)
+//#define LU_BRT_YELLOW RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)
+//#define LU_BRT_WHITE RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)
+
+
diff --git a/ports/beagleboneblack/nand740.c b/ports/beagleboneblack/nand740.c
new file mode 100644
index 0000000..95a912a
--- /dev/null
+++ b/ports/beagleboneblack/nand740.c
@@ -0,0 +1,333 @@
+/*
+ * Board/device specific connection between the generic
+ * nand command and the CSB740's NAND memory access through
+ * the OMAP3530.
+ *
+ * The CSB740 uses K9K4GO8UOM NAND (512Mx8bit) device from Samsung.
+ * It is connected to the OMAP3530's CS3 through the CPLD.
+ * The device ID for this part number should be: 0xECDC109554
+ *
+ * Maker code: 0xEC
+ * Device code: 0xDC
+ * Third cycle: 0x10
+ * Fourth cycle: 0x95
+ * Fifth cycle: 0x54
+ *
+ * Blocksize: 128K (smallest eraseable chunk)
+ * Pagesize: 2K (64 pages per block)
+ *
+ * Taken from the NAND datasheet...
+ * The 528M byte physical space requires 30 addresses, thereby
+ * requiring five cycles for addressing :
+ * 2 cycles of column address, 3 cycles of row address, in that
+ * order. Page Read and Page Program need the same five address
+ * cycles following the required command input. In Block Erase
+ * operation, however, only the three row address cycles are used.
+ * Device operations are selected by writing specific commands into
+ * the command register.
+ *
+ * Taken from ONFI Spec:
+ * The address is comprised of a row address and a column address.
+ * The row address identifies the page, block, and LUN to be accessed.
+ * The column address identifies the byte or word within a page to access.
+ *
+ * Note:
+ * Apparently this Sansung device is not ONFI compliant. There was an
+ * earlier version of the CSB740 that had a Micron part on it and it was
+ * ONFI compliant (ONFI=Open Nand Flash Interface specification).
+ *
+ */
+#include "config.h"
+#if INCLUDE_NANDCMD
+#include "stddefs.h"
+#include "genlib.h"
+#include "omap3530.h"
+#include "omap3530_mem.h"
+#include "nand.h"
+
+static int pgSiz;
+static int blkSiz;
+static char onfi;
+
+#define NANDSTAT_FAIL 0x01
+#define NANDSTAT_READY 0x40
+#define NANDSTAT_NOTWP 0x80
+
+#define NAND_CMD(cs) (vuchar *)(0x6e00007C + (0x30 * cs))
+#define NAND_ADR(cs) (vuchar *)(0x6e000080 + (0x30 * cs))
+#define NAND_DAT(cs) (vuchar *)(0x6e000084 + (0x30 * cs))
+
+#define PREFETCH_READ_MODE() GPMC_REG(GPMC_PREFETCH_CONFIG1) &= ~1
+#define WRITE_POSTING_MODE() GPMC_REG(GPMC_PREFETCH_CONFIG1) |= 1
+
+#define NAND_CS_BASEADDR 0x18000000
+
+/* some discussion to follow:
+ * http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/29683/103192.aspx
+ * Address is "page/block/column"...
+ */
+
+/* nandBusyWait():
+ * Poll the WAIT3 bit of the gmpc-status register, waiting for
+ * it to go active.
+ * The R/B (ready/busy) pin of the NAND device is low when busy.
+ * It is tied to WAIT3 of the CPU.
+ */
+void
+nandHardBusyWait(void)
+{
+ while((GPMC_REG(GPMC_STATUS) & 0x800) == 0x800);
+ //while((GPMC_REG(GPMC_STATUS) & 0x800) == 0);
+}
+
+void
+nandSoftBusyWait(void)
+{
+ do {
+ *NAND_CMD(3) = 0x70;
+ } while((*NAND_DAT(3) & NANDSTAT_READY) == 0);
+}
+
+void
+nandSetColAddr(unsigned long addr)
+{
+ // Column1 (A07|A06|A05|A04|A03|A02|A01|A00):
+ *NAND_ADR(3) = ((addr & 0x000000ff));
+
+ // Column2 (---|---|---|---|A11|A10|A09|A08):
+ *NAND_ADR(3) = ((addr & 0x00000f00) >> 8);
+}
+
+void
+nandSetRowAddr(unsigned long addr)
+{
+ // Row1 (A19|A18|A17|A16|A15|A14|A13|A12):
+ *NAND_ADR(3) = ((addr & 0x000ff000) >> 12);
+
+ // Row2 (A27|A26|A25|A24|A23|A22|A21|A20):
+ *NAND_ADR(3) = ((addr & 0x0ff00000) >> 20);
+
+ // Row3 (---|---|---|---|---|---|A29|A28):
+ *NAND_ADR(3) = ((addr & 0x30000000) >> 28);
+}
+
+/* nandReadChunk():
+ * Transfer some chunk of memory from NAND to a destination.
+ */
+int
+nandReadChunk(char *src, char *dest, int len)
+{
+ unsigned long addr = (long)src;
+
+ PREFETCH_READ_MODE();
+
+ if (nandVerbose)
+ printf("nandReadChunk(src=0x%x,dest=0x%x,len=%d)\n",src,dest,len);
+
+ while(len > 0) {
+ int tot;
+
+ *NAND_CMD(3) = 0x00;
+ nandSetColAddr(addr);
+ nandSetRowAddr(addr);
+ *NAND_CMD(3) = 0x30;
+
+ nandHardBusyWait();
+
+ tot = len > pgSiz ? pgSiz : len;
+ memcpy(dest,(char *)NAND_CS_BASEADDR,tot);
+
+ len -= tot;
+ dest += tot;
+ }
+ return(0);
+}
+
+int
+nandWriteChunk(char *dest, char *src, int len)
+{
+ unsigned long addr = (long)dest;
+
+ WRITE_POSTING_MODE();
+
+ if (nandVerbose)
+ printf("nandWriteBlock(dest=0x%x,src=0x%x,len=%d)\n",dest,src,len);
+
+ *NAND_CMD(3) = 0x80;
+ nandSetColAddr(addr);
+ nandSetRowAddr(addr);
+ memcpy((char *)NAND_CS_BASEADDR,src,len);
+ *NAND_CMD(3) = 0x10;
+
+ nandSoftBusyWait();
+
+ return(0);
+}
+
+int
+nandEraseChunk(char *base, int len)
+{
+ unsigned long addr = (long)base;
+
+ if (nandVerbose)
+ printf("nandEraseChunk(addr=0x%x,len=%d)\n",addr,len);
+
+ *NAND_CMD(3) = 0x60;
+ nandSetRowAddr(addr);
+ *NAND_CMD(3) = 0xd0;
+
+ nandSoftBusyWait();
+
+ return(0);
+}
+
+void
+nandId(void)
+{
+ uchar d[5];
+ uchar d1[4];
+
+ *NAND_CMD(3) = 0x90;
+ *NAND_ADR(3) = 0x00;
+ d[0] = *NAND_DAT(3);
+ d[1] = *NAND_DAT(3);
+ d[2] = *NAND_DAT(3);
+ d[3] = *NAND_DAT(3);
+ d[4] = *NAND_DAT(3);
+
+ switch(d[3] & 3) {
+ case 0:
+ pgSiz = 1024;
+ break;
+ case 1:
+ pgSiz = 1024*2;
+ break;
+ case 2:
+ pgSiz = 1024*4;
+ break;
+ case 3:
+ pgSiz = 1024*8;
+ break;
+ }
+ switch((d[3] & 0x30) >> 4) {
+ case 0:
+ blkSiz = 1024*64;
+ break;
+ case 1:
+ blkSiz = 1024*128;
+ break;
+ case 2:
+ blkSiz = 1024*256;
+ break;
+ case 3:
+ blkSiz = 1024*512;
+ break;
+ }
+
+ *NAND_CMD(3) = 0x90;
+ *NAND_ADR(3) = 0x20;
+ d1[0] = *NAND_DAT(3);
+ d1[1] = *NAND_DAT(3);
+ d1[2] = *NAND_DAT(3);
+ d1[3] = *NAND_DAT(3);
+ if (memcmp((char *)d1,"ONFI",4) == 0)
+ onfi = 1;
+ else
+ onfi = 0;
+
+ if (nandVerbose) {
+ printf("nandID(): %02x%02x%02x%02x%02x\n",d[0],d[1],d[2],d[3],d[4]);
+ printf("nandID+(): %02x%02x%02x%02x%02x\n",d1[0],d1[1],d1[2],d1[3]);
+ printf("Page size: 0x%x\n",pgSiz);
+ printf("Block size: 0x%x\n",blkSiz);
+ printf("%sONFI compliant\n",onfi ? "" : "Not ");
+ }
+}
+
+int
+nandInit(void)
+{
+ vulong cfgreg;
+
+#if 0
+ printf("CFG1: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG1),GPMC_REG(GPMC_CS3_CONFIG1));
+ printf("CFG2: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG2),GPMC_REG(GPMC_CS3_CONFIG2));
+ printf("CFG3: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG3),GPMC_REG(GPMC_CS3_CONFIG3));
+ printf("CFG4: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG4),GPMC_REG(GPMC_CS3_CONFIG4));
+ printf("CFG5: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG5),GPMC_REG(GPMC_CS3_CONFIG5));
+ printf("CFG6: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG6),GPMC_REG(GPMC_CS3_CONFIG6));
+ printf("CFG7: dm -4 0x%08x 1 = %08x\n",
+ MYGPMC_REG(GPMC_CS3_CONFIG7),GPMC_REG(GPMC_CS3_CONFIG7));
+#endif
+
+
+ /* WAIT3 of the CPU is tied to the NAND's READY pin. The NAND
+ * is on CS3. Referring to section 11.1.7.2.10 of the OMAP3530 TRM,
+ * the GPMC_CONFIGX registers must be programmed...
+ */
+ GPMC_REG(GPMC_CONFIG) |= 0x1; // Force posted write.
+ GPMC_REG(GPMC_CONFIG) &= ~0x800; // WAIT3 active low.
+ GPMC_REG(GPMC_CS3_CONFIG7) = 0x00000858; // Base addr 0x18000000
+ GPMC_REG(GPMC_CS3_CONFIG1) = 0x00030800; // 8-bit NAND, WAIT3
+ GPMC_REG(GPMC_CS3_CONFIG2) = 0x00000000; // Chipselect timing
+ GPMC_REG(GPMC_CS3_CONFIG3) |= 0x7;
+ GPMC_REG(GPMC_CS3_CONFIG6) = 0x8f0307c0;
+
+ // Set drive strength of BE0/CLE
+ *(vulong *)0x48002444 |= 0x00000020;
+
+ /***********************************************************
+ *
+ * ALE and CLE on the NAND are both active high, so we want
+ * them to be pulled low...
+ *
+ * ALE config is the low half of this config register, so we only
+ * touch the bottom half...
+ */
+ cfgreg = SCM_REG(PADCONFS_GPMC_NADV_ALE); // NOE[31:16], NADV_ALE[15:0]
+ cfgreg &= 0xffff0000;
+ cfgreg |= 0x00000008;
+ SCM_REG(PADCONFS_GPMC_NADV_ALE) = cfgreg;
+ /*
+ * CLE config is the upper half of this config register, so we only
+ * touch the upper half...
+ */
+ cfgreg = SCM_REG(PADCONFS_GPMC_NWE); // NBE0_CLE[31:16], NWE[15:0]
+ cfgreg &= 0x0000ffff;
+ cfgreg |= 0x00080000;
+ SCM_REG(PADCONFS_GPMC_NWE) = cfgreg;
+
+
+ /* WAIT3 of CPU is tied to R/B pin of NAND...
+ * So, we configure that pin to run as WAIT3.
+ * NOTE:
+ * There is some confusion between this and what is in cpuio.c.
+ * The PADCONFS_GPMC_WAIT2 register sets this pin as GPIO-65 there;
+ * however the comments are confusing.
+ */
+ cfgreg = SCM_REG(PADCONFS_GPMC_WAIT2); // WAIT3[31:16], WAIT2[15:0]
+ cfgreg &= 0x0000ffff;
+ cfgreg |= 0x00080000;
+ SCM_REG(PADCONFS_GPMC_NWE) = cfgreg;
+
+ nandId();
+ return(0);
+}
+
+int
+nandInfo(void)
+{
+ nandId();
+ return(0);
+}
+
+
+#endif
+
+
diff --git a/ports/beagleboneblack/omap3530.h b/ports/beagleboneblack/omap3530.h
new file mode 100644
index 0000000..7b16ffc
--- /dev/null
+++ b/ports/beagleboneblack/omap3530.h
@@ -0,0 +1,497 @@
+//==========================================================================
+//
+// omap3530.h
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 05/02/2008
+// Description: This file contains register base addresses and offsets
+// and access macros for the OMAP3530 on-chip peripherals
+// Peripherals not used by UMON have not been tested (and
+// may not be defined). Use these defines with caution!!
+//
+
+#include "bits.h"
+
+/*
+ * 3530 specific Section
+ */
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE 0x68000000
+
+/* L3 Firewall */
+#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048)
+#define A_READPERM0 (SMX_APE_BASE + 0x05050)
+#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058)
+
+/* GPMC */
+#define OMAP35XX_GPMC_BASE 0x6E000000
+
+/* SMS */
+#define OMAP35XX_SMS_BASE 0x6C000000
+
+/* SDRC */
+#define OMAP35XX_SDRC_BASE 0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP35XX_CORE_L4_IO_BASE 0x48000000
+
+#define OMAP35XX_WAKEUP_L4_IO_BASE 0x48300000
+
+#define OMAP35XX_L4_PER 0x49000000
+
+#define OMAP35XX_L4_IO_BASE OMAP35XX_CORE_L4_IO_BASE
+
+/* TAP information dont know for 3430*/
+#define OMAP35XX_TAP_BASE (0x49000000) /*giving some junk for virtio */
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
+#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+/*-------------------------------------------------------------------------------------*/
+/* UART */
+/*-------------------------------------------------------------------------------------*/
+#define OMAP35XX_UART1 (OMAP35XX_L4_IO_BASE+0x6A000)
+#define OMAP35XX_UART2 (OMAP35XX_L4_IO_BASE+0x6C000)
+#define OMAP35XX_UART3 (OMAP35XX_L4_PER+0x20000)
+#define UART1_REG(_x_) *(vulong *)(OMAP35XX_UART1 + _x_)
+#define UART2_REG(_x_) *(vulong *)(OMAP35XX_UART2 + _x_)
+#define UART3_REG(_x_) *(vulong *)(OMAP35XX_UART3 + _x_)
+
+/* UART Register offsets */
+#define UART_RHR 0x00 // Receive Holding Register (read only)
+#define UART_THR 0x00 // Transmit Holding Register (write only)
+#define UART_DLL 0x00 // Baud divisor lower byte (read/write)
+#define UART_DLH 0x04 // Baud divisor higher byte (read/write)
+#define UART_IER 0x04 // Interrupt Enable Register (read/write)
+#define UART_IIR 0x08 // Interrupt Identification Register (read only)
+#define UART_FCR 0x08 // FIFO Control Register (write only)
+#define UART_EFR 0x08 // Enhanced Feature Register
+#define UART_LCR 0x0C // Line Control Register (read/write)
+#define UART_MCR 0x10 // Modem Control Register (read/write)
+#define UART_LSR 0x14 // Line Status Register (read only)
+#define UART_MSR 0x18 // Modem Status Register (read only)
+#define UART_TCR 0x18 //
+#define UART_TLR 0x1C //
+#define UART_SPR 0x1C // Scratch Pad Register (read/write)
+#define UART_MDR1 0x20 // Mode Definition Register 1
+#define UART_MDR2 0x24 // Mode Definition Register 2
+//#define UART_SFLSR 0x28 // Status FIFO Line Status Register (IrDA modes only)
+//#define UART_TXFLL 0x28 // Transmit Frame Length Register Low (IrDA modes only)
+//#define UART_RESUME 0x2C // Resume Register (IR-IrDA and IR-CIR modes only)
+//#define UART_TXFLH 0x2C // Transmit Frame Length Register High (IrDA modes only)
+//#define UART_RXFLL 0x30 // Receive Frame Length Register Low (IrDA modes only)
+//#define UART_SFREGL 0x30 // Status FIFO Register Low (IrDA modes only)
+//#define UART_RXFLH 0x34 // Receive Frame Length Register High (IrDA modes only)
+//#define UART_SFREGH 0x34 // Status FIFO Register High (IrDA modes only)
+//#define UART_BLR 0x38 // BOF Control Register (IrDA modes only)
+//#define UART_UASR 0x38 // UART Autobauding Status Register (UART autobauding mode only)
+//#define UART_ACREG 0x3C // Auxiliary Control Register (IrDA-CIR modes only)
+#define UART_SCR 0x40 // Supplementary Control Register
+#define UART_SSR 0x44 // Supplementary Status Register
+//#define UART_EBLR 0x48 // BOF Length Register (IR-IrDA and IR-CIR modes only)
+#define UART_SYSC 0x54 // System Configuration Register
+#define UART_SYSS 0x58 // System Status Register
+#define UART_WER 0x5C // Wake-up Enable Register
+#define UART_CFPS 0x60 // Carrier Frequency Prescaler Register
+
+/*-------------------------------------------------------------------------------------*/
+/* SPI - Serial Peripheral Interface */
+/*-------------------------------------------------------------------------------------*/
+#define SPI1_BASE_ADD (OMAP35XX_L4_IO_BASE+0x98000) // routed to I/O sites on CSB703
+#define SPI2_BASE_ADD (OMAP35XX_L4_IO_BASE+0x9A000)
+#define SPI3_BASE_ADD (OMAP35XX_L4_IO_BASE+0xB8000) // routed to AD7843 touch controller on CSB703
+#define SPI4_BASE_ADD (OMAP35XX_L4_IO_BASE+0xBA000)
+#define SPI1_REG(_x_) *(vulong *)(SPI1_BASE_ADD + _x_)
+#define SPI2_REG(_x_) *(vulong *)(SPI2_BASE_ADD + _x_)
+#define SPI3_REG(_x_) *(vulong *)(SPI3_BASE_ADD + _x_)
+#define SPI4_REG(_x_) *(vulong *)(SPI4_BASE_ADD + _x_)
+
+// SPI Register Defines
+#define SPI_SYSCONFIG 0x10 // System Configuration Register
+#define SPI_SYSSTATUS 0x14 // System Status Register
+#define SPI_IRQSTATUS 0x18 // Interrupt Status Register
+#define SPI_IRQENABLE 0x1C // Interrupt Enable/Disable Register
+#define SPI_WAKEUPENABLE 0x20 // WakeUp Enable/Disable Register
+#define SPI_SYST 0x24 // System Test Register
+#define SPI_MODULCTRL 0x28 // Serial Port Interface Configuration Register
+#define SPI_CH0_CONF 0x2C // Channel 0 Configuration Register
+#define SPI_CH1_CONF 0x40 // Channel 1 Configuration Register
+#define SPI_CH2_CONF 0x54 // Channel 2 Configuration Register
+#define SPI_CH3_CONF 0x68 // Channel 3 Configuration Register
+#define SPI_CH0_STAT 0x30 // Channel 0 Status Register
+#define SPI_CH1_STAT 0x44 // Channel 1 Status Register
+#define SPI_CH2_STAT 0x58 // Channel 2 Status Register
+#define SPI_CH3_STAT 0x6C // Channel 3 Status Register
+#define SPI_CH0_CTRL 0x34 // Channel 0 Control Register
+#define SPI_CH1_CTRL 0x48 // Channel 1 ControlRegister
+#define SPI_CH2_CTRL 0x5C // Channel 2 ControlRegister
+#define SPI_CH3_CTRL 0x70 // Channel 3 ControlRegister
+#define SPI_TXD0 0x38 // Channel 0 Transmit Data Register
+#define SPI_TXD1 0x4C // Channel 1 Transmit Data Register
+#define SPI_TXD2 0x60 // Channel 2 Transmit Data Register
+#define SPI_TXD3 0x74 // Channel 3 Transmit Data Register
+#define SPI_RXD0 0x3C // Channel 0 Receive Data Register
+#define SPI_RXD1 0x50 // Channel 1 Receive Data Register
+#define SPI_RXD2 0x64 // Channel 2 Receive Data Register
+#define SPI_RXD3 0x78 // Channel 3 Receive Data Register
+#define SPI_XFERLEVEL 0x7C // FIFO Transfer Levels Register
+
+// SPI Channel x Configuration Bit Defines
+#define SPI_CH_CONF_CLKG BIT29 // 1 = One clock cycle granularity
+#define SPI_CH_CONF_FFER BIT28 // 1 = FIFO buffer is used to Receive data
+#define SPI_CH_CONF_FFEW BIT27 // 1 = FIFO buffer is used to Transmit data
+#define SPI_CH_CONF_TCS_0_5 (0x00 << 25) // 0.5 clock cycles between CS toggling and first (or last) edge of SPI clock
+#define SPI_CH_CONF_TCS_1_5 (0x01 << 25) // 1.5 clock cycles between CS toggling and first (or last) edge of SPI clock
+#define SPI_CH_CONF_TCS_2_5 (0x02 << 25) // 2.5 clock cycles between CS toggling and first (or last) edge of SPI clock
+#define SPI_CH_CONF_TCS_3_5 (0x03 << 25) // 3.5 clock cycles between CS toggling and first (or last) edge of SPI clock
+#define SPI_CH_CONF_SB_POL BIT24 // 1 = Start bit polarity is held to 1 during SPI transfer
+#define SPI_CH_CONF_SBE BIT23 // 1 = Start bit added before SPI transfer, 0 = default length specified by WL
+#define SPI_CH_CONF_SPIENSLV_0 (0x00 << 21) // Slave select detection enabled on CS0
+#define SPI_CH_CONF_SPIENSLV_1 (0x01 << 21) // Slave select detection enabled on CS1
+#define SPI_CH_CONF_SPIENSLV_2 (0x02 << 21) // Slave select detection enabled on CS2
+#define SPI_CH_CONF_SPIENSLV_3 (0x03 << 21) // Slave select detection enabled on CS3
+#define SPI_CH_CONF_FORCE BIT20 // 1 = CSx high when EPOL is 0 and low when EPOL is 1
+#define SPI_CH_CONF_TURBO BIT19 // 1 = Turbo is activated
+#define SPI_CH_CONF_IS BIT18 // 1 = spim_simo selected for reception, 0 = spim_somi selected for reception
+#define SPI_CH_CONF_DPE1 BIT17 // 1 = no transmission on spim_simo, 0 = spim_simo selected for transmission
+#define SPI_CH_CONF_DPE0 BIT16 // 1 = no transmission on spim_somi, 0 = spim_somi selected for transmission
+#define SPI_CH_CONF_DMAR BIT15 // 1 = DMA read request enabled
+#define SPI_CH_CONF_DMAW BIT14 // 1 = DMA write request enabled
+#define SPI_CH_CONF_TRM_TR (0x00 << 12) // Transmit and receive mode
+#define SPI_CH_CONF_TRM_RO (0x01 << 12) // Receive-only mode
+#define SPI_CH_CONF_TRM_TO (0x02 << 12) // Transmit-only mode
+#define SPI_CH_CONF_WL(_x_) ((_x_ & 0x1f) << 7) // SPI word length, 0x7 = 8-bit
+#define SPI_CH_CONF_EPOL BIT6 // 1 = SPIM_CSx is low during active state, 0 = high during active state
+#define SPI_CH_CONF_CLKD(_x_) ((_x_ & 0xf) << 2) // Frequency divider for spim_clk
+#define SPI_CH_CONF_POL BIT1 // 1 = spim_clk is low during active state, 0 = high during active state
+#define SPI_CH_CONF_PHA BIT0 // 1 = data latched on even-numbered edges, 0 = data latched on odd-numbered edges
+
+// SPI Interrupt Status Register Bit Defines
+#define SPI_RX3_FULL BIT14 //
+#define SPI_TX3_EMPTY BIT12 //
+#define SPI_RX2_FULL BIT10 //
+#define SPI_TX2_EMPTY BIT8 //
+#define SPI_RX1_FULL BIT14 //
+#define SPI_TX1_EMPTY BIT6 //
+#define SPI_RX0_FULL BIT2 //
+#define SPI_TX0_EMPTY BIT0 //
+
+// SPI Channel Status Register Bit Defines
+#define SPI_RXF_FULL BIT6 //
+#define SPI_RXF_EMPTY BIT5 //
+#define SPI_TXF_FULL BIT4 //
+#define SPI_TXF_EMPTY BIT3 //
+#define SPI_CH_EOT BIT2 //
+#define SPI_CH_TX0_EMPTY BIT1 //
+#define SPI_CH_RX0_FULL BIT0 //
+
+/*-------------------------------------------------------------------------------------*/
+/* General Purpose Timers */
+/*-------------------------------------------------------------------------------------*/
+#define OMAP35XX_GPT1 0x48318000
+#define OMAP35XX_GPT2 0x49032000
+#define OMAP35XX_GPT3 0x49034000
+#define OMAP35XX_GPT4 0x49036000
+#define OMAP35XX_GPT5 0x49038000
+#define OMAP35XX_GPT6 0x4903A000
+#define OMAP35XX_GPT7 0x4903C000
+#define OMAP35XX_GPT8 0x4903E000
+#define OMAP35XX_GPT9 0x49040000
+#define OMAP35XX_GPT10 0x48086000
+#define OMAP35XX_GPT11 0x48088000
+#define OMAP35XX_GPT12 0x48304000
+
+/*-------------------------------------------------------------------------------------*/
+/* General Purpose I/O */
+/*-------------------------------------------------------------------------------------*/
+#define GPIO1_BASE_ADD 0x48310000
+#define GPIO2_BASE_ADD 0x49050000
+#define GPIO3_BASE_ADD 0x49052000
+#define GPIO4_BASE_ADD 0x49054000
+#define GPIO5_BASE_ADD 0x49056000
+#define GPIO6_BASE_ADD 0x49058000
+#define GPIO1_REG(_x_) *(vulong *)(GPIO1_BASE_ADD + _x_)
+#define GPIO2_REG(_x_) *(vulong *)(GPIO2_BASE_ADD + _x_)
+#define GPIO3_REG(_x_) *(vulong *)(GPIO3_BASE_ADD + _x_)
+#define GPIO4_REG(_x_) *(vulong *)(GPIO4_BASE_ADD + _x_)
+#define GPIO5_REG(_x_) *(vulong *)(GPIO5_BASE_ADD + _x_)
+#define GPIO6_REG(_x_) *(vulong *)(GPIO6_BASE_ADD + _x_)
+
+/* GPIO Register offsets */
+#define GPIO_SYSCONFIG 0x10 //
+#define GPIO_SYSSTATUS 0x14 //
+#define GPIO_CTRL 0x30 //
+#define GPIO_OE 0x34 //
+#define GPIO_DATAIN 0x38 //
+#define GPIO_DATAOUT 0x3C //
+#define GPIO_CLEARDATAOUT 0x90 //
+#define GPIO_SETDATAOUT 0x94 //
+
+/*-------------------------------------------------------------------------------------*/
+/* WatchDog Timers (1 secure, 3 GP) */
+/*-------------------------------------------------------------------------------------*/
+#define WD1_BASE_ADD 0x4830C000
+#define WD2_BASE_ADD 0x48314000
+#define WD3_BASE_ADD 0x49030000
+#define WD1_REG(_x_) *(vulong *)(WD1_BASE_ADD + _x_)
+#define WD2_REG(_x_) *(vulong *)(WD2_BASE_ADD + _x_)
+#define WD3_REG(_x_) *(vulong *)(WD3_BASE_ADD + _x_)
+
+/* WatchDog Timer Register offsets */
+#define WD_CONFIG 0x10 // System Configuration Register
+#define WD_STATUS 0x14 // System Configuration Register
+#define WD_WISR 0x18 // System Configuration Register
+#define WD_WIER 0x1C // System Configuration Register
+#define WD_WCLR 0x24 // System Configuration Register
+#define WD_WCRR 0x28 // System Configuration Register
+#define WD_WLDR 0x2C // System Configuration Register
+#define WD_WTGR 0x30 // System Configuration Register
+#define WD_WWPS 0x34 // System Configuration Register
+#define WD_WSPR 0x48 // System Configuration Register
+
+/*-------------------------------------------------------------------------------------*/
+/* 32KTIMER */
+/*-------------------------------------------------------------------------------------*/
+#define SYNC_32KTIMER_BASE (0x48320000)
+#define S32K_CR (SYNC_32KTIMER_BASE+0x10)
+
+/*-------------------------------------------------------------------------------------*/
+/* System Control Module */
+/*-------------------------------------------------------------------------------------*/
+/* Module Name Base Address Size */
+/*
+ INTERFACE 0x48002000 36 bytes
+ PADCONFS 0x48002030 564 bytes
+ GENERAL 0x48002270 767 bytes
+ MEM_WKUP 0x48002600 1K byte
+ PADCONFS_WKU 0x48002A00 80 bytes
+ GENERAL_WKUP 0x48002A60 31 bytes
+*/
+/*-------------------------------------------------------------------------------------*/
+#define OMAP35XX_CTRL_BASE (OMAP35XX_L4_IO_BASE+0x2000)
+#define SCM_REG(_x_) *(vulong *)(OMAP35XX_CTRL_BASE + _x_)
+
+/* Pad Configuration Registers */
+/* Note: Cogent is only defining the PADCONFS registers that are used in Micromonitor */
+#define PADCONFS_GPMC_NCS3 0xB4 // NCS3[15:0], NCS4[31:16]
+#define PADCONFS_GPMC_NCS5 0xB8 // NCS5[15:0], EXP_INTX[31:16]
+#define PADCONFS_GPMC_NCS7 0xBC // LCD_BKL_X[15:0], LCLK[31:16]
+#define PADCONFS_GPMC_NADV_ALE 0xC0 // NADV_ALE[15:0], NOE[31:16]
+#define PADCONFS_GPMC_NWE 0xC4 // NWE[15:0], NBE0_CLE[31:16]
+#define PADCONFS_DSS_PCLK 0xD4 // LCD_PCLK_X[15:0], LCD_HS_X[31:16]
+#define PADCONFS_DSS_VSYNC 0xD8 // LCD_VS_X[15:0], LCD_OE_X[31:16]
+#define PADCONFS_DSS_DATA0 0xDC // LCD_B0_X[15:0], LCD_B1_X[31:16]
+#define PADCONFS_DSS_DATA2 0xE0 // LCD_B2_X[15:0], LCD_B3_X[31:16]
+#define PADCONFS_DSS_DATA4 0xE4 // LCD_B4_X[15:0], LCD_B5_X[31:16]
+#define PADCONFS_DSS_DATA6 0xE8 // LCD_G0_X[15:0], LCD_G1_X[31:16]
+#define PADCONFS_DSS_DATA8 0xEC // LCD_G2_X[15:0], LCD_G3_X[31:16]
+#define PADCONFS_DSS_DATA10 0xF0 // LCD_G4_X[15:0], LCD_G5_X[31:16]
+#define PADCONFS_DSS_DATA12 0xF4 // LCD_R0_X[15:0], LCD_R1_X[31:16]
+#define PADCONFS_DSS_DATA14 0xF8 // LCD_R2_X[15:0], LCD_R3_X[31:16]
+#define PADCONFS_DSS_DATA16 0xFC // LCD_R4_X[15:0], LCD_R5_X[31:16]
+#define PADCONFS_DSS_DATA18 0x100 // SPI1_CLK_X[15:0], SPI1_MOSI_X[31:16]
+#define PADCONFS_DSS_DATA20 0x104 // SPI1_MISO_X[15:0], *SPI1_CS0_X[31:16]
+#define PADCONFS_DSS_DATA22 0x108 // GPIO7_X[15:0], NC[31:16]
+#define PADCONFS_MMC1_DAT4 0x150 // *I2C_INT_X[15:0], *PIRQ_X[31:16]
+#define PADCONFS_MMC1_DAT6 0x154 // GPIO0_X[15:0], GPIO1_X[31:16]
+#define PADCONFS_MCBSP3_CLKX 0x170 // D_TXD[15:0], D_RXD[31:16]
+#define PADCONFS_SYS_NIRQ 0x1E0 // FIQ[15:0], SYS_CLK2[31:16]
+#define PADCONFS_SYS_OFF_MODE 0xA18 // OFF_MODE_X[15:0], USB_CLK[31:16]
+#define PADCONFS_GPMC_WAIT2 0xD0 // NA[15:0], E_INTX[31:16]
+#define PADCONFS_MMC1_CLK 0x144 // MMC1_CLK[15:0], MMC1_CMD[31:16]
+#define PADCONFS_MMC1_DAT0 0x148 // MMC1_DAT0[15:0], MMC1_DAT1[31:16]
+#define PADCONFS_MMC1_DAT2 0x14C // MMC1_DAT2[15:0], MMC1_DAT3[31:16]
+
+
+#define CM_REV_REG 0x48004800
+#define PRM_REV_REG 0x48306804
+#define CM_REV_MAJ() ((*(volatile unsigned long *)CM_REV_REG & 0xf0)>>4)
+#define CM_REV_MIN() (*(volatile unsigned long *)CM_REV_REG & 0x0f)
+#define PRM_REV_MAJ() ((*(volatile unsigned long *)PRM_REV_REG & 0xf0)>>4)
+#define PRM_REV_MIN() (*(volatile unsigned long *)PRM_REV_REG & 0x0f)
+
+/* MMC registers...
+ */
+#define CM_FCLKEN1_CORE 0x48004a00
+#define CM_ICLKEN1_CORE 0x48004a10
+#define CM_IDLEST1_CORE 0x48004a20
+#define CM_AUTOIDLE1_CORE 0x48004a30
+#define PM_WKEN1_CORE 0x48306aa0
+#define PM_MPUGRPSEL1_CORE 0x48306aa4
+#define PM_IVA2GRPSEL1_CORE 0x48306aa8
+#define PM_WKST1_CORE 0x48306ab0
+#define CONTROL_DEVCONF0 0x48002274
+#define MMC1_BASE_ADD 0x4809c000
+#define MMC2_BASE_ADD 0x480ad000
+#define MMC3_BASE_ADD 0x480b4000
+#define MMC1_REG(_x_) *(vulong *)(MMC1_BASE_ADD + _x_)
+#define MMC2_REG(_x_) *(vulong *)(MMC2_BASE_ADD + _x_)
+#define MMC3_REG(_x_) *(vulong *)(MMC3_BASE_ADD + _x_)
+#define MMCHS_SYSCONFIG 0x10
+#define MMCHS_SYSSTATUS 0x14
+#define MMCHS_CSRE 0x24
+#define MMCHS_SYSTEST 0x28
+#define MMCHS_CON 0x2C
+#define MMCHS_PWCNT 0x30
+#define MMCHS_BLK 0x104
+#define MMCHS_ARG 0x108
+#define MMCHS_CMD 0x10C
+#define MMCHS_RSP10 0x110
+#define MMCHS_RSP32 0x114
+#define MMCHS_RSP54 0x118
+#define MMCHS_RSP76 0x11C
+#define MMCHS_DATA 0x120
+#define MMCHS_PSTATE 0x124
+#define MMCHS_HCTL 0x128
+#define MMCHS_SYSCTL 0x12C
+#define MMCHS_STAT 0x130
+#define MMCHS_IE 0x134
+#define MMCHS_ISE 0x138
+#define MMCHS_AC12 0x13C
+#define MMCHS_CAPA 0x140
+#define MMCHS_CUR_CAPA 0x148
+#define MMCHS_REV 0x1FC
+
+/* Miscellaneous MMC register bits...
+ * (only specified the ones I use)
+ */
+#define EN_MMC1 (1 << 24)
+#define ST_MMC1 (1 << 24)
+#define AUTO_MMC1 (1 << 24)
+#define GRPSEL_MMC1 (1 << 24)
+#define VS18 0x04000000
+#define VS30 0x02000000
+#define VS33 0x01000000
+#define MMCINIT 0x00000002
+#define ODE 0x00000001
+#define SVDS 0x00000e00
+#define SVDS18 (5 << 9)
+#define SVDS30 (6 << 9)
+#define SVDS33 (7 << 9)
+#define SDBP 0x00000100
+#define ICE 0x00000001
+#define ICS 0x00000002
+#define CEN 0x00000004
+#define CLKD(v) ((v & 0x3ff) << 6)
+#define CLKDMSK (0x3ff << 6)
+#define CLKACTIVITYMSK (3 << 8)
+#define CLKACTIVITY(n) ((n & 3) << 8)
+#define SIDLEMODEMSK (3 << 3)
+#define SIDLEMODE(n) ((n & 3) << 3)
+#define ENWAKEUP (1 << 2)
+#define IWE (1 << 24)
+#define AUTOIDLE 1
+#define CLKEXTFREE (1 << 16)
+#define SRESET 0x00000002
+#define CC 0x00000001
+#define RESETDONE 0x00000001
+#define IE_ALL 0x317f8337
+#define CDP (1 << 7)
+#define CMD(v) ((v & 0x3f) << 24)
+#define CMDMSK (0x3f << 24)
+#define CMDI 0x00000001
+#define DEBOUNCE (3 << 16)
+#define CCRC (1 << 17)
+#define DCRC (1 << 21)
+#define CERR (1 << 28)
+#define CTO (1 << 16)
+#define DP (1 << 21)
+#define RSPTYPE_NONE 0x00000000
+#define RSPTYPE_136 0x00010000
+#define RSPTYPE_48 0x00020000
+#define RSPTYPE_48BSY 0x00030000
+#define RSPTYPE 0x00030000
+#define SRD (1 << 26)
+#define SRC (1 << 25)
+#define SRA (1 << 24)
+#define DTOMSK (0xf<<16)
+#define DTO(a) ((a&0xf) << 16)
+#define NBLK(a) ((a&0xffff) << 16)
+#define BLEN(a) (a&0x7ff)
+#define MMCSDIO1ADPCLKISEL (1 << 24)
+
+/* PBIAS...
+ */
+#define CONTROL_PBIAS_LITE 0x48002520
+#define PBIAS_LITE_VMMC1_3V (0x0101)
+#define MMC_PWR_STABLE (0x0202)
+#define PBIAS_LITE_VMMC1_52MHZ (0x0404)
+#define PBIAS_LITE_MMC1_ERROR (0x0808)
+#define PBIAS_LITE_MMC1_HIGH (0x8080)
+
+/* Control status...
+ */
+#define CONTROL_STATUS 0x480022f0
+#define SYSBOOT 0x3f
+#define DEVICETYPE (0x3 << 8)
+
+/* 16 bit access CONTROL */
+#define MUX_VAL(OFFSET,VALUE)\
+ *(unsigned short *) (OMAP35XX_CTRL_BASE + (OFFSET)) = VALUE;
+
+#define CP(x) (CONTROL_PADCONF_##x)
+
+#define CONTROL_PADCONF_DSS_DATA18 0x0100
+#define CONTROL_PADCONF_DSS_DATA19 0x0102
+#define CONTROL_PADCONF_DSS_DATA20 0x0104
+#define CONTROL_PADCONF_DSS_DATA21 0x0106
+
+#define CONTROL_PADCONF_MMC1_CLK 0x0144
+#define CONTROL_PADCONF_MMC1_CMD 0x0146
+#define CONTROL_PADCONF_MMC1_DAT0 0x0148
+#define CONTROL_PADCONF_MMC1_DAT1 0x014A
+#define CONTROL_PADCONF_MMC1_DAT2 0x014C
+#define CONTROL_PADCONF_MMC1_DAT3 0x014E
+
+#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
+#define CONTROL_PADCONF_I2C1_SCL 0x01BA
+#define CONTROL_PADCONF_I2C1_SDA 0x01BC
+#define CONTROL_PADCONF_McBSP3_DX 0x016C
+
+/* bits used in control reg's above
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ */
+
+#define IEN (1 << 8)
+
+#define IDIS (0 << 8)
+#define PTU (1 << 4)
+#define PTD (0 << 4)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0 /* modes */
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
diff --git a/ports/beagleboneblack/omap3530_gpio.c b/ports/beagleboneblack/omap3530_gpio.c
new file mode 100644
index 0000000..e1e4315
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_gpio.c
@@ -0,0 +1,329 @@
+//==========================================================================
+//
+// mx31_gpio.c
+//
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 05/09/2008
+// Description: This file contains code to intialize the MCIMX31 GPIO
+// section as well as functions for manipulating the GPIO
+// bits
+//
+//--------------------------------------------------------------------------
+
+#include "config.h"
+#include "cpuio.h"
+#include "stddefs.h"
+#include "genlib.h"
+#include "omap3530.h"
+#include "cpu_gpio.h" // pull in target board specific header
+
+//#define GPIO_DBG
+
+//--------------------------------------------------------
+// GPIO_init()
+//
+// This function sets the startup state for the MCIMX31 GPIO
+// registers as used on the target CPU. Refer to cpu_gpio.h
+// for a description of the default values. Here we just put
+// them into the chip in the following order:
+// 1. Port x DR - Data Register
+// 2. Port x DIR - Direction Register
+// 3. Port x PSTAT - Pad Status Register
+// 4. Port x ICR1 - GPIO Interrupt Configuration Register 1
+// 5. Port x ICR2 - GPIO Interrupt Configuration Register 2
+// 6. Port x IMASK - GPIO Interrupt Mask Register
+// 7. Port x ISTAT - GPIO Interrupt Status Register
+
+void GPIO_init()
+{
+ // Port 1
+ GPIO1_REG(GPIO_OE) = PORT1_OE;
+ GPIO1_REG(GPIO_DATAOUT) = PORT1_DR;
+ //GPIO1_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO1_REG(GPIO_SETDATAOUT) = 0;
+
+ // Port 2
+ //GPIO2_REG(GPIO_OE) = 0xFEFFFFFF;
+ GPIO2_REG(GPIO_OE) = PORT2_OE;
+ GPIO2_REG(GPIO_DATAOUT) = PORT2_DR;
+ //GPIO2_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO2_REG(GPIO_SETDATAOUT) = 0;
+
+ // Port 3
+ GPIO3_REG(GPIO_OE) = PORT3_OE;
+ GPIO3_REG(GPIO_DATAOUT) = PORT3_DR;
+ //GPIO3_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO3_REG(GPIO_SETDATAOUT) = 0;
+
+ // Port 4
+ GPIO4_REG(GPIO_OE) = PORT4_OE;
+ GPIO4_REG(GPIO_DATAOUT) = PORT4_DR;
+ //GPIO4_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO4_REG(GPIO_SETDATAOUT) = 0;
+
+ // Port 5
+ GPIO5_REG(GPIO_OE) = PORT5_OE;
+ GPIO5_REG(GPIO_DATAOUT) = PORT5_DR;
+ //GPIO5_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO5_REG(GPIO_SETDATAOUT) = 0;
+
+ // Port 6
+ GPIO6_REG(GPIO_OE) = PORT6_OE;
+ GPIO6_REG(GPIO_DATAOUT) = PORT6_DR;
+ //GPIO6_REG(GPIO_CLEARDATAOUT) = 0;
+ //GPIO6_REG(GPIO_SETDATAOUT) = 0;
+}
+
+//--------------------------------------------------------
+// GPIO_set()
+//
+// This function sets the desired bit passed in.
+// NOTE: We do not test to see if setting the bit
+// would screw up any alternate functions. Use
+// this function with caution!
+//
+
+int GPIO_set(int gpio_bit)
+{
+ // quick sanity test
+#ifdef GPIO_DBG
+ printf("GPIO_set %d.\n", gpio_bit);
+#endif
+ if (gpio_bit > 191) return -1;
+
+ if (gpio_bit < 32)
+ {
+ // Port 1
+ GPIO1_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 0));
+ }
+ else if (gpio_bit < 64)
+ {
+ // Port 2
+ GPIO2_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 32));
+ }
+ else if (gpio_bit < 96)
+ {
+ // Port 3
+ GPIO3_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 64));
+ }
+ else if (gpio_bit < 128)
+ {
+ // Port 4
+ GPIO4_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 96));
+ }
+ else if (gpio_bit < 160)
+ {
+ // Port 5
+ GPIO5_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 128));
+ }
+ else
+ {
+ // Port 6
+ GPIO6_REG(GPIO_DATAOUT) |= (1 << (gpio_bit - 160));
+ }
+ return 0;
+}
+
+//--------------------------------------------------------
+// GPIO_clr()
+//
+// This function clears the desired bit passed in.
+//
+
+int GPIO_clr(int gpio_bit)
+{
+#ifdef GPIO_DBG
+ printf("GPIO_clr %d.\n", gpio_bit);
+#endif
+ // quick sanity test
+ if (gpio_bit > 191) return -1;
+
+ if (gpio_bit < 32)
+ {
+ // Port 1
+ GPIO1_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 0));
+ }
+ else if (gpio_bit < 64)
+ {
+ // Port 2
+ GPIO2_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 32));
+ }
+ else if (gpio_bit < 96)
+ {
+ // Port 3
+ GPIO3_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 64));
+ }
+ else if (gpio_bit < 128)
+ {
+ // Port 4
+ GPIO4_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 96));
+ }
+ else if (gpio_bit < 160)
+ {
+ // Port 5
+ GPIO5_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 128));
+ }
+ else
+ {
+ // Port 6
+ GPIO6_REG(GPIO_DATAOUT) &= ~(1 << (gpio_bit - 160));
+ }
+ return 0;
+}
+//--------------------------------------------------------
+// GPIO_tst()
+//
+// This function returns the state of desired bit passed in.
+// It does not test to see if it's an input or output and thus
+// can be used to verify if an output set/clr has taken place
+// as well as for testing an input state.
+//
+
+int GPIO_tst(int gpio_bit)
+{
+#ifdef GPIO_DBG
+ printf("GPIO_tst %d.\n", gpio_bit);
+#endif
+ // quick sanity test
+ if (gpio_bit > 191) return -1;
+
+ if (gpio_bit < 32)
+ {
+ // Port 1
+ if (GPIO1_REG(GPIO_DATAIN) & (1 << (gpio_bit - 0))) return 1;
+ }
+ else if (gpio_bit < 64)
+ {
+ // Port 2
+ if (GPIO2_REG(GPIO_DATAIN) & (1 << (gpio_bit - 32))) return 1;
+ }
+ else if (gpio_bit < 96)
+ {
+ // Port 3
+ if (GPIO3_REG(GPIO_DATAIN) & (1 << (gpio_bit - 64))) return 1;
+ }
+ else if (gpio_bit < 128)
+ {
+ // Port 4
+ if (GPIO4_REG(GPIO_DATAIN) & (1 << (gpio_bit - 96))) return 1;
+ }
+ else if (gpio_bit < 160)
+ {
+ // Port 5
+ if (GPIO5_REG(GPIO_DATAIN) & (1 << (gpio_bit - 128))) return 1;
+ }
+ else
+ {
+ // Port 6
+ if (GPIO6_REG(GPIO_DATAIN) & (1 << (gpio_bit - 160))) return 1;
+ }
+ return 0; // bit was not set
+}
+
+//--------------------------------------------------------
+// GPIO_out()
+//
+// This function changes the direction of the desired bit
+// to output. NOTE: We do not test to see if changing the
+// direction of the bit would screw up anything. Use this
+// function with caution!
+//
+// This only worlks if the GPIO has been defined as a GPIO
+// during init. It will not override the init setting, only
+// change the direction bit
+
+int GPIO_out(int gpio_bit)
+{
+#ifdef GPIO_DBG
+ printf("GPIO_out %d.\n", gpio_bit);
+#endif
+ // quick sanity test
+ if (gpio_bit > 191) return -1;
+
+ if (gpio_bit < 32)
+ {
+ // Port 1
+ GPIO1_REG(GPIO_OE) &= ~(1 << (gpio_bit - 0));
+ }
+ else if (gpio_bit < 64)
+ {
+ // Port 2
+ GPIO2_REG(GPIO_OE) &= ~(1 << (gpio_bit - 32));
+ }
+ else if (gpio_bit < 96)
+ {
+ // Port 3
+ GPIO3_REG(GPIO_OE) &= ~(1 << (gpio_bit - 64));
+ }
+ else if (gpio_bit < 128)
+ {
+ // Port 4
+ GPIO4_REG(GPIO_OE) &= ~(1 << (gpio_bit - 96));
+ }
+ else if (gpio_bit < 160)
+ {
+ // Port 5
+ GPIO5_REG(GPIO_OE) &= ~(1 << (gpio_bit - 128));
+ }
+ else
+ {
+ // Port 6
+ GPIO6_REG(GPIO_OE) &= ~(1 << (gpio_bit - 160));
+ }
+ return 0;
+}
+
+//--------------------------------------------------------
+// GPIO_in()
+//
+// This function changes the direction of the desired bit
+// to input. NOTE: We do not test to see if changing the
+// direction of the bit would screw up anything. Use this
+// function with caution!
+//
+// This only worlks if the GPIO has been defined as a GPIO
+// during init. It will not override the init setting, only
+// change the direction bit
+int GPIO_in(int gpio_bit)
+{
+#ifdef GPIO_DBG
+ printf("GPIO_in %d.\n", gpio_bit);
+#endif
+ // quick sanity test
+ if (gpio_bit > 191) return -1;
+
+ if (gpio_bit < 32)
+ {
+ // Port 1
+ GPIO1_REG(GPIO_OE) |= (1 << (gpio_bit - 0));
+ }
+ else if (gpio_bit < 64)
+ {
+ // Port 2
+ GPIO2_REG(GPIO_OE) |= (1 << (gpio_bit - 32));
+ }
+ else if (gpio_bit < 96)
+ {
+ // Port 3
+ GPIO3_REG(GPIO_OE) |= (1 << (gpio_bit - 64));
+ }
+ else if (gpio_bit < 128)
+ {
+ // Port 4
+ GPIO4_REG(GPIO_OE) |= (1 << (gpio_bit - 96));
+ }
+ else if (gpio_bit < 160)
+ {
+ // Port 5
+ GPIO5_REG(GPIO_OE) |= (1 << (gpio_bit - 128));
+ }
+ else
+ {
+ // Port 6
+ GPIO6_REG(GPIO_OE) |= (1 << (gpio_bit - 160));
+ }
+ return 0;
+}
+
diff --git a/ports/beagleboneblack/omap3530_iomux.c b/ports/beagleboneblack/omap3530_iomux.c
new file mode 100644
index 0000000..586ac48
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_iomux.c
@@ -0,0 +1,530 @@
+//mx31_iomux.c
+
+#include "config.h"
+#include "cpuio.h"
+#include "stddefs.h"
+#include "genlib.h"
+#include "omap3530.h"
+#include "omap3530_iomux.h"
+#include "cpu_gpio.h" // pull in target board specific header
+
+void iomux_init()
+{
+
+// Initialization of GPR for CSB733
+IOMUX_CTL_REG(GENERAL_REGISTER) = WEIM_ON_CS3_EN | CSPI1_ON_UART_EN;
+
+// MX31_PIN_TTM_PAD = can not be written to.
+// cspi_miso = U2_RXD, cspi3_sclk = U2_RTS, cspi3_spi_rdy = U2_CTS, ttm_pad = default
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
+ | MX31_PIN_CSPI3_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
+ | MX31_PIN_CSPI3_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE));
+// | MX31_PIN_TTM_PAD();
+
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO(0x20)
+// | MX31_PIN_CSPI3_SCLK(0x20)
+// | MX31_PIN_CSPI3_SPI_RDY(0x20);
+//// | MX31_PIN_TTM_PAD();
+
+// MX31_PIN_CLKSS and MX31_PIN_CE_CONTROL = can not be written to.
+// reset_b = NC, ce_control = default, ctl_clkss = default, cspi3_mosi = U2_RXD
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER2) = MX31_PIN_ATA_RESET_B((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_CE_CONTROL((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+// | MX31_PIN_CLKSS()
+ | MX31_PIN_CSPI3_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1));
+
+// ata_cs1 = NC, ata_dior = D_TXD, ata_diow = NC, ata, dmack = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER3) = MX31_PIN_ATA_CS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_ATA_DIOR((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
+ | MX31_PIN_ATA_DIOW((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_ATA_DMACK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// sd1_data1 = SD_D1, sd1_data2 = SD_D2, sd1_data3 = SD_D3, ata_cs0 = D_RXD
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER4) = MX31_PIN_SD1_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SD1_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SD1_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_ATA_CS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1));
+
+// d3_spl = NC, sd1_cmd = SD_CMD, sd1_clk - SD_CLK, sd1_data0 = SD_D0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER5) = MX31_PIN_D3_SPL((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SD1_CMD((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SD1_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_SD1_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// vsync3 = LCD_VSYNC, contrast = NC, d3_rev = NC, d3_cls = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER6) = MX31_PIN_VSYNC3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CONTRAST((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_D3_REV((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_D3_CLS((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// ser_rs = NC, par_rs = NC, write = NC, read = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER7) = MX31_PIN_SER_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_PAR_RS((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_WRITE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_READ((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// sd_d_io = NC, sd_d_clk = NC, lcs0 = NC, lcs1 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER8) = MX31_PIN_SD_D_IO((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SD_D_CLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_LCS0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_LCS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// hsync = LCD_HSYNC, fpshift = LCD_PCLK, drdy0 = LCD_OE, sd_d_i = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER9) = MX31_PIN_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_FPSHIFT((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_DRDY0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SD_D_I((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// ld15 = LCD_R3, ld16 = LCD_R4, ld17 = LCD_R5, sd_d_i = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER10) = MX31_PIN_LD15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_VSYNC0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// ld11 = LCD_G5, ld12 = LCD_R0, ld13 = LCD_R1, ld14 = LCD_R2
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER11) = MX31_PIN_LD11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// ld7 = LCD_G1, ld8 = LCD_G2, ld9 = LCD_G3, ld10 = LCD_G4
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER12) = MX31_PIN_LD7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// ld3 = LCD_B3, ld4 = LCD_B4, ld5 = LCD_B5, ld6 = LCD_G0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER13) = MX31_PIN_LD3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usbh2_data1 = UH2_D1, ld0 = LCD_B0, ld1 = LCD_B1, ld2 = LCD_B0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER14) = MX31_PIN_USBH2_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_LD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usbh2_dir = UH2_DIR, usbh2_stp = UH2_STP, usbh2_nxt = UH2_NXT, usbh2_data0 = UH2_D0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER15) = MX31_PIN_USBH2_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_USBH2_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBH2_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBH2_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usbotg_data5 = UD_D5, usbotg_data6 = UD_D6, usbotg_data7 = UD_D7, usbh2_clk = UH2_CLK
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER16) = MX31_PIN_USBOTG_DATA5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBH2_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usbotg_data1 = UD_D1, usbotg_data2 = UD_D2, usbotg_data3 = UD_D3, usbotg_data4 = UD_D4
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER17) = MX31_PIN_USBOTG_DATA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usbotg_dir = UD_DIR, usbotg_stp = UD_STP, usbotg_nxt = UD_NXT, usbotg_data0 = UD_D0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER18) = MX31_PIN_USBOTG_DIR((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_STP((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_USBOTG_NXT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_USBOTG_DATA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// usb_pwr = NC, usb_oc = CF_RST, usb_byp = NC, usbotg_clk = UD_CLK
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER19) = MX31_PIN_USB_PWR((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_USB_OC((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_USB_BYP((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_USBOTG_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// MX31_PIN_TDO and MX31_PIN_SJC_MOD = can not be written to
+// tdo = TDO_C, trstb = TRST_C, de_b = TP1, sjc_mod = GND
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TDO()
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TRSTB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_DE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+// | MX31_PIN_SJC_MOD();
+
+// MX31_PIN_RTCK = can not be written to.
+// rtck = NC, tck = TCK_C, tms = TMS_C, tdi = TDI_C
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_RTCK()
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_TCK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_TMS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_TDI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// key_col4 = NC, key_col5 = NC, key_col6 = NC, key_col7 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER22) = MX31_PIN_KEY_COL4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_COL5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_COL6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_COL7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// key_col0 = NC, key_col1 = NC, key_col2 = NC, key_col3 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER23) = MX31_PIN_KEY_COL0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_COL1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_COL2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_COL3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// key_row4 = NC, key_row5 = NC, key_row6 = NC, key_row7 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER24) = MX31_PIN_KEY_ROW4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_ROW5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_ROW6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_KEY_ROW7((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// key_row0 = NC, key_row1 = NC, key_row2 = NC, key_row3 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER25) = MX31_PIN_KEY_ROW0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_ROW1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_ROW2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_KEY_ROW3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// txd2 = U1_TXD, rts2 = U1_RTS, cts2 = U1_CTS, batt_line = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER26) = MX31_PIN_TXD2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_RTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CTS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_BATT_LINE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// ri_dte1, dcd_dte1, and dtr_dce2 are set to CSPI1 signals by GPR(2)
+// rxd2 = U1_RXD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RI_DTE1()
+// | MX31_PIN_DCD_DTE1()
+// | MX31_PIN_DTR_DCE2()
+// | MX31_PIN_RXD2(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC);
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RXD2((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC));
+
+// dtr_dte1 and dsr_dte1 are set to CSPI1 signals by GPR(2)
+// ri_dce1 = SPI0_RDY, dcd_dce1 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER28) = MX31_PIN_RI_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_DCD_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+// | MX31_PIN_DTR_DTE1()
+// | MX31_PIN_DSR_DTE1();
+
+// rts1 = U0_RTS, cts1 = U0_CTS, dtr_dce1 = NC, dsr_dce1 = SPI0_CLK
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER29) = MX31_PIN_RTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CTS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_DTR_DCE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_DSR_DCE1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
+
+// cspi2_sclk = SPI1_CLK, cspi2_spi_rdy = SPI1_RDY, rxd1 = U0_RXD, txd1 = U0_TXD
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER30) = MX31_PIN_CSPI2_SCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSPI2_SPI_RDY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_RXD1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
+ | MX31_PIN_TXD1((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE));
+
+// cspi2_miso = SPI1_MISO, cspi2_ss0 = SPI1_CS0, cspi2_ss1 = SPI1_CS1, cspi2_ss2 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER31) = MX31_PIN_CSPI2_MISO((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSPI2_SS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSPI2_SS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSPI2_SS2((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// cspi1_ss2 = UH1_RCV, cspi1_sclk = UH1_OE, cspi1_spi_rdy = UH1_FS, cspi2_mosi = SPI1_MOSI
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER32) = MX31_PIN_CSPI1_SS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_CSPI1_SCLK((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_CSPI1_SPI_RDY((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_CSPI2_MOSI((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// cspi1_mosi = UH1_RXDM, cspi1_miso = UH1_RXDP, cspi1_ss0 = UH1_TXDM, cspi1_ss1 = UH1_TXDP
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER33) = MX31_PIN_CSPI1_MOSI((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1))
+ | MX31_PIN_CSPI1_MISO((OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1))
+ | MX31_PIN_CSPI1_SS0((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
+ | MX31_PIN_CSPI1_SS1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE));
+
+// stxd6 = AC_SDOUT, srxd6 = AC_SDIN, sck6 = AC_BCLK, sfs6 = AC_SYNC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER34) = MX31_PIN_STXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SRXD6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SCK6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SFS6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// stxd5 = SSI_TXD, srxd5 = SSI_RXD, sck5 = SSI_CLK, sfs5 = SSI_FRM
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER35) = MX31_PIN_STXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SRXD5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SCK5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SFS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// stxd4 = NC, srxd4 = NC, sck4 = SSI_MCLK, sfs4 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER36) = MX31_PIN_STXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SRXD4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SCK4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SFS4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// stxd3 = AC_RST, srxd3 = NC, sck3 = NC, sfs3 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER37) = MX31_PIN_STXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_SRXD3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SCK3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_SFS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// csi_hsync = VIP_HSYNC, csi_pixclk = VIP_PCLK, i2c_clk = I2C_SCL, i2c_dat = I2C_SDA
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER38) = MX31_PIN_CSI_HSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_PIXCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_I2C_CLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_I2C_DAT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// csi_d14 = VIP_D8, csi_d15 = VIP_D9, csi_mclk = VIP_MCLK, csi_vsync = VIP_VSYNC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER39) = MX31_PIN_CSI_D14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_MCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE))
+ | MX31_PIN_CSI_VSYNC((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// csi_d10 = VIP_D4, csi_d11 = VIP_D5, csi_D12 = VIP_D6, csi_D13 = VIP_D7
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER40) = MX31_PIN_CSI_D10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// csi_d6 = VIP_D0, csi_d7 = VIP_D1, csi_D8 = VIP_D2, csi_D9 = VIP_D3
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER41) = MX31_PIN_CSI_D6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// m_request = NC, m_grant = NC, csi_d4 = NC, csi_d5 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER42) = MX31_PIN_M_REQUEST((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_M_GRANT((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CSI_D4((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_CSI_D5((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// pc_rst = UH2_D5, isis16 = UH2_D6, pc_rw_b = UH2_D7, pc_poe = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER43) = MX31_PIN_PC_RST((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_IOIS16((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_PC_RW_B((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_PC_POE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// pc_vs1 = NC, pc_vs2 = UH2_D2, pc_bvd1 = UH2_D3, pc_bvd2 = UH2_D4
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER44) = MX31_PIN_PC_VS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_PC_VS2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_PC_BVD1((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1))
+ | MX31_PIN_PC_BVD2((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
+
+// pc_cd2_b = CF_CD, pc_wait_b = CF_WAIT, pc_ready = CF_RDY, pc_pwron = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER45) = MX31_PIN_PC_CD2_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_PC_WAIT_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_PC_READY((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_PC_PWRON((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// d2, d1, and d0 are not writable, reset values are correct.
+// d2 = LD2, d1 = LD1, d0 = LD0, pc_cd1_b = CF_CD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER46) = MX31_PIN_D2()
+// | MX31_PIN_D1()
+// | MX31_PIN_D0()
+// | MX31_PIN_PC_CD1_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+
+// d6, d5, d4 and d3 are not writable, reset values are correct.
+// d6 = LD6, d5 = LD5, d4 = LD4, d3 = LD3
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER47) = MX31_PIN_D6()
+// | MX31_PIN_D5()
+// | MX31_PIN_D4()
+// | MX31_PIN_D3();
+
+// d10, d9, d8 and d7 are not writable, reset values are correct.
+// d10 = LD10, d9 = LD9, d8 = LD8, d7 = LD7
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER48) = MX31_PIN_D10()
+// | MX31_PIN_D9()
+// | MX31_PIN_D8()
+// | MX31_PIN_D7();
+
+// d14, d13, d12 and d11 are not writable, reset values are correct.
+// d14 = LD14, d13 = LD13, d12 = LD12, d11 = L11
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER49) = MX31_PIN_D14()
+// | MX31_PIN_D13()
+// | MX31_PIN_D12()
+// | MX31_PIN_D11();
+
+// d15 is not writable, reset value is correct.
+// nfwp_b = *N_WP, nfce_b = *N_CE, nfrb = N_RDY, d15 = LD15
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER50) = MX31_PIN_NFWP_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_NFCE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_NFRB((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+// | MX31_PIN_D15();
+
+// nfwe_b = *N_WE, nfre_b = *N_RE, nfale = N_ALE, nfcle = N_CLE
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER51) = MX31_PIN_NFWE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_NFRE_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_NFALE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_NFCLE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// sdqs0, sdqs1, sdqs2, and sdqs3 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER52) = MX31_PIN_SDQS0()
+// | MX31_PIN_SDQS1()
+// | MX31_PIN_SDQS2()
+// | MX31_PIN_SDQS3();
+
+// sdclk_b is not writable, reset value is correct.
+// sdcke0 = SDCKE, sdcke1 = NC, sdclk = SDCLK, sdclk_b = *SDCLK
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER53) = MX31_PIN_SDCKE0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SDCKE1((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
+ | MX31_PIN_SDCLK((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+// | MX31_PIN_SDCLK_B();
+
+// rw = *WE, ras = *SDRAS, cas = *SDCAS, sdwe = *SDWE
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER54) = MX31_PIN_RW((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_RAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CAS((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SDWE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// ecb is not writable, reset value is correct.
+// cs5 = *CS5, ecb = ECB, lba = LBA, bclk = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER55) = MX31_PIN_CS5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+// | MX31_PIN_ECB()
+ | MX31_PIN_LBA((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_BCLK((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// cs1 = *CS1, cs2 = *SDCS, cs3 = NC, cs4 = *DTACK
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER56) = MX31_PIN_CS1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CS2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CS3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_CS4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1));
+
+// eb0 = *BE0, eb1 = *BE1, oe = *OE, cs0 = *CS0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER57) = MX31_PIN_EB0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_EB1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_OE((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_CS0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// dqm0 = DQM0, dqm1 = DQM1, dqm2 = DQM2, dqm3 = DQM3
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER58) = MX31_PIN_DQM0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_DQM1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_DQM2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_DQM3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// sd28, sd29, sd30 and sd31 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER59) = MX31_PIN_SD28()
+// | MX31_PIN_SD29()
+// | MX31_PIN_SD30()
+// | MX31_PIN_SD31();
+
+// sd24, sd25, sd26 and sd27 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER60) = MX31_PIN_SD24()
+// | MX31_PIN_SD25()
+// | MX31_PIN_SD26()
+// | MX31_PIN_SD27();
+
+// sd20, sd21, sd22 and sd23 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER61) = MX31_PIN_SD20()
+// | MX31_PIN_SD21()
+// | MX31_PIN_SD22()
+// | MX31_PIN_SD23();
+
+// sd16, sd17, sd18 and sd19 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER62) = MX31_PIN_SD16()
+// | MX31_PIN_SD17()
+// | MX31_PIN_SD18()
+// | MX31_PIN_SD19();
+
+// sd12, sd13, sd14 and sd15 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER63) = MX31_PIN_SD12()
+// | MX31_PIN_SD13()
+// | MX31_PIN_SD14()
+// | MX31_PIN_SD15();
+
+// sd8, sd9, sd10 and sd11 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER64) = MX31_PIN_SD8()
+// | MX31_PIN_SD9()
+// | MX31_PIN_SD10()
+// | MX31_PIN_SD11();
+
+// sd4, sd5, sd6 and sd7 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER65) = MX31_PIN_SD4()
+// | MX31_PIN_SD5()
+// | MX31_PIN_SD6()
+// | MX31_PIN_SD7();
+
+// sd0, sd1, sd2 and sd3 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER66) = MX31_PIN_SD0()
+// | MX31_PIN_SD1()
+// | MX31_PIN_SD2()
+// | MX31_PIN_SD3();
+
+// a24 = A24, a25 = A25, sdba1 = SDBA1, sdba0 = SDBA0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER67) = MX31_PIN_A24((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A25((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SDBA1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_SDBA0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER68) = MX31_PIN_A20((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A21((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A22((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A23((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER69) = MX31_PIN_A16((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A17((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A18((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A19((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER70) = MX31_PIN_A12((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A13((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A14((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A15((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER71) = MX31_PIN_A9((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_MA10((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A11((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER72) = MX31_PIN_A5((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A6((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A7((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A8((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// address lines are one to one.
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER73) = MX31_PIN_A1((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A2((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A3((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC))
+ | MX31_PIN_A4((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// dvfs1 = NC, vpg0 = NC, vpg1 = NC, a0 = A0
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER74) = MX31_PIN_DVFS1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_VPG0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_VPG1((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_A0((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+
+// ckil and power_fail are not writable, reset values are correct.
+//ckil = 32K, power_fail = PWR_FAIL, vstby = VSTBY, dvfs0 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER75) = MX31_PIN_CKIL()
+// | MX31_PIN_POWER_FAIL()
+// | MX31_PIN_VSTBY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DVFS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+
+// boot_mode1, boot_mode2, boot_mode3, and boot_mode4 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER76) = MX31_PIN_BOOT_MODE1()
+// | MX31_PIN_BOOT_MODE2()
+// | MX31_PIN_BOOT_MODE3()
+// | MX31_PIN_BOOT_MODE4();
+
+// por_b, clko, and boot_mode0 are not writable, reset values are correct.
+// reset_in_b = *RST_IN (this is set in the GPR)
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER77) = MX31_PIN_RESET_IN_B((OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC));
+// | MX31_PIN_POR_B()
+// | MX31_PIN_CLKO()
+// | MX31_PIN_BOOT_MODE0();
+
+// ckih is not writable, reset value is correct.
+// stx0 = GPIO1, srx0 = GPIO4, simpd0 = GPIO5
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER78) = MX31_PIN_STX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SRX0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SIMPD0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+// | MX31_PIN_CKIH();
+
+// gpio3_1 = VF_EN, sclk0 = GPIO8, srst0 = GPIO9, sven0 = GPIO0 (USR_LED)
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER79) = MX31_PIN_GPIO3_1((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE))
+ | MX31_PIN_SCLK0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SRST0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_SVEN0((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+
+// gpio1_4 = UH1_SUSP, gpio1_5 = PWR_RDY, gpio1_6 = UH1_MODE, gpio3_0 = NC
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER80) = MX31_PIN_GPIO1_4((OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE))
+ | MX31_PIN_GPIO1_5((OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC))
+ | MX31_PIN_GPIO1_6((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_GPIO3_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// gpio1_0 = *PIRQ, gpio1_1 = *E_INT, gpio1_2 = *EXP_INT, gpio1_3 = *I2C_INT
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER81) = MX31_PIN_GPIO1_0((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_GPIO1_1((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO))
+ | MX31_PIN_GPIO1_2((OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO))
+ | MX31_PIN_GPIO1_3((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO));
+
+// capture = GPIO2, compare = GPIO3, watchdog_rst = NC, pwm0 = LCD_BKL
+IOMUX_CTL_REG(SW_MUX_CTL_REGISTER82) = MX31_PIN_CAPTURE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_COMPARE((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_WATCHDOG_RST((OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO))
+ | MX31_PIN_PWMO((OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE));
+}
diff --git a/ports/beagleboneblack/omap3530_iomux.h b/ports/beagleboneblack/omap3530_iomux.h
new file mode 100644
index 0000000..f424664
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_iomux.h
@@ -0,0 +1,1077 @@
+//==========================================================================
+//
+// mx31_gpio.h
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 05/02/2008
+// Description: This file contains offsets and bit defines
+// for the MCIMX31 Software Multiplexor Control Register
+//
+
+#include "omap3530.h"
+#include "bits.h"
+
+// Base address for Software Multiplexor Control Register (SW_MUX_CTL).
+// The SW_MUX_CTL has 82 seperate registers each of which contains 4
+// seperate Control Signals. So we have to write to a total of 328
+// different signals in order to set-up the MX31 to run on the Cogent platform.
+#define IOMUXC_BASE_ADDR 0x43FAC000
+#define IOMUX_CTL_REG(_x_) *(vulong *)(IOMUXC_BASE_ADDR + _x_)
+
+#define GENERAL_REGISTER 0x008
+#define SW_MUX_CTL_REGISTER1 0x00C // Contains cspi3_miso, cspi3_sclk, sspi3_spi_rdy, and ttm_pad
+#define SW_MUX_CTL_REGISTER2 0x010 // Contains ata_reset_b, ce_control, clkss, and cspi3_mosi
+#define SW_MUX_CTL_REGISTER3 0x014 // Contains ata_cs1, ata_dior, ata_diow, and ata_dmack
+#define SW_MUX_CTL_REGISTER4 0x018 // Contains sd1_data1, sd1_data2, sd1_data3, and ata_cs0
+#define SW_MUX_CTL_REGISTER5 0x01C // Contains d3_spl, sd1_cmd, sd1_clk, and sd1_data0
+#define SW_MUX_CTL_REGISTER6 0x020 // Contains vsync3, contrast, d3_rev, and d3_cls
+#define SW_MUX_CTL_REGISTER7 0x024 // Contains ser_rs, par_rs, write, and read
+#define SW_MUX_CTL_REGISTER8 0x028 // Contains sd_d_io, sd_d_clk, lcs0, and lcs1
+#define SW_MUX_CTL_REGISTER9 0x02C // Contains hsync, fpshift, drdy0, and sd_d_i
+#define SW_MUX_CTL_REGISTER10 0x030 // Contains ld15, ld16, ld17, and vsync0
+#define SW_MUX_CTL_REGISTER11 0x034
+#define SW_MUX_CTL_REGISTER12 0x038
+#define SW_MUX_CTL_REGISTER13 0x03C
+#define SW_MUX_CTL_REGISTER14 0x040
+#define SW_MUX_CTL_REGISTER15 0x044
+#define SW_MUX_CTL_REGISTER16 0x048
+#define SW_MUX_CTL_REGISTER17 0x04C
+#define SW_MUX_CTL_REGISTER18 0x050
+#define SW_MUX_CTL_REGISTER19 0x054
+#define SW_MUX_CTL_REGISTER20 0x058
+#define SW_MUX_CTL_REGISTER21 0x05C
+#define SW_MUX_CTL_REGISTER22 0x060
+#define SW_MUX_CTL_REGISTER23 0x064
+#define SW_MUX_CTL_REGISTER24 0x068
+#define SW_MUX_CTL_REGISTER25 0x06C
+#define SW_MUX_CTL_REGISTER26 0x070
+#define SW_MUX_CTL_REGISTER27 0x074
+#define SW_MUX_CTL_REGISTER28 0x078
+#define SW_MUX_CTL_REGISTER29 0x07C
+#define SW_MUX_CTL_REGISTER30 0x080
+#define SW_MUX_CTL_REGISTER31 0x084
+#define SW_MUX_CTL_REGISTER32 0x088
+#define SW_MUX_CTL_REGISTER33 0x08C
+#define SW_MUX_CTL_REGISTER34 0x090
+#define SW_MUX_CTL_REGISTER35 0x094
+#define SW_MUX_CTL_REGISTER36 0x098
+#define SW_MUX_CTL_REGISTER37 0x09C
+#define SW_MUX_CTL_REGISTER38 0x0A0
+#define SW_MUX_CTL_REGISTER39 0x0A4
+#define SW_MUX_CTL_REGISTER40 0x0A8
+#define SW_MUX_CTL_REGISTER41 0x0AC
+#define SW_MUX_CTL_REGISTER42 0x0B0
+#define SW_MUX_CTL_REGISTER43 0x0B4
+#define SW_MUX_CTL_REGISTER44 0x0B8
+#define SW_MUX_CTL_REGISTER45 0x0BC
+#define SW_MUX_CTL_REGISTER46 0x0C0
+#define SW_MUX_CTL_REGISTER47 0x0C4
+#define SW_MUX_CTL_REGISTER48 0x0C8
+#define SW_MUX_CTL_REGISTER49 0x0CC
+#define SW_MUX_CTL_REGISTER50 0x0D0
+#define SW_MUX_CTL_REGISTER51 0x0D4
+#define SW_MUX_CTL_REGISTER52 0x0D8
+#define SW_MUX_CTL_REGISTER53 0x0DC
+#define SW_MUX_CTL_REGISTER54 0x0E0
+#define SW_MUX_CTL_REGISTER55 0x0E4
+#define SW_MUX_CTL_REGISTER56 0x0E8
+#define SW_MUX_CTL_REGISTER57 0x0EC
+#define SW_MUX_CTL_REGISTER58 0x0F0
+#define SW_MUX_CTL_REGISTER59 0x0F4
+#define SW_MUX_CTL_REGISTER60 0x0F8
+#define SW_MUX_CTL_REGISTER61 0x0FC
+#define SW_MUX_CTL_REGISTER62 0x100
+#define SW_MUX_CTL_REGISTER63 0x104
+#define SW_MUX_CTL_REGISTER64 0x108
+#define SW_MUX_CTL_REGISTER65 0x10C
+#define SW_MUX_CTL_REGISTER66 0x110
+#define SW_MUX_CTL_REGISTER67 0x114
+#define SW_MUX_CTL_REGISTER68 0x118
+#define SW_MUX_CTL_REGISTER69 0x11C
+#define SW_MUX_CTL_REGISTER70 0x120
+#define SW_MUX_CTL_REGISTER71 0x124
+#define SW_MUX_CTL_REGISTER72 0x128
+#define SW_MUX_CTL_REGISTER73 0x12C
+#define SW_MUX_CTL_REGISTER74 0x130
+#define SW_MUX_CTL_REGISTER75 0x134
+#define SW_MUX_CTL_REGISTER76 0x138
+#define SW_MUX_CTL_REGISTER77 0x13C
+#define SW_MUX_CTL_REGISTER78 0x140
+#define SW_MUX_CTL_REGISTER79 0x144
+#define SW_MUX_CTL_REGISTER80 0x148
+#define SW_MUX_CTL_REGISTER81 0x14C
+#define SW_MUX_CTL_REGISTER82 0x150
+
+// General Purpose Register Bit Defines
+#define DDR_MODE_ON_CLK0_EN BIT31 // 1 = Enable DDR mode on CLK0 contact
+#define USBH2_LOOPBACK_EN BIT30 // 1 = Turn on sw_input_on (loopback) on some USBH2 contacts
+#define USBH1_LOOPBACK_EN BIT29 // 1 = Turn on sw_input_on (loopback) on some USBH1 contacts
+#define USBOTG_LOOPBACK_EN BIT28 // 1 = Turn on sw_input_on (loopback) on some USBOTG contacts
+#define USBH1_SUS_ON_SFS6_EN BIT27 // 1 = Enable USBH1_SUSPEND signal on SFS6 contact
+#define ATA_ON_KEYPAD_EN BIT26 // 1 = Enable ATA signals on Keypad Group contacts
+#define UART5_DMA_REQ_EN BIT25 // Selects either CSPI3 or UART5 DMA requests for events 10 and 11, 1 = UART5, 0 = CSPI1
+#define SLEW_RATE_SEL BIT24 // 1 = Fast Slew Rate, 0 = Slow Slew Rate
+#define DRIVE_STRENGTH_SEL BIT23 // 1 = Maximum drive strength, 0 = standard or high drive strength
+#define UPLL_ON_GPIO3_1_EN BIT22 // 1 = Enable UPLL clock bypass through GPIO3_1 contact
+#define SPLL_ON_GPIO3_0_EN BIT21 // 1 = Enable SPLL clock bypass through GPIO3_0 contact
+#define MSHC2_DMA_REQ_EN BIT20 // Selects either SDHC2 or MSHC2 DMA requests, 1 = MSCHC2, 0 = SDHC2
+#define MSHC1_DMA_REQ_EN BIT19 // Selects either SDHC1 or MSHC1 DMA requests, 1 = MSCHC1, 0 = SDHC1
+#define OTG_DATA_ON_UART_EN BIT18 // 1 = Enable USBOTG_DATA[5:3] on Full UART Group contacts
+#define OTG_D4_ON_DSR_DCE1_EN BIT17 // 1 = Enable USBOTG_DATA4 on DSR_DCE1 contact
+#define TAMPER_DETECT_EN BIT16 // 1 = Enable Tamper detect logic
+#define MBX_DMA_REQ_EN BIT15 // Selects either External or MBX DMA requests, 1 = MDX, 0 = External
+#define UART_DMA_REQ_EN BIT14 // Selects either CSPI1 or UART3 DMA requests, 1 = UART3, 0 = CSPI1
+#define WEIM_ON_CS3_EN BIT13 // Selects either CSD1 or WEIM on EMI CS3 contact, 1 = CSD1, 0 = WEIM
+#define WEIM_ON_CS2_EN BIT12 // Selects either CSD0 or WEIM on EMI CS2 contact, 1 = CSD0, 0 = WEIM
+#define USBH2_ON_AUDIO_EN BIT11 // 1 = Enable USBH2 signals on AudioPort 3 and AudioPort6
+#define ATA_SIG_ON_CSPI1_EN BIT10 // 1 = Enable ATA signals on CSPI1 Group contacts
+#define ATA_DATA_ON_CSPI1_EN BIT9 // 1 = Enable ATA DATA14-15 on Timer Group contacts and DATA0-6 on CSPI1 Group contacts
+#define ATA_DATA_ON_AUDIO_EN BIT8 // 1 = Enable DATA7-10 signals of ATA on AudioPort3 and DATA11-13 on AudioPort6
+#define ATA_DATA_ON_IPU_EN BIT7 // 1 = Enable DATA0-13 signals of ATA on IPU (CSI) and DATA14-15 on I2C
+#define ATA_SIG_ON_NANDF_EN BIT6 // 1 = Enable ATA signals on NANF contacts
+#define ATA_DATA_ON_NANDF_EN BIT5 // 1 = Enable ATA DATA7-13 on NANDF contacts
+#define ATA_ON_USBH2_EN BIT4 // 1 = Enable ATA signals on USBH2 contacts
+#define PWMO_ON_ATA_IORDY_EN BIT3 // 1 = Enable ATA IORDY signal on PWMO contact
+#define CSPI1_ON_UART_EN BIT2 // 1 = Replaces Full UART Group with CSPI1 signals
+#define DDR_MODE_EN BIT1 // 1 = Forces DDR type I/O contacts to DDR mode
+#define FIR_DMA_REQ_EN BIT0 // Selects FIR or UART2 SDMA events, 1 = FIR, 0 = UART2
+
+// Initialization of GPR for CSB733
+//IOMUX_CTL_REG(GENERAL_REGISTER) = WEIM_ON_CS3_EN | CSPI1_ON_UART_EN;
+
+// various IOMUX output functions
+#define OUTPUTCONFIG_GPIO 0x00 // used as GPIO
+#define OUTPUTCONFIG_FUNC 0x10 // output used as function
+#define OUTPUTCONFIG_ALT1 0x20 // output used as alternate function 1
+#define OUTPUTCONFIG_ALT2 0x30 // output used as alternate function 2
+#define OUTPUTCONFIG_ALT3 0x40 // output used as alternate function 3
+#define OUTPUTCONFIG_ALT4 0x50 // output used as alternate function 4
+#define OUTPUTCONFIG_ALT5 0x60 // output used as alternate function 5
+#define OUTPUTCONFIG_ALT6 0x70 // output used as alternate function 6
+
+// various IOMUX input functions
+#define INPUTCONFIG_NONE 0x00 // not configured for input
+#define INPUTCONFIG_GPIO 0x01 // input used as GPIO
+#define INPUTCONFIG_FUNC 0x02 // input used as function
+#define INPUTCONFIG_ALT1 0x04 // input used as alternate function 1
+#define INPUTCONFIG_ALT2 0x08 // input used as alternate function 2
+
+// Software Mux Control Signal Defines (SW_MUX_CTL_SIGNAL 1-4)
+#define MX31_PIN_CSPI3_MISO(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSPI3_SCLK(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSPI3_SPI_RDY(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_TTM_PAD(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_ATA_RESET_B(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CE_CONTROL(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CLKSS(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSPI3_MOSI(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_ATA_CS1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_ATA_DIOR(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_ATA_DIOW(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_ATA_DMACK(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD1_DATA1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD1_DATA2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD1_DATA3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_ATA_CS0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_D3_SPL(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD1_CMD(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD1_CLK(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD1_DATA0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_VSYNC3(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CONTRAST(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_D3_REV(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_D3_CLS(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SER_RS(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_PAR_RS(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_WRITE(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_READ(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD_D_IO(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD_D_CLK(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LCS0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_LCS1(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_HSYNC(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_FPSHIFT(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DRDY0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD_D_I(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_LD15(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_LD16(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LD17(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_VSYNC0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_LD11(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_LD12(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LD13(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_LD14(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_LD7(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_LD8(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LD9(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_LD10(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_LD3(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_LD4(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LD5(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_LD6(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USBH2_DATA1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_LD0(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LD1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_LD2(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USBH2_DIR(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_USBH2_STP(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_USBH2_NXT(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_USBH2_DATA0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USBOTG_DATA5(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_USBOTG_DATA6(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_USBOTG_DATA7(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_USBH2_CLK(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USBOTG_DATA1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_USBOTG_DATA2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_USBOTG_DATA3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_USBOTG_DATA4(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USBOTG_DIR(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_USBOTG_STP(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_USBOTG_NXT(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_USBOTG_DATA0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_USB_PWR(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_USB_OC(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_USB_BYP(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_USBOTG_CLK(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_TDO(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_TRSTB(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DE_B(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SJC_MOD(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RTCK(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_TCK(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_TMS(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_TDI(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_KEY_COL4(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_KEY_COL5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_KEY_COL6(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_KEY_COL7(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_KEY_COL0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_KEY_COL1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_KEY_COL2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_KEY_COL3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_KEY_ROW4(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_KEY_ROW5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_KEY_ROW6(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_KEY_ROW7(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_KEY_ROW0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_KEY_ROW1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_KEY_ROW2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_KEY_ROW3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_TXD2(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_RTS2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CTS2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_BATT_LINE(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RI_DTE1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_DCD_DTE1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DTR_DCE2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_RXD2(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RI_DCE1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_DCD_DCE1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DTR_DTE1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_DSR_DTE1(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RTS1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CTS1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DTR_DCE1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_DSR_DCE1(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSPI2_SCLK(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSPI2_SPI_RDY(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_RXD1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_TXD1(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSPI2_MISO(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSPI2_SS0(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSPI2_SS1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSPI2_SS2(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSPI1_SS2(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSPI1_SCLK(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSPI1_SPI_RDY(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSPI2_MOSI(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSPI1_MOSI(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSPI1_MISO(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSPI1_SS0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSPI1_SS1(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_STXD6(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SRXD6(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SCK6(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SFS6(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_STXD5(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SRXD5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SCK5(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SFS5(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_STXD4(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SRXD4(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SCK4(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SFS4(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_STXD3(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SRXD3(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SCK3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SFS3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSI_HSYNC(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSI_PIXCLK(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_I2C_CLK(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_I2C_DAT(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSI_D14(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSI_D15(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSI_MCLK(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSI_VSYNC(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSI_D10(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSI_D11(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSI_D12(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSI_D13(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CSI_D6(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CSI_D7(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSI_D8(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSI_D9(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_M_REQUEST(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_M_GRANT(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CSI_D4(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CSI_D5(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_PC_RST(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_IOIS16(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_PC_RW_B(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_PC_POE(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_PC_VS1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_PC_VS2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_PC_BVD1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_PC_BVD2(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_PC_CD2_B(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_PC_WAIT_B(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_PC_READY(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_PC_PWRON(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_D2(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_D1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_D0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_PC_CD1_B(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_D6(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_D5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_D4(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_D3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_D10(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_D9(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_D8(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_D7(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_D14(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_D13(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_D12(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_D11(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_NFWP_B(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_NFCE_B(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_NFRB(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_D15(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_NFWE_B(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_NFRE_B(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_NFALE(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_NFCLE(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SDQS0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SDQS1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SDQS2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SDQS3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SDCKE0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SDCKE1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SDCLK(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SDCLK_B(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RW(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_RAS(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CAS(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SDWE(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CS5(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_ECB(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_LBA(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_BCLK(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CS1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_CS2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CS3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CS4(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_EB0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_EB1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_OE(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CS0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_DQM0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_DQM1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_DQM2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_DQM3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD28(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD29(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD30(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD31(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD24(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD25(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD26(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD27(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD20(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD21(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD22(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD23(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD16(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD17(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD18(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD19(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD12(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD13(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD14(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD15(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD8(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD9(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD10(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD11(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD4(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD6(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD7(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_SD0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SD1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SD2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SD3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A24(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A25(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SDBA1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SDBA0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A20(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A21(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_A22(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A23(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A16(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A17(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_A18(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A19(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A12(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A13(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_A14(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A15(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A9(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A10(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_MA10(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A11(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A5(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A6(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_A7(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A8(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_A1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_A2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_A3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A4(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_DVFS1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_VPG0(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_VPG1(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_A0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CKIL(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_POWER_FAIL(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_VSTBY(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_DVFS0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_BOOT_MODE1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_BOOT_MODE2(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_BOOT_MODE3(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_BOOT_MODE4(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_RESET_IN_B(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_POR_B(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_CLKO(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_BOOT_MODE0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_STX0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SRX0(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SIMPD0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_CKIH(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_GPIO3_1(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_SCLK0(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_SRST0(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_SVEN0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_GPIO1_4(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_GPIO1_5(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_GPIO1_6(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_GPIO3_0(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_GPIO1_0(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_GPIO1_1(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_GPIO1_2(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_GPIO1_3(_x_) ((_x_ & 0xff) << 0)
+
+#define MX31_PIN_CAPTURE(_x_) ((_x_ & 0xff) << 24)
+#define MX31_PIN_COMPARE(_x_) ((_x_ & 0xff) << 16)
+#define MX31_PIN_WATCHDOG_RST(_x_) ((_x_ & 0xff) << 8)
+#define MX31_PIN_PWMO(_x_) ((_x_ & 0xff) << 0)
+
+//// MX31_PIN_TTM_PAD = can not be written to.
+//// cspi_miso = U2_RXD, cspi3_sclk = U2_RTS, cspi3_spi_rdy = U2_CTS, ttm_pad = default
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER1) = MX31_PIN_CSPI3_MISO(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_CSPI3_SCLK(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_CSPI3_SPI_RDY(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_TTM_PAD();
+//
+//// MX31_PIN_CLKSS and MX31_PIN_CE_CONTROL = can not be written to.
+//// reset_b = NC, ce_control = default, ctl_clkss = default, cspi3_mosi = U2_RXD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER2) = MX31_PIN_ATA_RESET_B(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_CE_CONTROL(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CLKSS()
+// | MX31_PIN_CSPI3_MOSI(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT2);
+//
+//// ata_cs1 = NC, ata_dior = D_TXD, ata_diow = NC, ata, dmack = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER3) = MX31_PIN_ATA_CS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_ATA_DIOR(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_ATA_DIOW(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_ATA_DMACK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// sd1_data1 = SD_D1, sd1_data2 = SD_D2, sd1_data3 = SD_D3, ata_cs0 = D_RXD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER4) = MX31_PIN_SD1_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SD1_DATA2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SD1_DATA3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_ATA_CS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1);
+//
+//// d3_spl = NC, sd1_cmd = SD_CMD, sd1_clk - SD_CLK, sd1_data0 = SD_D0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER5) = MX31_PIN_D3_SPL(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SD1_CMD(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SD1_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_SD1_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// vsync3 = LCD_VSYNC, contrast = NC, d3_rev = NC, d3_cls = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER6) = MX31_PIN_VSYNC3(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_CONTRAST(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_D3_REV(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_D3_CLS(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
+//
+//// ser_rs = NC, par_rs = NC, write = NC, read = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER7) = MX31_PIN_SER_RS(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_PAR_RS(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_WRITE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_READ(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// sd_d_io = NC, sd_d_clk = NC, lcs0 = NC, lcs1 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER8) = MX31_PIN_SD_D_IO(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SD_D_CLK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_LCS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_LCS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// hsync = LCD_HSYNC, fpshift = LCD_PCLK, drdy0 = LCD_OE, sd_d_i = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER9) = MX31_PIN_HSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_FPSHIFT(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_DRDY0(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_SD_D_I(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// ld15 = LCD_R3, ld16 = LCD_R4, ld17 = LCD_R5, sd_d_i = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER10) = MX31_PIN_LD15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD16(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD17(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_VSYNC0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// ld11 = LCD_G5, ld12 = LCD_R0, ld13 = LCD_R1, ld14 = LCD_R2
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER11) = MX31_PIN_LD11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// ld7 = LCD_G1, ld8 = LCD_G2, ld9 = LCD_G3, ld10 = LCD_G4
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER12) = MX31_PIN_LD7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// ld3 = LCD_B3, ld4 = LCD_B4, ld5 = LCD_B5, ld6 = LCD_G0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER13) = MX31_PIN_LD3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usbh2_data1 = UH2_D1, ld0 = LCD_B0, ld1 = LCD_B1, ld2 = LCD_B0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER14) = MX31_PIN_USBH2_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_LD2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usbh2_dir = UH2_DIR, usbh2_stp = UH2_STP, usbh2_nxt = UH2_NXT, usbh2_data0 = UH2_D0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER15) = MX31_PIN_USBH2_DIR(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_USBH2_STP(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBH2_NXT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBH2_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usbotg_data5 = UD_D5, usbotg_data6 = UD_D6, usbotg_data7 = UD_D7, usbh2_clk = UH2_CLK
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER16) = MX31_PIN_USBOTG_DATA5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBH2_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usbotg_data1 = UD_D1, usbotg_data2 = UD_D2, usbotg_data3 = UD_D3, usbotg_data4 = UD_D4
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER17) = MX31_PIN_USBOTG_DATA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usbotg_dir = UD_DIR, usbotg_stp = UD_STP, usbotg_nxt = UD_NXT, usbotg_data0 = UD_D0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER18) = MX31_PIN_USBOTG_DIR(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_STP(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_USBOTG_NXT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_USBOTG_DATA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// usb_pwr = NC, usb_oc = CF_RST, usb_byp = NC, usbotg_clk = UD_CLK
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER19) = MX31_PIN_USB_PWR(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_USB_OC(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_USB_BYP(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_USBOTG_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// MX31_PIN_TDO and MX31_PIN_SJC_MOD = can not be written to
+//// tdo = TDO_C, trstb = TRST_C, de_b = TP1, sjc_mod = GND
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER20) = MX31_PIN_TDO()
+// | MX31_PIN_TRSTB(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SJC_MOD();
+//
+//// MX31_PIN_RTCK = can not be written to.
+//// rtck = NC, tck = TCK_C, tms = TMS_C, tdi = TDI_C
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER21) = MX31_PIN_RTCK()
+// | MX31_PIN_TCK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_TMS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_TDI(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// key_col4 = NC, key_col5 = NC, key_col6 = NC, key_col7 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER22) = MX31_PIN_KEY_COL4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_COL5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_COL6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_COL7(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// key_col0 = NC, key_col1 = NC, key_col2 = NC, key_col3 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER23) = MX31_PIN_KEY_COL0(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_COL1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_COL2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_COL3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
+//
+//// key_row4 = NC, key_row5 = NC, key_row6 = NC, key_row7 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER24) = MX31_PIN_KEY_ROW4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_ROW5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_ROW6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_KEY_ROW7(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// key_row0 = NC, key_row1 = NC, key_row2 = NC, key_row3 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER25) = MX31_PIN_KEY_ROW0(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_ROW1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_ROW2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_KEY_ROW3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
+//
+//// txd2 = U1_TXD, rts2 = U1_RTS, cts2 = U1_CTS, batt_line = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER26) = MX31_PIN_TXD2(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_RTS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CTS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_BATT_LINE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// ri_dte1, dcd_dte1, and dtr_dce2 are set to CSPI1 signals by GPR(2)
+//// rxd2 = U1_RXD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER27) = MX31_PIN_RI_DTE1()
+// | MX31_PIN_DCD_DTE1()
+// | MX31_PIN_DTR_DCE2()
+// | MX31_PIN_RXD2(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC);
+//
+//// dtr_dte1 and dsr_dte1 are set to CSPI1 signals by GPR(2)
+//// ri_dce1 = SPI0_RDY, dcd_dce1 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER28) = MX31_PIN_RI_DCE1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_DCD_DCE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_DTR_DTE1()
+// | MX31_PIN_DSR_DTE1();
+//
+//// rts1 = U0_RTS, cts1 = U0_CTS, dtr_dce1 = NC, dsr_dce1 = SPI0_CLK
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER29) = MX31_PIN_RTS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CTS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_DTR_DCE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_DSR_DCE1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
+//
+//// cspi2_sclk = SPI1_CLK, cspi2_spi_rdy = SPI1_RDY, rxd1 = U0_RXD, txd1 = U0_TXD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER30) = MX31_PIN_CSPI2_SCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSPI2_SPI_RDY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_RXD1(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
+// | MX31_PIN_TXD1(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE);
+//
+//// cspi2_miso = SPI1_MISO, cspi2_ss0 = SPI1_CS0, cspi2_ss1 = SPI1_CS1, cspi2_ss2 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER31) = MX31_PIN_CSPI2_MISO(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSPI2_SS0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSPI2_SS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSPI2_SS2(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
+//
+//// cspi1_ss2 = UH1_RCV, cspi1_sclk = UH1_OE, cspi1_spi_rdy = UH1_FS, cspi2_mosi = SPI1_MOSI
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER32) = MX31_PIN_CSPI1_SS2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_CSPI1_SCLK(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_CSPI1_SPI_RDY(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_CSPI2_MOSI(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// cspi1_mosi = UH1_RXDM, cspi1_miso = UH1_RXDP, cspi1_ss0 = UH1_TXDM, cspi1_ss1 = UH1_TXDP
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER33) = MX31_PIN_CSPI1_MOSI(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)
+// | MX31_PIN_CSPI1_MISO(OUTPUTCONFIG_GPIO | INPUTCONFIG_ALT1)
+// | MX31_PIN_CSPI1_SS0(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_CSPI1_SS1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE);
+//
+//// stxd6 = AC_SDOUT, srxd6 = AC_SDIN, sck6 = AC_BCLK, sfs6 = AC_SYNC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER34) = MX31_PIN_STXD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SRXD6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SCK6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SFS6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// stxd5 = SSI_TXD, srxd5 = SSI_RXD, sck5 = SSI_CLK, sfs5 = SSI_FRM
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER35) = MX31_PIN_STXD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SRXD5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SCK5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SFS5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// stxd4 = NC, srxd4 = NC, sck4 = SSI_MCLK, sfs4 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER36) = MX31_PIN_STXD4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SRXD4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SCK4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SFS4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// stxd3 = AC_RST, srxd3 = NC, sck3 = NC, sfs3 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER37) = MX31_PIN_STXD3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_SRXD3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SCK3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_SFS3(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
+//
+//// csi_hsync = VIP_HSYNC, csi_pixclk = VIP_PCLK, i2c_clk = I2C_SCL, i2c_dat = I2C_SDA
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER38) = MX31_PIN_CSI_HSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_PIXCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_I2C_CLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_I2C_DAT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// csi_d14 = VIP_D8, csi_d15 = VIP_D9, csi_mclk = VIP_MCLK, csi_vsync = VIP_VSYNC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER39) = MX31_PIN_CSI_D14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_MCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_NONE)
+// | MX31_PIN_CSI_VSYNC(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// csi_d10 = VIP_D4, csi_d11 = VIP_D5, csi_D12 = VIP_D6, csi_D13 = VIP_D7
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER40) = MX31_PIN_CSI_D10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// csi_d6 = VIP_D0, csi_d7 = VIP_D1, csi_D8 = VIP_D2, csi_D9 = VIP_D3
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER41) = MX31_PIN_CSI_D6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// m_request = NC, m_grant = NC, csi_d4 = NC, csi_d5 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER42) = MX31_PIN_M_REQUEST(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_M_GRANT(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CSI_D4(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_CSI_D5(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// pc_rst = UH2_D5, isis16 = UH2_D6, pc_rw_b = UH2_D7, pc_poe = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER43) = MX31_PIN_PC_RST(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_IOIS16(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_PC_RW_B(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_PC_POE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// pc_vs1 = NC, pc_vs2 = UH2_D2, pc_bvd1 = UH2_D3, pc_bvd2 = UH2_D4
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER44) = MX31_PIN_PC_VS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_PC_VS2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_PC_BVD1(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1)
+// | MX31_PIN_PC_BVD2(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
+//
+//// pc_cd2_b = CF_CD, pc_wait_b = CF_WAIT, pc_ready = CF_RDY, pc_pwron = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER45) = MX31_PIN_PC_CD2_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_PC_WAIT_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_PC_READY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_PC_PWRON(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// d2, d1, and d0 are not writable, reset values are correct.
+//// d2 = LD2, d1 = LD1, d0 = LD0, pc_cd1_b = CF_CD
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER46) = MX31_PIN_D2()
+// | MX31_PIN_D1()
+// | MX31_PIN_D0()
+// | MX31_PIN_PC_CD1_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// d6, d5, d4 and d3 are not writable, reset values are correct.
+//// d6 = LD6, d5 = LD5, d4 = LD4, d3 = LD3
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER47) = MX31_PIN_D6()
+// | MX31_PIN_D5()
+// | MX31_PIN_D4()
+// | MX31_PIN_D3();
+//
+//// d10, d9, d8 and d7 are not writable, reset values are correct.
+//// d10 = LD10, d9 = LD9, d8 = LD8, d7 = LD7
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER48) = MX31_PIN_D10()
+// | MX31_PIN_D9()
+// | MX31_PIN_D8()
+// | MX31_PIN_D7();
+//
+//// d14, d13, d12 and d11 are not writable, reset values are correct.
+//// d14 = LD14, d13 = LD13, d12 = LD12, d11 = L11
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER49) = MX31_PIN_D14()
+// | MX31_PIN_D13()
+// | MX31_PIN_D12()
+// | MX31_PIN_D11();
+//
+//// d15 is not writable, reset value is correct.
+//// nfwp_b = *N_WP, nfce_b = *N_CE, nfrb = N_RDY, d15 = LD15
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER50) = MX31_PIN_NFWP_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_NFCE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_NFRB(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_D15();
+//
+//// nfwe_b = *N_WE, nfre_b = *N_RE, nfale = N_ALE, nfcle = N_CLE
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER51) = MX31_PIN_NFWE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_NFRE_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_NFALE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_NFCLE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// sdqs0, sdqs1, sdqs2, and sdqs3 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER52) = MX31_PIN_SDQS0()
+// | MX31_PIN_SDQS1()
+// | MX31_PIN_SDQS2()
+// | MX31_PIN_SDQS3();
+//
+//// sdclk_b is not writable, reset value is correct.
+//// sdcke0 = SDCKE, sdcke1 = NC, sdclk = SDCLK, sdclk_b = *SDCLK
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER53) = MX31_PIN_SDCKE0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDCKE1(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDCLK(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDCLK_B();
+//
+//// rw = *WE, ras = *SDRAS, cas = *SDCAS, sdwe = *SDWE
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER54) = MX31_PIN_RW(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_RAS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CAS(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDWE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// ecb is not writable, reset value is correct.
+//// cs5 = *CS5, ecb = ECB, lba = LBA, bclk = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER55) = MX31_PIN_CS5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_ECB()
+// | MX31_PIN_LBA(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_BCLK(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// cs1 = *CS1, cs2 = *SDCS, cs3 = NC, cs4 = *DTACK
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER56) = MX31_PIN_CS1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CS2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CS3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_CS4(OUTPUTCONFIG_ALT1 | INPUTCONFIG_ALT1);
+//
+//// eb0 = *BE0, eb1 = *BE1, oe = *OE, cs0 = *CS0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER57) = MX31_PIN_EB0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_EB1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_OE(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_CS0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// dqm0 = DQM0, dqm1 = DQM1, dqm2 = DQM2, dqm3 = DQM3
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER58) = MX31_PIN_DQM0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DQM1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DQM2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DQM3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// sd28, sd29, sd30 and sd31 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER59) = MX31_PIN_SD28()
+// | MX31_PIN_SD29()
+// | MX31_PIN_SD30()
+// | MX31_PIN_SD31();
+//
+//// sd24, sd25, sd26 and sd27 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER60) = MX31_PIN_SD24()
+// | MX31_PIN_SD25()
+// | MX31_PIN_SD26()
+// | MX31_PIN_SD27();
+//
+//// sd20, sd21, sd22 and sd23 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER61) = MX31_PIN_SD20()
+// | MX31_PIN_SD21()
+// | MX31_PIN_SD22()
+// | MX31_PIN_SD23();
+//
+//// sd16, sd17, sd18 and sd19 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER62) = MX31_PIN_SD16()
+// | MX31_PIN_SD17()
+// | MX31_PIN_SD18()
+// | MX31_PIN_SD19();
+//
+//// sd12, sd13, sd14 and sd15 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER63) = MX31_PIN_SD12()
+// | MX31_PIN_SD13()
+// | MX31_PIN_SD14()
+// | MX31_PIN_SD15();
+//
+//// sd8, sd9, sd10 and sd11 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER64) = MX31_PIN_SD8()
+// | MX31_PIN_SD9()
+// | MX31_PIN_SD10()
+// | MX31_PIN_SD11();
+//
+//// sd4, sd5, sd6 and sd7 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER65) = MX31_PIN_SD4()
+// | MX31_PIN_SD5()
+// | MX31_PIN_SD6()
+// | MX31_PIN_SD7();
+//
+//// sd0, sd1, sd2 and sd3 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER66) = MX31_PIN_SD0()
+// | MX31_PIN_SD1()
+// | MX31_PIN_SD2()
+// | MX31_PIN_SD3();
+//
+//// a24 = A24, a25 = A25, sdba1 = SDBA1, sdba0 = SDBA0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER67) = MX31_PIN_A24(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A25(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDBA1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_SDBA0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER68) = MX31_PIN_A20(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A21(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A22(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A23(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER69) = MX31_PIN_A16(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A17(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A18(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A19(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER70) = MX31_PIN_A12(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A13(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A14(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A15(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER71) = MX31_PIN_A9(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_MA10(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A11(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER72) = MX31_PIN_A5(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A6(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A7(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A8(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// address lines are one to one.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER73) = MX31_PIN_A1(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A2(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A3(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_A4(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// dvfs1 = NC, vpg0 = NC, vpg1 = NC, a0 = A0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER74) = MX31_PIN_DVFS1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_VPG0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_VPG1(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_A0(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC);
+//
+//// ckil and power_fail are not writable, reset values are correct.
+////ckil = 32K, power_fail = PWR_FAIL, vstby = VSTBY, dvfs0 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER75) = MX31_PIN_CKIL()
+// | MX31_PIN_POWER_FAIL()
+// | MX31_PIN_VSTBY(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_DVFS0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// boot_mode1, boot_mode2, boot_mode3, and boot_mode4 are not writable, reset values are correct.
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER76) = MX31_PIN_BOOT_MODE1()
+// | MX31_PIN_BOOT_MODE2()
+// | MX31_PIN_BOOT_MODE3()
+// | MX31_PIN_BOOT_MODE4();
+//
+//// por_b, clko, and boot_mode0 are not writable, reset values are correct.
+//// reset_in_b = *RST_IN (this is set in the GPR)
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER77) = MX31_PIN_RESET_IN_B(OUTPUTCONFIG_FUNC | INPUTCONFIG_FUNC)
+// | MX31_PIN_POR_B()
+// | MX31_PIN_CLKO()
+// | MX31_PIN_BOOT_MODE0();
+//
+//// ckih is not writable, reset value is correct.
+//// stx0 = GPIO1, srx0 = GPIO4, simpd0 = GPIO5
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER78) = MX31_PIN_STX0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SRX0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SIMPD0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_CKIH();
+//
+//// gpio3_1 = VF_EN, sclk0 = GPIO8, srst0 = GPIO9, sven0 = GPIO0
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER79) = MX31_PIN_GPIO3_1(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE)
+// | MX31_PIN_SCLK0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SRST0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_SVEN0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// gpio1_4 = UH1_SUSP, gpio1_5 = PWR_RDY, gpio1_6 = UH1_MODE, gpio3_0 = NC
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER80) = MX31_PIN_GPIO1_4(OUTPUTCONFIG_ALT1 | INPUTCONFIG_NONE)
+// | MX31_PIN_GPIO1_5(OUTPUTCONFIG_GPIO | INPUTCONFIG_FUNC)
+// | MX31_PIN_GPIO1_6(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_GPIO3_0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// gpio1_0 = *PIRQ, gpio1_1 = *E_INT, gpio1_2 = *EXP_INT, gpio1_3 = *I2C_INT
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER81) = MX31_PIN_GPIO1_0(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_GPIO1_1(OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)
+// | MX31_PIN_GPIO1_2(OUTPUTCONFIG_FUNC | INPUTCONFIG_GPIO)
+// | MX31_PIN_GPIO1_3(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO);
+//
+//// capture = GPIO2, compare = GPIO3, watchdog_rst = NC, pwm0 = LCD_BKL
+//IOMUX_CTL_REG(SW_MUX_CTL_REGISTER82) = MX31_PIN_CAPTURE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_COMPARE(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_WATCHDOG_RST(OUTPUTCONFIG_GPIO | INPUTCONFIG_GPIO)
+// | MX31_PIN_PWMO(OUTPUTCONFIG_GPIO | INPUTCONFIG_NONE);
diff --git a/ports/beagleboneblack/omap3530_lcd.c b/ports/beagleboneblack/omap3530_lcd.c
new file mode 100644
index 0000000..13a2c37
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_lcd.c
@@ -0,0 +1,342 @@
+//==========================================================================
+//
+// omap3530_lcd.c
+//
+// Author(s): Luis Torrico - Cogent Computer Systems, Inc.
+// Date: 12-10-2008
+// Description: Init Code for TI OMAP3530 LCD Controller
+// NOTE Only 16-bit mode has been tested!
+//
+//==========================================================================
+
+#include "config.h"
+#include "cpuio.h"
+#include "stddefs.h"
+#include "genlib.h"
+#include "omap3530.h"
+#include "omap3530_lcd.h"
+#include "cpu_gpio.h"
+#include "vga_lookup.h"
+#include "font8x16.h"
+#include "fb_draw.h"
+#include "warmstart.h"
+
+#if INCLUDE_LCD
+
+//--------------------------------------------------------------------------
+// function prototypes and externs
+//
+void fbdev_init(void);
+
+extern void udelay(int);
+extern int GPIO_clr(int);
+extern int GPIO_set(int);
+extern int GPIO_tst(int);
+extern int GPIO_out(int);
+extern int GPIO_in(int);
+
+// ADDED FOR WRITING CHARACTERS TO THE DISPLAY
+void lcd_putchar(char c);
+void lcd_writechar(uchar c);
+void lcd_clr_row(int char_row);
+void lcd_clr_scr(void);
+void lcd_switch_buffer(void);
+
+// globals to keep track of foreground, background colors and x,y position
+int lcd_color_depth; // 4, 8 or 16
+int lcd_fg_color; // 0 to 15, used as lookup into VGA color table
+int lcd_bg_color; // 0 to 15, used as lookup into VGA color table
+int lcd_col; // current column, 0 to COLS_PER_SCREEN - 1
+int lcd_row; // current row, 0 to (ROWS_PER_SCREEN * 2) - 1
+int lcd_tst_mode = 0;
+ulong lcd_fb_offset; // current offset into frame buffer for lcd_putchar
+
+//#define LCD_DBG
+//--------------------------------------------------------------------------
+// fbdev_init
+//
+// This function sets up the OMAP3530 LCD Controller, to be used
+// as uMon's frame buffer device.
+//
+void
+fbdev_init(void)
+{
+ //ushort temp16;
+
+ if (StateOfMonitor != INITIALIZE)
+ return;
+
+ lcd_color_depth = 16;
+ lcd_fg_color = vga_lookup[LCD_FG_DEF];
+ lcd_bg_color = vga_lookup[LCD_BG_DEF];
+
+ // Select DSS1_ALWON_FCLK (96MHz) as source for DSI and DISPC
+ DSS_REG(DSS_CONTROL) = 0x30;
+
+ // apply a soft reset to the display subsystem
+ DISPC_REG(DISPC_SYSCONFIG) = 0x02;
+
+ udelay(1000);
+
+ // Set interface and functional clock to on during wakeup
+ // and no standby or idle
+ DISPC_REG(DISPC_SYSCONFIG) |= 0x2015;
+
+ // Set up the DMA base address
+ DISPC_REG(DISPC_GFX_BA) = 0x80200000;
+
+ // Set up RGB 16 and disable the DMA for now
+ DISPC_REG(DISPC_GFX_ATTR) = 0x0000000C;
+
+ // Set preload based on equation in section 15.5.3.2 in RM
+ //DISPC_REG(DISPC_GFX_PRELOAD) = 0x60;
+
+ // Set number of bytes to increment at end of row to 1 (default value)
+ DISPC_REG(DISPC_GFX_ROW_INC) = 0x0001;
+
+ // Set number of bytes to increment between two pixels to 1 (default value)
+ DISPC_REG(DISPC_GFX_PIX_INC) = 0x0001;
+
+ // Set FIFO thresholds to defaults (hi = 1023, lo = 960)
+ //DISPC_REG(DISPC_GFX_FIFO_TH) = 0x03FF03C0;
+ DISPC_REG(DISPC_GFX_FIFO_TH) = 0x03FC03BC;
+
+ // Set start position to 0 (frame buffer and active display area are the same)
+ DISPC_REG(DISPC_GFX_POS) = 0x00000000;
+
+ // Set frame buffer size, Y = PIXELS_PER_COL, X = PIXELS_PER_ROW
+ DISPC_REG(DISPC_GFX_SIZE) = (((PIXELS_PER_COL -1) << 16) | (PIXELS_PER_ROW - 1));
+
+ // Set the control register keep bit 5 (GOLCD) and bit 28 (LCDENABLESIGNAL) low
+ // until shadow registers have all been written
+ DISPC_REG(DISPC_CONTROL) = 0x38019209;
+
+ // Disable all gating, pixel clock always toggles, frame data only
+ // loaded every frame (palette/gamma table off)
+ DISPC_REG(DISPC_CONFIG) = 0x00000004;
+ //DISPC_REG(DISPC_CONFIG) = 0x00000000;
+
+ // Disable all capabilities not used for LCD
+ DISPC_REG(DISPC_CAPABLE) = 0x00000000;
+
+ // Set horizontal timing
+ DISPC_REG(DISPC_TIMING_H) = ((LCD_H_BACK << 20) | (LCD_H_FRONT << 8) | LCD_H_WIDTH);
+
+ // Set vertical timing
+ DISPC_REG(DISPC_TIMING_V) = ((LCD_V_BACK << 20) | (LCD_V_FRONT << 8) | LCD_V_WIDTH);
+
+ // Set syncs low true and DE to hi true
+ DISPC_REG(DISPC_POL_FREQ) = 0x00003000;
+
+ // Set logic divisor to 1 and pixel divisor to 2
+ DISPC_REG(DISPC_DIVISOR) = 0x00020001;
+
+ // Set LCD size, lines per panel is , pixels per line is
+ DISPC_REG(DISPC_SIZE_LCD) = (((PIXELS_PER_COL -1) << 16) | (PIXELS_PER_ROW - 1));
+
+ // Enable the DMA
+ DISPC_REG(DISPC_GFX_ATTR) |= 0x00000001;
+
+ // Set bit 5 (GOLCD) to enable LCD
+ DISPC_REG(DISPC_CONTROL) |= 0x00000020;
+
+ printf("OMAP3530 LCD Initialization Complete.\n");
+
+ return;
+}
+
+/* fbdev_setstart():
+ * Used by uMon's FBI interface to establish the starting address of
+ * the frame buffer memory.
+ */
+void
+fbdev_setstart(long offset)
+{
+ // Select DSS1_ALWON_FCLK (96MHz) as source for DSI and DISPC
+ DSS_REG(DSS_CONTROL) = 0x30;
+
+ // Set up the DMA base address
+ DISPC_REG(DISPC_GFX_BA) = offset;
+
+ // Enable the DMA
+ DISPC_REG(DISPC_GFX_ATTR) |= 0x00000001;
+
+ // Set bit 5 (GOLCD) to enable LCD
+ DISPC_REG(DISPC_CONTROL) |= 0x00000020;
+
+ return;
+}
+
+char *lcd_tstHelp[] = {
+ "OMAP3530 LCD controller test",
+ "-[n,x,d[4,8,16]]",
+ "The user may set color depth to run the test at.",
+ "The frame buffer R/W test will test all of the frame ",
+ "buffer regardless of depth.",
+ "Options...",
+ " -n run test without keycheck - CAUTION: RESET SYSTEM TO STOP!",
+ " -d4 run test, force a depth of 4-bits/pixel",
+ " -d8 run test, force a depth of 8-bits/pixel",
+ " -d16 run test, force a depth of 16-bits/pixel",
+ " -x init only, do not run frame buffer tests",
+ "",
+ " No options, default to current mode and depth.",
+ 0
+};
+
+int lcd_tst(int argc,char *argv[])
+{
+ volatile ushort wr16, rd16;
+ int i, x, opt;
+ int no_wait = 0;
+ int init_only = 0;
+ char c;
+
+ lcd_tst_mode = 1;
+
+ while ((opt=getopt(argc,argv,"clnsxd:4,8,16")) != -1) {
+ switch(opt) {
+ case 'd': // set the color depth
+ switch(*optarg) {
+ case '4':
+ lcd_color_depth = 4;
+ printf("Forcing 4bpp Mode!\n");
+ break;
+ case '8':
+ lcd_color_depth = 8;
+ printf("Forcing 8bpp Mode!\n");
+ break;
+ default: // test with 16bpp
+ lcd_color_depth = 16;
+ printf("Forcing 16bpp Mode!\n");
+ break;
+ }
+ break;
+ case 'n': // no waiting for keypress - fastest operation
+ no_wait = 1;
+ printf("No Keypress Mode, Must Reset System to Stop!\n");
+ break;
+ case 'x': // init only
+ no_wait = 1;
+ printf("Initializing LCD, Skipping testsp!\n");
+ init_only = 1;
+ break;
+ default: // test with current mode
+ break;
+ }
+ }
+
+ // get the new parameters into the LCD controller
+ fbdev_init();
+
+ if (init_only) return 0;
+
+ printf("Frame Buffer R/W...");
+ // do an address=data read/write test on the frame buffer
+ // PIXELS_PER_COL * PIXELS_PER_ROW is the highest pixel.
+ // Multiply by bits_per_pixel (sed_color_depth), then
+ // divide by 8 to get the actual byte count.
+ for (i = 0; i < LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth); i += 2){
+ LCD_BUF(i) = i & 0xffff;
+ rd16 = LCD_BUF(i);
+ if(rd16 != (i & 0xffff)){
+ printf("Fail at 0x%08x, WR 0x%08x, RD 0x%04lx!\n",LCD_BUF_ADD + i, i, (ulong)rd16);
+ return -1;
+ }
+ }
+
+ printf("OK!, Press key to continue.\n");
+
+ c = getchar();
+
+ printf("Frame Buffer Start: 0x%08x, End 0x%08x\n",LCD_BUF_ADD,
+ LCD_BUF_ADD + LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth));
+ if (no_wait)
+ {
+ printf("Begin Full Screen Color Test.\n");
+ while(1){
+ // fill the frame buffer with incrementing color values
+ for (x = 0; x < 16; x++){
+ switch (lcd_color_depth){
+ case 4: wr16 = x | x << 4 | x << 8 | x << 12; break;
+ case 8: wr16 = x | x << 8; break;
+ default: wr16 = vga_lookup[x]; break; // 16-bits bypasses the lookup table
+ }
+ for (i = 0; i < LCD_FB_SIZE(lcd_color_depth); i += 2){
+ LCD_BUF(i) = wr16;
+ }
+ } // for x
+ } // while
+ } // no_wait
+ else
+ {
+ printf("Begin Full Screen Color Test, Press any key to go to next color, \'x\' to end.\n");
+ while(1){
+ // fill the frame buffer with incrementing color values
+ for (x = 0; x < 16; x++){
+ switch (lcd_color_depth){
+ case 4: wr16 = x | x << 4 | x << 8 | x << 12; break;
+ case 8: wr16 = x | x << 8; break;
+ default: wr16 = vga_lookup[x]; break; // 16-bits bypasses the lookup table
+ }
+ for (i = 0; i < LCD_FB_SIZE(lcd_color_depth) + LCD_ROW_SIZE(lcd_color_depth); i += 2){
+ LCD_BUF(i) = wr16;
+ }
+ c = getchar();
+ if (c == 'x') goto lcd_tst_next;
+ } // for x
+ } // while
+ } // else no keycheck test
+
+ lcd_tst_next:
+
+ // write a one pixel border around the screen
+ lcd_fg_color = 15; // VGA Bright White
+ fb_draw_line2(LEFT, TOP, RIGHT, TOP, lcd_fg_color);
+ fb_draw_line2(LEFT, TOP, LEFT, BOTTOM, lcd_fg_color);
+ fb_draw_line2(LEFT, BOTTOM, RIGHT, BOTTOM, lcd_fg_color); // bottom left to bottom right
+ fb_draw_line2(RIGHT, TOP, RIGHT, BOTTOM, lcd_fg_color); // bottom right to top right
+ // draw an x
+ fb_draw_line2(LEFT, TOP, RIGHT, BOTTOM, lcd_fg_color);
+ fb_draw_line2(LEFT, BOTTOM, RIGHT, TOP, lcd_fg_color);
+ // draw 3 circles at the center of the screen, one inside the other
+ lcd_fg_color = 12; // VGA Bright Red
+ fb_draw_circle2(CENTER_X, CENTER_Y, 100, lcd_fg_color);
+ lcd_fg_color = 10; // VGA Bright Green
+ fb_draw_circle2(CENTER_X, CENTER_Y, 66, lcd_fg_color);
+ lcd_fg_color = 9; // VGA Bright Blue
+ fb_draw_circle2(CENTER_X, CENTER_Y, 33, lcd_fg_color);
+
+ return 0;
+}
+
+// fb_set_pixel sets a pixel to the specified color.
+// This is target specific and is called from the generic
+// fb_draw.c functions
+void fb_set_pixel(ulong X, ulong Y, uchar color)
+{
+ // Make sure the specified pixel is valid.
+#if 0
+ if((X < 0) || (X >= PIXELS_PER_ROW) || (Y < 0) || (Y >= PIXELS_PER_COL))
+ {
+ printf("fb_set_pixel() bad X (%ld) or Y (%ld)!\n", X, Y);
+ return;
+ }
+#else
+ if (X < 0)
+ X = 0;
+ else {
+ if (X >= PIXELS_PER_ROW)
+ X = PIXELS_PER_ROW - 1;
+ }
+ if (Y < 0)
+ Y = 0;
+ else {
+ if (Y >= PIXELS_PER_COL)
+ Y = PIXELS_PER_COL - 1;
+ }
+#endif
+
+ LCD_BUF(LCD_GET_PIXEL_ADD(X, Y)) = vga_lookup[color];
+}
+#endif
diff --git a/ports/beagleboneblack/omap3530_lcd.h b/ports/beagleboneblack/omap3530_lcd.h
new file mode 100644
index 0000000..0457548
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_lcd.h
@@ -0,0 +1,75 @@
+//==========================================================================
+//
+// omap3530_lcd.h
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 12/10/2008
+// Description: This file contains register offsets and bit defines
+// for the OMAP3530 Cortex-A8 LCD Controller
+//
+
+#include "bits.h"
+
+/* The DSS is designed to support video and graphics processing functions and to */
+/* interface with video/still image sensors and displays. */
+
+/*-------------------------------------------------------------------------------------*/
+/* Display Interface Subsystem */
+/*-------------------------------------------------------------------------------------*/
+/* Module Name Base Address Size */
+/*
+ DSI Protocol Engine 0x4804FC00 512 bytes
+ DSI Complex I/O 0x4804FE00 64 bytes
+ DSI PLL Controller 0x4804FF00 32 bytes
+ DISS 0x48050000 512 byte
+ DISPC 0x48050400 1K byte
+ RFBI 0x48050800 256 bytes
+ VENC 0x48050C00 256 bytes
+*/
+/*-------------------------------------------------------------------------------------*/
+#define DSS_BASE_ADD 0x48050000 // Display Subsystem Base Address
+#define DISPC_BASE_ADD 0x48050400 // Display Controller Base Address
+#define DSS_REG(_x_) *(vulong *)(DSS_BASE_ADD + _x_)
+#define DISPC_REG(_x_) *(vulong *)(DISPC_BASE_ADD + _x_)
+
+// Display Subsystem Registers
+#define DSS_SYSCONFIG 0x10 //
+#define DSS_SYSSTATUS 0x14 //
+#define DSS_IRQSTATUS 0x18 //
+#define DSS_CONTROL 0x40 //
+#define DSS_SDI_CONTROL 0x44 //
+#define DSS_PLL_CONTROL 0x48 //
+#define DSS_SDI_STATUS 0x5C //
+
+// Display Controller Registers
+#define DISPC_SYSCONFIG 0x10 //
+#define DISPC_SYSSTATUS 0x14 //
+#define DISPC_IRQSTATUS 0x18 //
+#define DISPC_IRQENABLE 0x1C //
+#define DISPC_CONTROL 0x40 //
+#define DISPC_CONFIG 0x44 //
+#define DISPC_CAPABLE 0x48 //
+#define DISPC_DEFAULT_COLOR 0x4C //
+#define DISPC_TRANS_COLOR 0x54 //
+#define DISPC_LINE_STATUS 0x5C //
+#define DISPC_LINE_NUMBER 0x60 //
+#define DISPC_TIMING_H 0x64 //
+#define DISPC_TIMING_V 0x68 //
+#define DISPC_POL_FREQ 0x6C //
+#define DISPC_DIVISOR 0x70 //
+#define DISPC_GLOBAL_ALPHA 0x74 //
+#define DISPC_SIZE_DIG 0x78 //
+#define DISPC_SIZE_LCD 0x7C //
+#define DISPC_GFX_BA 0x80 //
+#define DISPC_GFX_POS 0x88 //
+#define DISPC_GFX_SIZE 0x8C //
+#define DISPC_GFX_ATTR 0xA0 //
+#define DISPC_GFX_FIFO_TH 0xA4 //
+#define DISPC_GFX_FIFO_SS 0xA8 //
+#define DISPC_GFX_ROW_INC 0xAC //
+#define DISPC_GFX_PIX_INC 0xB0 //
+#define DISPC_GFX_WIN_SKIP 0xB4 //
+#define DISPC_GFX_TABLE_BA 0xB8 //
+#define DISPC_GFX_PRELOAD 0x62C //
+
diff --git a/ports/beagleboneblack/omap3530_mem.h b/ports/beagleboneblack/omap3530_mem.h
new file mode 100644
index 0000000..820873c
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_mem.h
@@ -0,0 +1,184 @@
+//==========================================================================
+//
+// omap3530_mem.h
+//
+// Author(s): Luis Torrico, Cogent Computer Systems, Inc.
+// Contributors:
+// Date: 12/09/2008
+// Description: This file contains register base addresses and offsets
+// and access macros for the OMAP3530 Cortex-A8 memory controller
+//
+
+#include "bits.h"
+
+// The GPMC supports up to eight chip-select regions of programmable size, and programmable base
+// addresses in a total address space of 1 Gbyte.
+// Chip Select mapping for CSB740
+// CS0 = NOR = 0x08000000
+// CS1 = N/A
+// CS2 = N/A
+// CS3 = NAND = 0x18000000
+// CS4 = Ethernet = 0x2C000000
+// CS5 = Expansion = 0x28000000
+// CS6 = N/A
+// CS7 = N/A
+
+//#define OMAP35XX_GPMC_BASE 0x6E000000
+#define GPMC_REG(_x_) *(vulong *)(OMAP35XX_GPMC_BASE + _x_)
+#define MYGPMC_REG(_x_) (vulong *)(OMAP35XX_GPMC_BASE + _x_)
+
+// GPMC - General Purpose Memory Controller
+#define GPMC_SYS_CONFIG 0x10 // Chip Select 0 Upper Control Register
+#define GPMC_SYS_STATUS 0x14 // Chip Select 0 Lower Control Register
+#define GPMC_IRQ_STATUS 0x18 // Chip Select 0 Additional Control Register
+#define GPMC_IRQ_EN 0x1C // Chip Select 1 Upper Control Register
+#define GPMC_TIMEOUT 0x40 // Chip Select 1 Lower Control Register
+#define GPMC_ERR_ADD 0x44 // Chip Select 1 Additional Control Register
+#define GPMC_ERR_TYPE 0x48 // Chip Select 2 Upper Control Register
+#define GPMC_CONFIG 0x50 // Chip Select 2 Lower Control Register
+#define GPMC_STATUS 0x54 // Chip Select 2 Additional Control Register
+
+#define GPMC_CS0_CONFIG1 0x60 // Chip Select 3 Upper Control Register
+#define GPMC_CS0_CONFIG2 0x64 // Chip Select 3 Lower Control Register
+#define GPMC_CS0_CONFIG3 0x68 // Chip Select 3 Additional Control Register
+#define GPMC_CS0_CONFIG4 0x6C // Chip Select 4 Upper Control Register
+#define GPMC_CS0_CONFIG5 0x70 // Chip Select 4 Lower Control Register
+#define GPMC_CS0_CONFIG6 0x74 // Chip Select 4 Additional Control Register
+#define GPMC_CS0_CONFIG7 0x78 // Chip Select 5 Upper Control Register
+
+#define GPMC_CS1_CONFIG1 0x90 // Chip Select 5 Lower Control Register
+#define GPMC_CS1_CONFIG2 0x94 // Chip Select 5 Additional Control Register
+#define GPMC_CS1_CONFIG3 0x98 // Configuration Register
+#define GPMC_CS1_CONFIG4 0x9C // Chip Select 5 Lower Control Register
+#define GPMC_CS1_CONFIG5 0xA0 // Chip Select 5 Additional Control Register
+#define GPMC_CS1_CONFIG6 0xA4 // Configuration Register
+#define GPMC_CS1_CONFIG7 0xA8 // Configuration Register
+
+#define GPMC_CS2_CONFIG1 0xC0 // Chip Select 5 Lower Control Register
+#define GPMC_CS2_CONFIG2 0xC4 // Chip Select 5 Additional Control Register
+#define GPMC_CS2_CONFIG3 0xC8 // Configuration Register
+#define GPMC_CS2_CONFIG4 0xCC // Chip Select 5 Lower Control Register
+#define GPMC_CS2_CONFIG5 0xD0 // Chip Select 5 Additional Control Register
+#define GPMC_CS2_CONFIG6 0xD4 // Configuration Register
+#define GPMC_CS2_CONFIG7 0xD8 // Configuration Register
+
+#define GPMC_CS3_CONFIG1 0xF0 // Chip Select 5 Lower Control Register
+#define GPMC_CS3_CONFIG2 0xF4 // Chip Select 5 Additional Control Register
+#define GPMC_CS3_CONFIG3 0xF8 // Configuration Register
+#define GPMC_CS3_CONFIG4 0xFC // Chip Select 5 Lower Control Register
+#define GPMC_CS3_CONFIG5 0x100 // Chip Select 5 Additional Control Register
+#define GPMC_CS3_CONFIG6 0x104 // Configuration Register
+#define GPMC_CS3_CONFIG7 0x108 // Configuration Register
+
+#define GPMC_CS4_CONFIG1 0x120 // Chip Select 5 Lower Control Register
+#define GPMC_CS4_CONFIG2 0x124 // Chip Select 5 Additional Control Register
+#define GPMC_CS4_CONFIG3 0x128 // Configuration Register
+#define GPMC_CS4_CONFIG4 0x12C // Chip Select 5 Lower Control Register
+#define GPMC_CS4_CONFIG5 0x130 // Chip Select 5 Additional Control Register
+#define GPMC_CS4_CONFIG6 0x134 // Configuration Register
+#define GPMC_CS4_CONFIG7 0x138 // Configuration Register
+
+#define GPMC_CS5_CONFIG1 0x150 // Chip Select 5 Lower Control Register
+#define GPMC_CS5_CONFIG2 0x154 // Chip Select 5 Additional Control Register
+#define GPMC_CS5_CONFIG3 0x158 // Configuration Register
+#define GPMC_CS5_CONFIG4 0x15C // Chip Select 5 Lower Control Register
+#define GPMC_CS5_CONFIG5 0x160 // Chip Select 5 Additional Control Register
+#define GPMC_CS5_CONFIG6 0x164 // Configuration Register
+#define GPMC_CS5_CONFIG7 0x168 // Configuration Register
+
+#define GPMC_CS6_CONFIG1 0x180 // Chip Select 5 Lower Control Register
+#define GPMC_CS6_CONFIG2 0x184 // Chip Select 5 Additional Control Register
+#define GPMC_CS6_CONFIG3 0x188 // Configuration Register
+#define GPMC_CS6_CONFIG4 0x18C // Chip Select 5 Lower Control Register
+#define GPMC_CS6_CONFIG5 0x190 // Chip Select 5 Additional Control Register
+#define GPMC_CS6_CONFIG6 0x194 // Configuration Register
+#define GPMC_CS6_CONFIG7 0x198 // Configuration Register
+
+#define GPMC_CS7_CONFIG1 0x1B0 // Chip Select 5 Lower Control Register
+#define GPMC_CS7_CONFIG2 0x1B4 // Chip Select 5 Additional Control Register
+#define GPMC_CS7_CONFIG3 0x1B8 // Configuration Register
+#define GPMC_CS7_CONFIG4 0x1BC // Chip Select 5 Lower Control Register
+#define GPMC_CS7_CONFIG5 0x1C0 // Chip Select 5 Additional Control Register
+#define GPMC_CS7_CONFIG6 0x1C4 // Configuration Register
+#define GPMC_CS7_CONFIG7 0x1C8 // Configuration Register
+
+#define GPMC_PREFETCH_CONFIG1 0x1E0
+#define GPMC_PREFETCH_CONFIG2 0x1E4
+#define GPMC_PREFETCH_CONTROL 0x1EC
+#define GPMC_PREFETCH_STATUS 0x1F0
+
+// Bit Defines for OMAP3530 GPMC
+// WEIM_CS0U to WEIM_CS5U - Chip Select Upper Control Register
+#define WEIM_CSU_SP BIT31 // Supervisor Protect, 0 = User mode accesses allowed, 1 = User mode accesses prohibited
+#define WEIM_CSU_WP BIT30 // Write Protect, 0 = Writes allowed, 1 = Writes prohibited
+#define WEIM_CSU_BCD(_x_) ((_x_ & 0x03) << 28) // Burst Clock Divisor, when EIM_CFG_BCM = 0
+#define WEIM_CSU_BCS(_x_) ((_x_ & 0x03) << 24) // Burst Clock Start, # of 1/2 cycles from LBA to BCLK high
+#define WEIM_CSU_PSZ_4 (0 << 22) // page size = 4 words
+#define WEIM_CSU_PSZ_8 (1 << 22) // page size = 8 words
+#define WEIM_CSU_PSZ_16 (2 << 22) // page size = 16 words
+#define WEIM_CSU_PSZ_32 (3 << 22) // page size = 32 words
+#define WEIM_CSU_PME BIT21 // 1 = Enables page mode emulation
+#define WEIM_CSU_SYNC BIT20 // 1 = Enables synchronous burst mode
+#define WEIM_CSU_DOL(_x_) ((_x_ & 0x0f) << 16) // # of clocks -1 before latching read data when SYNC = 1
+#define WEIM_CSU_CNC_0 (0 << 14) // Hold CS negated after end of cycle for 0 clocks
+#define WEIM_CSU_CNC_1 (1 << 14) // Hold CS negated after end of cycle for 1 clock
+#define WEIM_CSU_CNC_2 (2 << 14) // Hold CS negated after end of cycle for 2 clocks
+#define WEIM_CSU_CNC_3 (3 << 14) // Hold CS negated after end of cycle for 3 clocks
+#define WEIM_CSU_WSC(_x_) ((_x_ & 0x3f) << 8) // Wait States, 0 = 2, 1 = 2, 2-62 = +1, 63 = dtack
+#define WEIM_CSU_WSC_DTACK (0x3f << 8) // Wait States, 0 = 2, 1 = 2, 2-62 = +1, 63 = dtack
+#define WEIM_CSU_EW BIT7 // Determines how WEIM supports the ECB input
+#define WEIM_CSU_WWS(_x_) ((_x_ & 0x07) << 4) // Additional wait states for write cycles
+#define WEIM_CSU_EDC(_x_) ((_x_ & 0x0f) << 0) // Dead Cycles after reads for bus turn around
+
+// Bit Defines for MCIMX31
+// WEIM_CS0L to WEIM_CS5L - Chip Select Lower Control Register
+#define WEIM_CSL_OEA(_x_) ((_x_ & 0x0f) << 28) // # of 1/2 cycles after CS asserts before OE asserts
+#define WEIM_CSL_OEN(_x_) ((_x_ & 0x0f) << 24) // # of 1/2 cycles OE negates before CS negates
+#define WEIM_CSL_WEA(_x_) ((_x_ & 0x0f) << 20) // # of 1/2 cycles EB0-3 assert before WE asserts
+#define WEIM_CSL_WEN(_x_) ((_x_ & 0x0f) << 16) // # of 1/2 cycles EB0-3 negate before WE negates
+#define WEIM_CSL_CSA(_x_) ((_x_ & 0x0f) << 12) // # of clocks address is asserted before CS and held after CS
+#define WEIM_CSL_EBC BIT11 // 0 = assert EB0-3 for Reads & Writes, 1 = Writes only
+#define WEIM_CSL_DSZ_BYTE_3 (0 << 8) // device is 8-bits wide, located on byte 3 (D31-24)
+#define WEIM_CSL_DSZ_BYTE_2 (1 << 8) // device is 8-bits wide, located on byte 2 (D23-16)
+#define WEIM_CSL_DSZ_BYTE_1 (2 << 8) // device is 8-bits wide, located on byte 1 (D15-8)
+#define WEIM_CSL_DSZ_BYTE_0 (3 << 8) // device is 8-bits wide, located on byte 0 (D7-0)
+#define WEIM_CSL_DSZ_HALF_1 (4 << 8) // device is 16-bits wide, located on half word 1 (D31-16)
+#define WEIM_CSL_DSZ_HALF_0 (5 << 8) // device is 16-bits wide, located on half word 1 (D15-0)
+#define WEIM_CSL_DSZ_WORD (6 << 8) // device is 32-bits wide, located on half word 1 (D15-0)
+#define WEIM_CSL_CSN(_x_) ((_x_ & 0x0f) << 4) // Chip Select Negate
+#define WEIM_CSL_PSR BIT3 // PSRAM Enable, 0 = disabled, 1 = enabled
+#define WEIM_CSL_CRE BIT2 // Control Register Enable
+#define WEIM_CSL_WRAP BIT1 // 0 = Memory in linear mode, 1 = Memory in wrap mode
+#define WEIM_CSL_CSEN BIT0 // 1 = Enable Chip Select
+
+// Bit Defines for MCIMX31
+// WEIM_CS0A to WEIM_CS5A - Chip Select Additional Control Register
+#define WEIM_CSA_EBRA(_x_) ((_x_ & 0x0f) << 28) // # of half AHB clock cycles before EB asserted.
+#define WEIM_CSA_EBRN(_x_) ((_x_ & 0x0f) << 24) // # of half AHB clock cycles between EB negation and end of access.
+#define WEIM_CSA_RWA(_x_) ((_x_ & 0x0f) << 20) // # of half AHB clock cycles RW delay
+#define WEIM_CSA_RWN(_x_) ((_x_ & 0x0f) << 16) // # of half AHB clock cycles between EB negation and end of access
+#define WEIM_CSA_MUM BIT15 // 1 = Muxed Mode
+#define WEIM_CSA_LAH_0 (0 << 13) // 0 AHB half clock cycles between LBA negation and address invalid
+#define WEIM_CSA_LAH_1 (1 << 13) // 1 AHB half clock cycles between LBA negation and address invalid
+#define WEIM_CSA_LAH_2 (2 << 13) // 2 AHB half clock cycles between LBA negation and address invalid
+#define WEIM_CSA_LAH_3 (3 << 13) // 3 AHB half clock cycles between LBA negation and address invalid
+#define WEIM_CSA_LBN(_x_) ((_x_ & 0x07) << 10) // This bit field determines when LBA is negated
+#define WEIM_CSA_LBA_0 (0 << 8) // 0 AHB half clock cycles between beginning of access and LBA assertion.
+#define WEIM_CSA_LBA_1 (1 << 8) // 1 AHB half clock cycles between beginning of access and LBA assertion.
+#define WEIM_CSA_LBA_2 (2 << 8) // 2 AHB half clock cycles between beginning of access and LBA assertion.
+#define WEIM_CSA_LBA_3 (3 << 8) // 3 AHB half clock cycles between beginning of access and LBA assertion.
+#define WEIM_CSA_DWW(_x_) ((_x_ & 0x03) << 6) // Decrease Write Wait State
+#define WEIM_CSA_DCT_0 (0 << 4) // 0 AHB clock cycles between CS assertion and first DTACK check.
+#define WEIM_CSA_DCT_1 (1 << 4) // 1 AHB clock cycles between CS assertion and first DTACK check.
+#define WEIM_CSA_DCT_2 (2 << 4) // 2 AHB clock cycles between CS assertion and first DTACK check.
+#define WEIM_CSA_DCT_3 (3 << 4) // 3 AHB clock cycles between CS assertion and first DTACK check.
+#define WEIM_CSA_WWU BIT3 // 1 = Allow wrap on write
+#define WEIM_CSA_AGE BIT2 // 1 = Enable glue logic
+#define WEIM_CSA_CNC2 BIT1 // Chip Select Negation Clock Cycles
+#define WEIM_CSA_FCE BIT0 // 1 = Data captured using BCLK_FB
+
+// WEIM_CFG - Configuration Register
+#define WEIM_CFG_BCM BIT2 // 1 = Burst Clock always on, 0 = when CS with SYNC = 1 is accessed
+#define WEIM_CFG_MAS BIT0 // 1 = Merged address space
+
+
diff --git a/ports/beagleboneblack/omap3530_sdmmc.c b/ports/beagleboneblack/omap3530_sdmmc.c
new file mode 100644
index 0000000..b542d4e
--- /dev/null
+++ b/ports/beagleboneblack/omap3530_sdmmc.c
@@ -0,0 +1,505 @@
+/* NOTE:
+ * THIS CODE IS NOT READY FOR USE YET!!!
+ */
+#include "config.h"
+#include "cpuio.h"
+#include "genlib.h"
+#include "stddefs.h"
+#include "timer.h"
+#include "omap3530.h"
+#include "sd.h"
+
+
+#define MMCTMOUT 2000
+
+/* This code is included here just for simulating the SD
+ * interface (temporarily if a real one isn't ready. In a real system,
+ * the INCLUDE_SD_DUMMY_FUNCS definition would be off.
+ */
+int
+xsdCmd(unsigned long cmd, unsigned short argh, unsigned short argl)
+{
+ vulong stat, rsp;
+ struct elapsed_tmr tmr;
+
+ printf("sdCmd(0x%08lx) (cmd=%d)\n",cmd,(cmd & 0x3f000000) >> 24);
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for command line not-in-use
+ while(MMC1_REG(MMCHS_PSTATE) & CMDI) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: CMDI timeout\n");
+ return(-1);
+ }
+ }
+
+ MMC1_REG(MMCHS_ARG) = ((argh << 16) | argl);
+ MMC1_REG(MMCHS_IE) = 0xfffffeff;
+ MMC1_REG(MMCHS_CMD) = cmd;
+
+again:
+ stat = MMC1_REG(MMCHS_STAT);
+ if (stat & CTO) {
+ if (stat & CCRC)
+ printf("cmdline in use\n");
+ else
+ printf("CTO1 CCRC0\n");
+ MMC1_REG(MMCHS_SYSCTL) |= SRC;
+ startElapsedTimer(&tmr,MMCTMOUT);
+ while(MMC1_REG(MMCHS_SYSCTL) & SRC) {
+ if(msecElapsed(&tmr))
+ printf("sdInit: SRC timeout\n");
+ }
+ return(-1);
+ }
+ if ((stat & CC) == 0)
+ goto again;
+
+ cmd = MMC1_REG(MMCHS_CMD);
+ if ((cmd & RSPTYPE) == RSPTYPE_NONE) {
+ printf("Success!\n");
+ return(0);
+ }
+
+ if ((cmd & RSPTYPE) == RSPTYPE_136) {
+ rsp = MMC1_REG(MMCHS_RSP10);
+ printf("RSP0: %04x, RSP1: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ rsp = MMC1_REG(MMCHS_RSP32);
+ printf("RSP2: %04x, RSP3: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ rsp = MMC1_REG(MMCHS_RSP54);
+ printf("RSP4: %04x, RSP5: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ rsp = MMC1_REG(MMCHS_RSP76);
+ printf("RSP6: %04x, RSP7: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ }
+ if ((cmd & RSPTYPE) == RSPTYPE_48) {
+ rsp = MMC1_REG(MMCHS_RSP10);
+ printf("RSP0: %04x, RSP1: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ rsp = MMC1_REG(MMCHS_RSP32);
+ printf("RSP2: %04x, RSP3: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ }
+ if ((cmd & RSPTYPE) == RSPTYPE_48BSY) {
+ rsp = MMC1_REG(MMCHS_RSP10);
+ printf("RSP0: %04x, RSP1: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ rsp = MMC1_REG(MMCHS_RSP32);
+ printf("RSP2: %04x, RSP3: %04x\n",
+ rsp & 0xffff,(rsp & 0xffff0000) >> 16);
+ }
+
+ return(0);
+}
+
+int
+sdCmd(unsigned long cmd, unsigned short argh, unsigned short argl)
+{
+ vulong stat, arg;
+ struct elapsed_tmr tmr;
+
+ printf("sdCmd(0x%08lx) (cmd=%d)\n",cmd,(cmd & 0x3f000000) >> 24);
+
+ MMC1_REG(MMCHS_STAT) = 0xffffffff;
+ MMC1_REG(MMCHS_BLK) = NBLK(1) | BLEN(512);
+ MMC1_REG(MMCHS_SYSCTL) &= ~DTOMSK;
+ MMC1_REG(MMCHS_SYSCTL) |= DTO(14);
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for command line not-in-use
+ while(MMC1_REG(MMCHS_PSTATE) & CMDI) {
+ if(msecElapsed(&tmr)) {
+ printf("sdCmd: CMDI timeout\n");
+ return(-1);
+ }
+ monDelay(1);
+ }
+
+ arg = argh;
+ arg <<= 16;
+ arg |= argl;
+ MMC1_REG(MMCHS_ARG) = arg;
+ MMC1_REG(MMCHS_IE) = 0xfffffeff;
+ MMC1_REG(MMCHS_CMD) = cmd;
+
+ startElapsedTimer(&tmr,MMCTMOUT);
+ do {
+ stat = MMC1_REG(MMCHS_STAT);
+ if (stat & CTO) {
+ if (stat & CCRC)
+ printf("CCRC1\n");
+ else
+ printf("CTO1 CCRC0\n");
+ MMC1_REG(MMCHS_SYSCTL) |= SRC;
+ startElapsedTimer(&tmr,MMCTMOUT);
+ while(MMC1_REG(MMCHS_SYSCTL) & SRC) {
+ if(msecElapsed(&tmr))
+ printf("sdCmd: SRC timeout\n");
+ }
+ return(-1);
+ }
+ if(msecElapsed(&tmr)) {
+ printf("sdCmd: CC timeout\n");
+ return(-1);
+ }
+ monDelay(1);
+ } while ((stat & CC) == 0);
+
+ stat = MMC1_REG(MMCHS_STAT);
+ if (stat & CCRC)
+ printf("Cmd crc\n");
+ if (stat & DCRC)
+ printf("Data crc\n");
+ if (stat & CERR) {
+ printf("Card error 0x%lx\n",stat);
+ return(-1);
+ }
+ if (stat & CTO) {
+ printf("CTO set!\n");
+ return(-1);
+ }
+ if (stat & CC) {
+ printf("Success!\n");
+ return(0);
+ }
+ else {
+ printf("Didn't complete!\n");
+ return(-1);
+ }
+}
+
+int
+sdClkSet(int clkval)
+{
+ vulong reg;
+ struct elapsed_tmr tmr;
+
+ MMC1_REG(MMCHS_SYSCTL) &= ~CEN;
+ reg = MMC1_REG(MMCHS_SYSCTL);
+ reg &= ~CLKDMSK;
+ reg |= CLKD(96000/clkval);
+ MMC1_REG(MMCHS_SYSCTL) = reg;
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for clock stable
+ while((MMC1_REG(MMCHS_SYSCTL) & ICS) == 0) {
+ if(msecElapsed(&tmr)) {
+ printf("sdClkSet: ICS timeout\n");
+ return(-1);
+ }
+ monDelay(1);
+ }
+ MMC1_REG(MMCHS_SYSCTL) |= CEN;
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for clock stable
+ while((MMC1_REG(MMCHS_SYSCTL) & CEN) == 0) {
+ if(msecElapsed(&tmr)) {
+ printf("sdClkSet: ICS timeout\n");
+ return(-1);
+ }
+ monDelay(1);
+ }
+ return(0);
+}
+
+/* sdInit():
+ * This function is called by the "sd init" command on the command line.
+ * Where applicable, the text refers to the section in the Sept 2008
+ * Technical Reference Manual (TRM) from which I got the code/functionality.
+ */
+int
+sdInit(int interface, int verbose)
+{
+ int i, pbiasretry = 0;
+ vulong reg;
+ struct elapsed_tmr tmr;
+
+ /* There's only one interface on the CSB740, so reject anything
+ * other than interface 0...
+ */
+ if (interface != 0)
+ return(-1);
+
+ /*******************************
+ *
+ * Clock configuration:
+ * (TRM 22.5.1.1)
+ */
+ *(vulong *)CM_ICLKEN1_CORE |= EN_MMC1; // Configure interface and
+ *(vulong *)CM_FCLKEN1_CORE |= EN_MMC1; // functional clocks.
+
+ /*******************************
+ *
+ * Not really sure what this is... apparently some kind of clock steering.
+ * I tried both setting the bit and clearing it. Made no difference.
+ * In both cases the clock was present on the CLK pin.
+ */
+ *(vulong *)CONTROL_DEVCONF0 |= MMCSDIO1ADPCLKISEL;
+
+ /********************************
+ *
+ * Set up BIAS (this allows the pins to run at 1.8 or 3.0 volts I think).
+ * This is configured as 0606 in rom_reset.S (i don't think thats right).
+ * Note: The CSB703 ties this interface to 3.3 volts.
+ * TRM 22.5.3
+ * TRM 7.5.2 and flowchart in figure 7-24...
+ */
+pbias_retry:
+ *(vulong *)CONTROL_PBIAS_LITE = PBIAS_LITE_VMMC1_52MHZ;
+ monDelay(100);
+ *(vulong *)CONTROL_PBIAS_LITE |= MMC_PWR_STABLE;
+ monDelay(100);
+ if (*(vulong *)CONTROL_PBIAS_LITE & PBIAS_LITE_MMC1_ERROR) {
+ *(vulong *)CONTROL_PBIAS_LITE &= (~MMC_PWR_STABLE);
+ monDelay(100);
+ if (pbiasretry++ < 3) {
+ goto pbias_retry;
+ }
+ else {
+ printf("sdInit: PBIAS timeout\n");
+ return(-1);
+ }
+ }
+
+#if 0
+ /*******************************
+ *
+ * These registers are things I found when scouring the TRM for "MMC".
+ * I don't think they have any affect on basic startup of the interface
+ * so they are removed for now...
+ */
+ *(vulong *)CM_AUTOIDLE1_CORE &= ~AUTO_MMC1; // Disable auto clock enable
+ *(vulong *)PM_WKEN1_CORE &= ~EN_MMC1; // Disable wakeup event
+ *(vulong *)PM_MPUGRPSEL1_CORE &= ~GRPSEL_MMC1; // Disable mpu-group wakeup
+ *(vulong *)PM_IVA2GRPSEL1_CORE &= ~GRPSEL_MMC1; // Disable iva2-group wakeup
+ *(vulong *)PM_WKST1_CORE &= ~EN_MMC1; // Clear wakeup status
+#endif
+
+ /*******************************
+ *
+ * Issue soft reset and wait for completion...
+ * (TRM 22.5.1.2)
+ */
+ MMC1_REG(MMCHS_SYSCONFIG) |= SRESET; // Software reset
+ if ((MMC1_REG(MMCHS_SYSSTATUS) & RESETDONE) == 0)
+ printf("Good, RESETDONE is low here\n");
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for completion
+ while((MMC1_REG(MMCHS_SYSSTATUS) & RESETDONE) == 0) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: SRST failed\n");
+ return(-1);
+ }
+ }
+ /********************************
+ *
+ * Set SRA bit, then wait for it to clear.
+ */
+ MMC1_REG(MMCHS_SYSCTL) |= SRA;
+ startElapsedTimer(&tmr,MMCTMOUT);
+ while((MMC1_REG(MMCHS_SYSCTL) & SRA)) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: SRA timeout\n");
+ return(-1);
+ }
+ }
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for debounce stable.
+ while((MMC1_REG(MMCHS_PSTATE) & DEBOUNCE) != DEBOUNCE) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: DEBOUNCE timeout\n");
+ return(-1);
+ }
+ }
+
+ /*******************************
+ *
+ * Establish hardware capabilities:
+ * TRM 22.5.1.3
+ */
+ reg = MMC1_REG(MMCHS_CAPA);
+ reg &= ~(VS18 | VS30 | VS33);
+ reg |= VS18;
+ MMC1_REG(MMCHS_CAPA) = reg;
+
+#if 0
+ /********************************
+ *
+ * Enable wakeup mode (don't think I need this, tried both ways)
+ * TRM 22.5.1.4
+ */
+ MMC1_REG(MMCHS_SYSCONFIG) |= ENWAKEUP;
+ MMC1_REG(MMCHS_HCTL) |= IWE;
+#endif
+
+ /********************************
+ *
+ * MMC Host and Bus Configuration
+ * TRM 22.5.1.5
+ */
+ //MMC1_REG(MMCHS_CON) =
+ MMC1_REG(MMCHS_HCTL) &= ~SVDS;
+ MMC1_REG(MMCHS_HCTL) |= SVDS18;
+ monDelay(10);
+ MMC1_REG(MMCHS_HCTL) |= SDBP;
+ monDelay(100);
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for SVDS verification
+ while((MMC1_REG(MMCHS_HCTL) & SDBP) == 0) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: SDBP timeout\n");
+ return(-1);
+ }
+ }
+
+ MMC1_REG(MMCHS_SYSCTL) |= ICE; // Enable internal clock
+
+ MMC1_REG(MMCHS_SYSCTL) &= ~CLKDMSK; // Set clock divisor:
+ MMC1_REG(MMCHS_SYSCTL) |= CLKD(960); // (should be <= 80Khz initially)
+
+ startElapsedTimer(&tmr,MMCTMOUT); // Wait for clock stable
+ while((MMC1_REG(MMCHS_SYSCTL) & ICS) == 0) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: ICS timeout\n");
+ return(-1);
+ }
+ }
+
+ /* I set these two bits with the hope that the clock will be
+ * active even if there is no card installed (so I atleast can
+ * see *some* activity).
+ */
+ MMC1_REG(MMCHS_SYSCTL) |= CEN; // External clock enable
+#if 0
+ MMC1_REG(MMCHS_CON) |= CLKEXTFREE;
+
+ reg = MMC1_REG(MMCHS_SYSCONFIG);
+ reg &= ~SIDLEMODEMSK;
+ reg &= ~CLKACTIVITYMSK;
+ reg &= ~AUTOIDLE;
+ reg |= (SIDLEMODE(1) | CLKACTIVITY(3));
+ MMC1_REG(MMCHS_SYSCONFIG) = reg;
+#endif
+
+ /********************************
+ *
+ * Set the INIT bit to send an initialization stream to the card...
+ * (top of left flowchart in TRM section 22.5.2.1)
+ */
+ MMC1_REG(MMCHS_CON) |= MMCINIT;
+ for(i=0;i<10;i++) {
+ sdCmd(CMD(0) | RSPTYPE_NONE,0,0);
+ monDelay(2);
+ }
+ MMC1_REG(MMCHS_CON) &= ~MMCINIT;
+ MMC1_REG(MMCHS_STAT) = 0xffffffff;
+
+ if (sdClkSet(400) != 0)
+ return(-1);
+
+ /* this is the get_card_type() function in the code from TI...
+ */
+ if (sdCmd(CMD(55) | RSPTYPE_48,0,0) < 0) {
+ printf("Card type = MMC\n");
+ MMC1_REG(MMCHS_CON) |= ODE;
+ }
+ else {
+ if ((MMC1_REG(MMCHS_RSP10) & 0xffff) == 0x0120) {
+ printf("Card type = SD\n");
+ }
+ else {
+ printf("Card type = MMC_CARD\n");
+ MMC1_REG(MMCHS_CON) |= ODE;
+ }
+ }
+
+
+#if 0
+ /********************************
+ *
+ * Send Command 5
+ * (top of right flowchart in TRM section 22.5.2.1)
+ */
+ sdCmd(CMD(5) | RSPTYPE_NONE,0,0);
+
+ startElapsedTimer(&tmr,MMCTMOUT);
+ do {
+ reg = MMC1_REG(MMCHS_STAT);
+ if (reg & CC) {
+ /* For now we assume only SD cards... */
+ printf("SDIO detected!!! Shouldn't be here!\n");
+ return(-1);
+ }
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: CTO timeout1\n");
+ return(-1);
+ }
+
+ } while((reg & CTO) == 0);
+
+ /********************************
+ *
+ * Set SRC bit, then wait for it to clear.
+ * (midway down right flowchart in TRM section 22.5.2.1)
+ */
+ MMC1_REG(MMCHS_SYSCTL) |= SRC;
+ startElapsedTimer(&tmr,MMCTMOUT);
+ while((MMC1_REG(MMCHS_SYSCTL) & SRC)) {
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: SRC timeout\n");
+ return(-1);
+ }
+ }
+
+ sdCmd(CMD(8) | RSPTYPE_NONE,0,0);
+
+ startElapsedTimer(&tmr,MMCTMOUT);
+ do {
+ reg = MMC1_REG(MMCHS_STAT);
+ if (reg & CC) {
+ /* For now we assume only SD cards... */
+ printf("SD BINGO!!! This is where we want to be!\n");
+ return(0);
+ }
+ if(msecElapsed(&tmr)) {
+ printf("sdInit: CTO timeout2\n");
+ return(-1);
+ }
+
+ } while((reg & CTO) == 0);
+
+ /* For now we assume only SD cards... */
+ printf("MMC detected!!! Shouldn't be here!\n");
+#endif
+ return(-1);
+}
+
+int
+sdRead(int interface, char *buf, int blk, int blkcnt)
+{
+ char *from;
+ int size;
+
+ if (interface != 0)
+ return(-1);
+
+ from = (char *)(blk * SD_BLKSIZE);
+ size = blkcnt * SD_BLKSIZE;
+ memcpy(buf,from,size);
+ return(0);
+}
+
+int
+sdWrite(int interface, char *buf, int blk, int blkcnt)
+{
+ char *to;
+ int size;
+
+ if (interface != 0)
+ return(-1);
+
+ to = (char *)(blk * SD_BLKSIZE);
+ size = blkcnt * SD_BLKSIZE;
+ memcpy(to,buf,size);
+ return(0);
+}
+
diff --git a/ports/beagleboneblack/ram_reset.S b/ports/beagleboneblack/ram_reset.S
new file mode 100644
index 0000000..f801b19
--- /dev/null
+++ b/ports/beagleboneblack/ram_reset.S
@@ -0,0 +1,211 @@
+ .file "ram_reset.s"
+
+/*
+ * General notice:
+ * This code is part of a boot-monitor package developed as a generic base
+ * platform for embedded system designs. As such, it is likely to be
+ * distributed to various projects beyond the control of the original
+ * author. Please notify the author of any enhancements made or bugs found
+ * so that all may benefit from the changes. In addition, notification back
+ * to the author will allow the new user to pick up changes that may have
+ * been made by other users after this version of the code was distributed.
+ *
+ * Author: Ed Sutter
+ * email: esutter at lucent.com
+ * phone: 908-582-2351
+ *
+ *
+ * Modified for the CSB740 - OMAP3530 Single Board
+ *
+ * ram_reset.s:
+ */
+
+#include "warmstart.h"
+#include "omap3530.h"
+#include "config.h"
+
+ /*
+ * Have a separate stack for each processor mode.
+ */
+
+ /* define sizes for each mode's stack */
+ .equ FiqStackSz, 4096
+ .equ IrqStackSz, 4096
+ .equ AbtStackSz, 4096
+ .equ UndStackSz, 4096
+ .equ SysStackSz, 4096
+
+ /* declare the stacks */
+ .extern MonStack
+ .global FiqStack
+ .global IrqStack
+ .global AbtStack
+ .global UndStack
+ .global SysStack
+
+ /* allocate the stacks */
+ .comm FiqStack, FiqStackSz /* for the FIQ mode */
+ .comm IrqStack, IrqStackSz /* for the IRQ mode */
+ .comm AbtStack, AbtStackSz /* for the Abort mode */
+ .comm UndStack, UndStackSz /* for the Undef mode */
+ .comm SysStack, SysStackSz /* for the System mode */
+ /* User mode has the same stack as system mode. */
+
+/*********************************************************************/
+
+ .extern start
+
+ .global reset
+ .global coldstart
+ .global lukewarmstart
+ .global warmstart
+ .global ipaddr
+ .global etheraddr
+ .global moncomptr
+
+ .text
+
+ /*
+ * Exception table at address 0
+ */
+reset:
+ b coldstart
+ b undefined_instruction
+ b software_interrupt
+ b abort_prefetch
+ b abort_data
+ b not_assigned
+ b interrupt_request
+ b fast_interrupt_request
+
+#include "etheraddr.S"
+#include "moncomptr.S"
+
+/*********************************************************************/
+
+ /*
+ * At the end of the reset sequence, MMU, Icache, Dcache,
+ * and write buffer are all disabled.
+ * Also IRQs and FIQs are disabled in the processor's CPSR
+ * The operating mode is SVC (supervisory mode), and the
+ * PC is vectored at 0x00000000. A branch in 0x00000000
+ * brings us directly here.
+ *
+ */
+
+coldstart:
+// ldr r0, =0x2001 /* allow access to all coprocessors */
+// mcr p15,0,r0,c15,c1,0
+// nop
+// nop
+// nop
+
+// ldr r0, =0x00000078
+// mcr p15,0,r0,c1,c0,0 /* Disable MMU, caches, write buffer */
+// nop
+// nop
+// nop
+
+// ldr r0, =0x00000000
+// mcr p15,0,r0,c8,c7,0 /* flush TLB's */
+// mcr p15,0,r0,c7,c7,0 /* flush Caches */
+// mcr p15,0,r0,c7,c10,4 /* Flush Write Buffer */
+// nop
+// nop
+// nop
+
+// mvn r0, #0 /* grant manager access to all domains */
+// mcr p15,0,r0,c3,c0,0
+
+/********************************************************************/
+
+midstart:
+ ldr r0, =INITIALIZE
+
+ /* fall-through to 'lukewarmstart' */
+
+/********************************************************************/
+
+lukewarmstart:
+ /* Save the argument to r11 */
+ mov r11, r0
+
+ /*
+ * *** DO NOT TOUCH R11 ***
+ */
+
+ /*
+ * Set-up the stack-pointers for all operating modes
+ */
+
+ /* FIQ mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x11 /* set FIQ mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(FiqStack + FiqStackSz - 4) /* initialize the stack ptr */
+ /* IRQ mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x12 /* set IRQ mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(IrqStack + IrqStackSz - 4) /* initialize the stack ptr */
+ /* Abort mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x17 /* set Abort mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(AbtStack + AbtStackSz - 4) /* initialize the stack ptr */
+ /* Undef mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x1b /* set Undef mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(UndStack + UndStackSz - 4) /* initialize the stack ptr */
+ /* System mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x1f /* set System mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(SysStack + SysStackSz - 4) /* initialize the stack ptr */
+ /* 'warmstart' will take us back to SVC mode
+ stack for SVC mode will also be setup in warmstart */
+
+ mov r0, r11 /* get argument back from r11 */
+
+ b warmstart
+
+
+/********************************************************************/
+
+warmstart:
+ /* Save the argument to r11 */
+ mov r11, r0
+
+ /*
+ * *** DO NOT TOUCH R11 ***
+ */
+
+
+ /* Change (back) to SVC mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x13 /* set System mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ /* Reset the stack pointer for the SVC mode (our current mode) */
+ ldr sp, =(MonStack + MONSTACKSIZE - 4)
+
+ /*
+ * Restore argument which was saved to r11 and jump to
+ * the C function start().
+ */
+
+ mov r0, r11
+jump_to_c:
+ bl start
+
+ /* the C code should never return */
+ b reset
+
+.align 4
+
diff --git a/ports/beagleboneblack/regnames.c b/ports/beagleboneblack/regnames.c
new file mode 100644
index 0000000..9c4747e
--- /dev/null
+++ b/ports/beagleboneblack/regnames.c
@@ -0,0 +1 @@
+#include "regs_arm.c"
diff --git a/ports/beagleboneblack/rom_reset.S b/ports/beagleboneblack/rom_reset.S
new file mode 100644
index 0000000..d2c9cfb
--- /dev/null
+++ b/ports/beagleboneblack/rom_reset.S
@@ -0,0 +1,418 @@
+ .file "rom_reset.S"
+
+/*
+ * General notice:
+ * This code is part of a boot-monitor package developed as a generic base
+ * platform for embedded system designs. As such, it is likely to be
+ * distributed to various projects beyond the control of the original
+ * author. Please notify the author of any enhancements made or bugs found
+ * so that all may benefit from the changes. In addition, notification back
+ * to the author will allow the new user to pick up changes that may have
+ * been made by other users after this version of the code was distributed.
+ *
+ * Author: Ed Sutter
+ * email: esutter at lucent.com
+ * phone: 908-582-2351
+ *
+ *
+ * Modified for the CSB740 - OMAP3530 Single Board
+ *
+ * rom_reset.s:
+ */
+
+#include "warmstart.h"
+#include "omap3530.h"
+#include "config.h"
+
+ /*
+ * Have a separate stack for each processor mode.
+ */
+
+ /* define sizes for each mode's stack */
+ .equ FiqStackSz, 4096
+ .equ IrqStackSz, 4096
+ .equ AbtStackSz, 4096
+ .equ UndStackSz, 4096
+ .equ SysStackSz, 4096
+
+ /* declare the stacks */
+ .extern MonStack
+ .global FiqStack
+ .global IrqStack
+ .global AbtStack
+ .global UndStack
+ .global SysStack
+ .global raise
+ .global cache_init
+
+ /* allocate the stacks */
+ .comm FiqStack, FiqStackSz /* for the FIQ mode */
+ .comm IrqStack, IrqStackSz /* for the IRQ mode */
+ .comm AbtStack, AbtStackSz /* for the Abort mode */
+ .comm UndStack, UndStackSz /* for the Undef mode */
+ .comm SysStack, SysStackSz /* for the System mode */
+ /* User mode has the same stack as system mode. */
+
+/*********************************************************************/
+
+ .extern start
+
+ .global reset
+ .global coldstart
+ .global lukewarmstart
+ .global warmstart
+
+ .text
+
+ /*
+ * Exception table at address 0
+ */
+reset:
+ b coldstart
+ b undefined_instruction
+ b software_interrupt
+ b abort_prefetch
+ b abort_data
+ b not_assigned
+ b interrupt_request
+ b fast_interrupt_request
+
+#include "etheraddr.S"
+#include "moncomptr.S"
+#include "alttfsdevtbl.S"
+
+coldstart:
+ ldr pc, =coldstart_1 // jump to actual ROM location
+ nop
+
+coldstart_1:
+ /* Make sure interrupts are off, and we're in supervisor mode...
+ */
+ mrs r0,cpsr // Retreive current program status register
+ bic r0,r0,#0x1f // Clear all mode bits.
+ orr r0,r0,#0xd3 // Set mode to supervisor, IRQ FIQ disabled.
+ msr cpsr,r0
+
+// bl cache_init
+
+//----------------------------------------------------------
+// Start of Cogent Setup for CSB740 OMAP3530
+//----------------------------------------------------------
+
+init_pbias:
+ ldr r2, =0x00000000 // set bias for sdio1
+ ldr r1, =0x48002520
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000606 // set bias for sdio1
+ ldr r1, =0x48002520
+ str r2, [r1]
+
+ bl delay_200
+init_clocks:
+ ldr r2, =0x00000037 // Enable DPLL1 in lock mode
+ ldr r1, =0x48004904
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x000A7115 // Set DPLL1 (MPU) M = 625, (N +1)= 21 + 1, MPU_CLK = ~545MHz
+ ldr r1, =0x48004940
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x099F1700 // Set DPLL3 (CORE) M = 415, (N +1)= 23 + 1, CORE_CLK = ~332MHz
+ ldr r1, =0x48004D40
+ str r2, [r1]
+
+ bl delay_200
+
+ //ldr r2, =0x00000080 // Enable SYS_CLKOUT2 for debug purposes
+ //ldr r1, =0x48004D70
+ //str r2, [r1]
+
+ //bl delay_200
+
+ ldr r2, =0x43fffe00 // Turn on all available module clocks
+ ldr r1, =0x48004a00
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x7ffffedb // Turn on all available peripheral clocks
+ ldr r1, =0x48004a10
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00006000 // enable auto clock for UART1 and UART2
+ ldr r1, =0x48004a30
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000028 // enable WDT2 and GPIO 1 functional clock
+ ldr r1, =0x48004c00
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x0000002c // enable WDT2, GPIO 1 interface and 32Ksync (for Linux) clock
+ ldr r1, =0x48004c10
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x0003E000 // enable GPIO 2-6 functional clocks
+ ldr r1, =0x48005000
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x0003E000 // enable GPIO 2-6 interface clocks
+ ldr r1, =0x48005010
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000003 // enable DSS1_ALWON_FCLK
+ ldr r1, =0x48004e00
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000001 // enable DSS interface clock
+ ldr r1, =0x48004e10
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x0000100A // Set CLKSEL_DSS1 to divide by 1
+ ldr r1, =0x48004e40
+ str r2, [r1]
+
+ bl delay_200
+
+init_ddr:
+ ldr r2, =0x0000001A // reset DDR
+ ldr r1, =0x6D000010
+ str r2, [r1]
+
+ ldr r1, =0x6D000014 // SDRC_SYSSTATUS
+wait_reset:
+ ldr r2, [r1]
+ tst r2, #1 // test RESETDONE
+ beq wait_reset
+
+ ldr r2, =0x00000018 // release DDR reset
+ ldr r1, =0x6D000010
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000100 // 32-bit SDRAM on data lane [31:0] - CS0
+ ldr r1, =0x6D000044
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x02584099 // SDRC_MCFG0 register
+ ldr r1, =0x6D000080
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00054601 // SDRC_RFR_CTRL0 register
+ ldr r1, =0x6D0000a4
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0xA29DB4C6 // SDRC_ACTIM_CTRLA0 register
+ ldr r1, =0x6D00009c
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00012214 // SDRC_ACTIM_CTRLB0 register
+ ldr r1, =0x6D0000A0
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000081 // Disble Power Down of CKE due to 1 CKE on combo part
+ ldr r1, =0x6D000070
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000000 // NOP command
+ ldr r1, =0x6D0000A8
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000001 // Precharge command
+ ldr r1, =0x6D0000A8
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000002 // Auto-refresh command
+ ldr r1, =0x6D0000A8
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000002 // Auto-refresh command
+ ldr r1, =0x6D0000A8
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x00000032 // SDRC MR0 register Burst length=4
+ ldr r1, =0x6D000084
+ str r2, [r1]
+
+ bl delay_200
+
+ ldr r2, =0x0000000A // SDRC DLLA control register
+ ldr r1, =0x6D000060
+ str r2, [r1]
+
+ bl delay_200
+
+/********************************************************************/
+
+midstart:
+ ldr r0, =INITIALIZE
+
+ /* fall-through to 'lukewarmstart' */
+
+/********************************************************************/
+
+lukewarmstart:
+ /* Save the argument to r11 */
+ mov r11, r0
+
+ /*
+ * *** DO NOT TOUCH R11 ***
+ */
+
+ /*
+ * Set-up the stack-pointers for all operating modes
+ */
+
+ /* FIQ mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x11 /* set FIQ mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(FiqStack + FiqStackSz - 4) /* initialize the stack ptr */
+ /* IRQ mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x12 /* set IRQ mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(IrqStack + IrqStackSz - 4) /* initialize the stack ptr */
+ /* Abort mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x17 /* set Abort mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(AbtStack + AbtStackSz - 4) /* initialize the stack ptr */
+ /* Undef mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x1b /* set Undef mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(UndStack + UndStackSz - 4) /* initialize the stack ptr */
+ /* System mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x1f /* set System mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ ldr sp, =(SysStack + SysStackSz - 4) /* initialize the stack ptr */
+ /* 'warmstart' will take us back to SVC mode
+ stack for SVC mode will also be setup in warmstart */
+
+ mov r0, r11 /* get argument back from r11 */
+ b warmstart
+
+
+/********************************************************************/
+
+warmstart:
+ /* Save the argument to r11 */
+ mov r11, r0
+
+ /*
+ * *** DO NOT TOUCH R11 ***
+ */
+
+
+ /* Change (back) to SVC mode */
+ mrs r0, cpsr /* move CPSR to r0 */
+ bic r0, r0, #0x1f /* clear all mode bits */
+ orr r0, r0, #0x13 /* set System mode bits */
+ msr CPSR_c, r0 /* move back to CPSR */
+ /* Reset the stack pointer for the SVC mode (our current mode) */
+ ldr sp, =(MonStack + MONSTACKSIZE - 4)
+
+ /*
+ * Restore argument which was saved to r11 and jump to
+ * the C function start().
+ */
+
+ mov r0, r11
+jump_to_c:
+ bl start
+
+ /* the C code should never return */
+ b reset
+
+.align 4
+
+
+/*********************************************************************
+ * simple delay loop
+ */
+delay_200:
+ ldr r3, =200 /* loop count */
+delay_loop:
+ subs r3,r3,#1
+ bne delay_loop
+ nop
+
+ mov pc, lr
+
+raise: mov pc, lr /* to make linker happy */
+
+/*********************************************************************
+ * Cache initialization:
+ * Turn everything down and invalidate...
+ */
+cache_init:
+ /* Make sure caches are turned down...
+ */
+ mrc p15, 0, r3, cr1, cr0, 0 // turn off I/D-cache
+ bic r3, r3, #4096 // I
+ bic r3, r3, #4 // D
+ mcr p15, 0, r3, cr1, cr0, 0
+
+ mov r0, #0
+// mcr p15, 0, r0, cr7, cr7, 0 // arm_cache_invalidate
+ mcr p15, 0, r0, cr7, cr6, 0 // arm_dcache_invalidate
+ mcr p15, 0, r0, cr7, cr5, 0 // arm_icache_invalidate
+
+ mrc p15, 0, r0, cr1, cr0, 1 // l2cache_disable
+ bic r0, r0, #2
+ mcr p15, 0, r0, cr1, cr0, 1
+
+ mov r0, #1
+ mrc p15, 1, r0, cr0, cr0, 1 // emu_ext_boot_l2_inv
+ mov pc, lr
+
diff --git a/ports/beagleboneblack/target_version.h b/ports/beagleboneblack/target_version.h
new file mode 100644
index 0000000..4abd503
--- /dev/null
+++ b/ports/beagleboneblack/target_version.h
@@ -0,0 +1,17 @@
+/* target_version.h:
+ * Initial version for all ports is zero. As the TARGET_VERSION incrments
+ * as a result of changes made to the target-specific code, this file should
+ * be used as an informal log of those changes for easy reference by others.
+ *
+ * 0: UART/DRAM/FLASH/TFS working through BDI2000
+ * 0->1: Boots from flash (without bdi2000), sleep delay adjusted.
+ * 1->2: Ethernet added.
+ * 2->3: LCD interface added.
+ * 3->4: Flash driver fix, enabled INCLUDE_HWTMR, and added show_version(),
+ * and the splash screen is loaded from TFS.
+ * 4->5: Added support for the FBI (frame buffer) interface, and hard-reset.
+ * 5->6: Speedup (clock configuration) provided by Luis; also changed
+ * cpuio.c so that SPI-mode of the touch-screen interface now works.
+ */
+
+#define TARGET_VERSION 6
diff --git a/ports/beagleboneblack/tfsdev.h b/ports/beagleboneblack/tfsdev.h
new file mode 100644
index 0000000..4331851
--- /dev/null
+++ b/ports/beagleboneblack/tfsdev.h
@@ -0,0 +1,31 @@
+/* tfsdev.h:
+ This file is ONLY included by tfs.c. It is seperate from tfs.h because
+ it is target-specific. It is not part of config.h because it includes
+ the declaration of the tfsdevtbl[].
+ A prefix in the name of the file determines what device is used to store
+ that file. If no prefix is found the the first device in the table is
+ used as a default. The syntax of the prefix is "//STRING/" where STRING
+ is user-definable, but the initial // and final / are required by tfs
+ code.
+*/
+
+struct tfsdev tfsdevtbl[] = {
+ { "//FLASH/",
+ TFSSTART,
+ TFSEND,
+ TFSSPARE,
+ TFSSPARESIZE,
+ TFSSECTORCOUNT,
+ TFS_DEVTYPE_FLASH, },
+
+#ifdef FLASHRAM_BASE
+ { "//RAM/",
+ FLASHRAM_BASE,
+ FLASHRAM_END-FLASHRAM_SECTORSIZE,
+ FLASHRAM_END-FLASHRAM_SECTORSIZE+1,
+ FLASHRAM_SECTORSIZE,
+ FLASHRAM_SECTORCOUNT-1,
+ TFS_DEVTYPE_RAM | TFS_DEVINFO_AUTOINIT, },
+#endif
+ { 0, TFSEOT,0,0,0,0,0 }
+};
diff --git a/ports/beagleboneblack/xcmddcl.h b/ports/beagleboneblack/xcmddcl.h
new file mode 100644
index 0000000..13552a3
--- /dev/null
+++ b/ports/beagleboneblack/xcmddcl.h
@@ -0,0 +1,34 @@
+
+/* extcmddcl.h: */
+/* This file must exist even if it is empty because it is #included in the */
+/* common file cmdtbl.c. The purpose is to keep the common comand table */
+/* file (common/cmdtbl.c) from being corrupted with non-generic commands */
+/* that may be target specific. */
+/* It is the declaration portion of the code that must be at the top of */
+/* the cmdtbl[] array. */
+/* For example:
+
+extern int dummycmd(); Function declaration.
+extern char *dummyHelp[]; Command help array declaration.
+
+*/
+
+extern int date();
+extern char *dateHelp[];
+
+#if INCLUDE_LCD
+extern int lcd_tst();
+extern char *lcd_tstHelp[];
+#endif
+
+//extern int i2c();
+//extern char *i2cHelp[];
+
+extern int nandCmd();
+extern char *nandHelp[];
+
+extern int ads();
+extern char *adsHelp[];
+
+extern int ldatags();
+extern char *ldatagsHelp[];
diff --git a/ports/beagleboneblack/xcmdtbl.h b/ports/beagleboneblack/xcmdtbl.h
new file mode 100644
index 0000000..334218c
--- /dev/null
+++ b/ports/beagleboneblack/xcmdtbl.h
@@ -0,0 +1,19 @@
+/* extcmdtbl.h: */
+/* This file must exist even if it is empty because it is #included in the */
+/* common file cmdtbl.c. The purpose is to keep the common comand table */
+/* file (common/cmdtbl.c) from being corrupted with non-generic commands */
+/* that may be target specific. */
+/* It is the entry in the command table representing the new command being */
+/* added to the cmdtbl[] array. */
+/* For example:
+ "dummy", dummycmd, dummyHelp,
+*/
+{"ads", ads, adsHelp,},
+//{"i2c", i2c, i2cHelp,},
+#if INCLUDE_LCD
+{"lcd_tst", lcd_tst, lcd_tstHelp,},
+#endif
+{"ldatags", ldatags, ldatagsHelp,},
+#if INCLUDE_NANDCMD
+{"nand", nandCmd, nandHelp,},
+#endif
--
2.3.3
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