[PATCH 01/13] Removed csb740 OMAP3530 setup in rom_reset.S in BBB port

[Jarielle Catbagan]

---
 ports/beagleboneblack/rom_reset.S | 190 --------------------------------------
 1 file changed, 190 deletions(-)

diff --git a/ports/beagleboneblack/rom_reset.S b/ports/beagleboneblack/rom_reset.S
index d2c9cfb..800a9a1 100644
--- a/ports/beagleboneblack/rom_reset.S
+++ b/ports/beagleboneblack/rom_reset.S
@@ -95,196 +95,6 @@ coldstart_1:
 
 //	bl cache_init
 
-//----------------------------------------------------------
-// Start of Cogent Setup for CSB740 OMAP3530
-//----------------------------------------------------------
-
-init_pbias:
-	ldr r2, =0x00000000			// set bias for sdio1 
-	ldr r1, =0x48002520
-	str r2, [r1]
-
-	bl	delay_200
-
-	ldr r2, =0x00000606			// set bias for sdio1
-	ldr r1, =0x48002520
-	str r2, [r1]
-
-	bl	delay_200
-init_clocks:
-	ldr r2, =0x00000037			// Enable DPLL1 in lock mode
-	ldr r1, =0x48004904
-	str r2, [r1]
-
-	bl	delay_200
-
-	ldr r2, =0x000A7115			// Set DPLL1 (MPU) M = 625, (N +1)= 21 + 1, MPU_CLK = ~545MHz
-	ldr r1, =0x48004940
-	str r2, [r1]
-
-	bl	delay_200
-
-	ldr r2, =0x099F1700			// Set DPLL3 (CORE) M = 415, (N +1)= 23 + 1, CORE_CLK = ~332MHz
-	ldr r1, =0x48004D40
-	str r2, [r1]
-
-	bl	delay_200
-
-	//ldr r2, =0x00000080			// Enable SYS_CLKOUT2 for debug purposes
-	//ldr r1, =0x48004D70
-	//str r2, [r1]
-
-	//bl	delay_200
-
-	ldr r2, =0x43fffe00			// Turn on all available module clocks
-	ldr r1, =0x48004a00
-	str r2, [r1]
-
-	bl	delay_200
-
-	ldr r2, =0x7ffffedb			// Turn on all available peripheral clocks
-	ldr r1, =0x48004a10
-	str r2, [r1]
-
-	bl	delay_200
-
-	ldr r2, =0x00006000			// enable auto clock for UART1 and UART2
-	ldr r1, =0x48004a30
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x00000028			// enable WDT2 and GPIO 1 functional clock
-	ldr r1, =0x48004c00
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x0000002c			// enable WDT2, GPIO 1 interface and 32Ksync (for Linux) clock
-	ldr r1, =0x48004c10
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x0003E000			// enable GPIO 2-6 functional clocks
-	ldr r1, =0x48005000
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x0003E000			// enable GPIO 2-6 interface clocks
-	ldr r1, =0x48005010
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x00000003			// enable DSS1_ALWON_FCLK
-	ldr r1, =0x48004e00
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x00000001			// enable DSS interface clock
-	ldr r1, =0x48004e10
-	str r2, [r1]
-
-	bl	delay_200
-	
-	ldr r2, =0x0000100A			// Set CLKSEL_DSS1 to divide by 1
-	ldr r1, =0x48004e40
-	str r2, [r1]
-
-	bl	delay_200
-	
-init_ddr:
-    ldr r2, =0x0000001A			// reset DDR 
-    ldr r1, =0x6D000010
-    str r2, [r1]
-
-    ldr r1, =0x6D000014			// SDRC_SYSSTATUS
-wait_reset:
-    ldr r2, [r1]
-    tst r2, #1				// test RESETDONE
-    beq wait_reset
-
-    ldr r2, =0x00000018			// release DDR reset
-    ldr r1, =0x6D000010
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000100			// 32-bit SDRAM on data lane [31:0] - CS0
-    ldr r1, =0x6D000044
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x02584099			// SDRC_MCFG0 register
-    ldr r1, =0x6D000080
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00054601			// SDRC_RFR_CTRL0 register
-    ldr r1, =0x6D0000a4
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0xA29DB4C6			// SDRC_ACTIM_CTRLA0 register
-    ldr r1, =0x6D00009c
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00012214			// SDRC_ACTIM_CTRLB0 register
-    ldr r1, =0x6D0000A0
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000081			// Disble Power Down of CKE due to 1 CKE on combo part
-    ldr r1, =0x6D000070
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000000			// NOP command 
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000001			// Precharge command  
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000002			// Auto-refresh command  
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000002			// Auto-refresh command  
-    ldr r1, =0x6D0000A8
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x00000032			// SDRC MR0 register Burst length=4  
-    ldr r1, =0x6D000084
-    str r2, [r1]
-
-	bl	delay_200
-
-    ldr r2, =0x0000000A			// SDRC DLLA control register  
-    ldr r1, =0x6D000060
-    str r2, [r1]
-
-	bl	delay_200
-
 /********************************************************************/
 
 midstart:
-- 
2.3.3