stacking of rtems_clock_tick?

[Joel Sherrill]

"Aaron J. Grier" wrote:
> 
> On Fri, Aug 18, 2000 at 09:19:09AM -0500, Joel Sherrill wrote:
> 
> > "Aaron J. Grier" wrote:
> > >
> > > sp tests 11, 14, 22, and 24 are all bombing out with
> > >
> > > _Thread_Dispatch_disable_level is (0) not 1
> > >
> > > any ideas?
> >
> > Which version of RTEMS are you using?
> 
> 4.5.0-beta3a.

The code is OK then... read on...

> > This integrity check was fairly recently added and some tests tried to
> > print from context switch user extensions which ended up violating
> > this.
> >
> > Where is the failure?
> 
> c/src/tests/sptests/sp11/timer.c line #95, in TA2_send_10_to_self()
> 
> c/src/tests/sptests/sp14/task1.c line #31, in Signal_3_to_task_1()
> 
> c/src/tests/sptests/sp22/delay.c line #30, in Delayed_resume()
> 
> c/src/tests/sptests/sp24/resume.c line #32, in Resume_task()
> 
> all failures are generated from the directive_failed_with_level macro,
> and all above functions are being called from _Watchdog_Tickle.

I checked sp11 in particular and the code assumes that the timer
routine is being invoked from clock_tick from an ISR.  See below..

> shouldn't _Thread_Dispatch_disable_level be 0 if you're being called
> from a watchdog, since _Watchdog_Tickle_Ticks is separate from
> _Thread_Dispatch?

No... _Thread_Dispatch_disable_level is a critical section counter
and is always >= _ISR_Nest_level.  In a clock tick ISR, the count
should be >=1 and so should the _Thread_Dispatch_disable_level.
If the ISR occurs inside an RTEMS critical section, then 
_ISR_Nest_level = _Thread_Dispatch_disable_level + 1.  If outside
an RTEMS critical section _ISR_Nest_level ==
_Thread_Dispatch_disable_level.

In this case, I have no idea how the timer is being fired from
an environment where _Thread_Dispatch_disable_level is 0!!!!
This looks to me like the ISR_DIspatching code is not incrementing
_Thread_Dispatch_disable_level for some reason.  I recall you
are on a 6830x.  Do you have a VBR or are you using the 68000-style
interrupt tricks?  Handwalk through the isr vectoring code.  The
first instruction in _ISR_Dispatch is this:

        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable
multitasking

So it should be >= 1 if you are really invoked from an ISR.

Chris Johns... do you have any suggestions?  I think he started
with the gen68302 BSP?

> --
>   Aaron J. Grier   |    Frye Electronics, Tigard, OR   |   aaron at frye.com
>    "Cthulhu for President. Why settle for a lesser evil?" -- Matt Minnis

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel at OARcorp.com                 On-Line Applications Research
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