MPC860 tlb exception handling

[Gunter Magin]

Hi,

can somebody please explain what's behind the code snippet in RTEMS-4.0's:

c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S:

    .org    itlbm_vector - file_base
itlbm_vectors:
    mfspr   r2, 784      /* MI_CTR */
    mfspr   r3, 792      /* MD_CTR */
    .....
    mfspr   r19, 825      /* M_RAM0 */
    mfspr   r20, 826      /* M_RAM1 */
    .long   0

    .org    dtlbm_vector - file_base
dtlbm_vectors:
    mfspr   r1, 0x1a

itlbm is supposed to be an exception handler for instruction TLB miss 
exceptions. Same applies for dtlbm, itlbe, dtlbe exceptions.

After heavy storing the MMU-spr's into gpr's, this pseudo-opcode 
".long 0" looks strange. It is not a valid PPC opcode, so yet another
exception will be raised. However the TLB exceptions are not yet handled
enough for a next exception to be recoverable.

I don't know, if TLB exceptions are raised at all under RTEMS, probably not. 
So I wonder why there is this spr fiddling at all...

gm