PowerPC FP handling weakness.

[Sergei Organov]

Duncan Smith <dds at flavors.com> writes:
[...]
> At Flavors we have been using RTEMS for 4 or 5 years on 604/604e MPC105/106,
> VME boards.  Although the version we use is an old one, the BSP requirement
> is probably similar.
> 
> In our own BSP we do lazy FPU context switching based on actual use of FP
> through the FP fault.
>

As an exercise I also implemented similar FPU context switching for another
RTOS, and have faced with one subtle problem. The FP enable and interrupts
enable bits are in the same MSR register. When on-demand context switch is
used, the FP bit in MSR can be cleared any time if scheduling is enabled. This
fact makes it impossible to use _ISR_Disable/_ISR_Enable pair in the form they
are now, because the value of FP bit could be lost: _ISR_Disable reads MSR
with FP bit set, then interrupts/context switches occur that clear FP bit,
then interrupts are disabled by writing MSR with old value with cleared
interrupts bit but set FP bit (here the right value of FP bit is lost), then
FP instruction is executed and clobbers FP context owned by different task.

One solution to the problem is to always clear FP bit in _ISR_Disable. This
can lead to unnecessary FP context switches though.

How did you solve the problem?

BR,
Sergei.