Q powerpc new exception processing.

[Joel Sherrill]

Charles-Antoine Gauthier wrote:
> 
> Sergei Organov wrote:
> >
> > Joel Sherrill <joel.sherrill at oarcorp.com> writes:
> > > Sergei Organov wrote:
> > > >
> > > > Hello,
> > > >
> > > > I'm going to switch to new exception processing model for mpc505/509
> > > > processors. In 'cpu_asm.S' in the 'new_exception_processing' subdirectory
> > > > routines '_CPU_Context_save_fp' and '_CPU_Context_restore_fp' are changed
> > > > compared to the version in 'old_exception_processing'. They don't contain
> > > > "double" version anymore, i.e. loading/storing of FP registers is
> > > > unconditionally made using 'stfs/lfs' instructions. Do I need to return double
> > > > version back, or am I missing something?
> > >
> > > I suppose you might as well restore this double option.  I believe there
> > > was some discussion that it may not have the dramatic benefits once
> > > believed
> > > but having it available makes it possible to enable it when it will be
> > > of use.
> >
> > Now I understand even less than before :-( AFAIK most PowerPC processors that
> > have FP have 64 bits FP registers, i.e. they have "double" FPU and in my
> > understanding for such processors using 'stfs/lfs' to save/restore FP
> > registers is just wrong. Are 750 and 604 that seem to be the only two
> > processors supported by the new exception processing different in this area?
> > Why 'single' instructions are used in the first place? Isn't it correct to
> > just replace them with 'double' version?
> 
> stfs CONVERTS the content of a double precision FPR to single precision
> before storing to memory, while lfs CONVERT from single to double
> precision on a load. Clearly, using stfs/lfs is wrong.
> 
> Maybe the original author can explain what we don't understand.

This code may indeed be unneccessary then.  THe original PowerPC port
was
to a 403 and the FP code was based on "the architecture book" with no 
use on real HW until later.  This code may never have been used or
necessary.

My understanding is that (on paper) the PowerPC architecture does
not require implementations to have 64-bit floating point HW and allows
for 32-bit FPUs.  This allowance may never have bene taken in practice.

> >
> > Thanks in advance,
> > Sergei.
> 
> --
> Charles-Antoine Gauthier
> Institute for Information Technology   Institut de technologie de
> l'information
> National Research Council of Canada    Conseil national de recherches du
> Canada

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