Problems with starting new BSP

Correo Fernando-ruiz (E-mail) correo at
Tue Jul 10 20:31:45 UTC 2001

Hi Ralf.

> -----Mensaje original-----
> De: corsepiu [mailto:corsepiu]En nombre de Ralf Corsepius
> Enviado el: martes, 10 de julio de 2001 21:17
> Para: fernando.ruiz at
> CC: 'Radzislaw Galler'; 'Joel Sherrill'; 'Radzislaw Galler';
> rtems-users at; jmills at
> Asunto: Re: Problems with starting new BSP
> > ------------- END OF EXAMPLE ---------------
> >
> <Sigh> this bug finally seems to be fixed </sigh>
> This will open opportunities for me to clean up some parts of the
> sh-port's code.

It's possible including a new include file in order to simplify the life
at the programmers when a new clean code from the scratch is writed instead
translation from open source code (linux,Bsd,...)

I think that the memory mapped registers can be managed in a way more
that the linux read8() write16() etc macros.

With this file we add three ways to make the same thing.
All the actual code is compatible but
the original Hitachi EVB registers can be accessed adding a simple '_' at
of the macro numerical value rewrited by you.

The bits of the registers can be accessed using bit_fields.

I have used all of this im my implementation and works very well
(sauf erreur, bien sur)

A bref example:

 * ****************************************
 * SCI Programming
 * ****************************************

typedef struct {
 unsigned char _CA  :1;
 unsigned char _CHR :1;
 unsigned char _PE  :1;
 unsigned char _OE  :1;
 unsigned char _STOP:1;
 unsigned char _MP  :1;
 unsigned char _CKS :2;

typedef struct {
 unsigned char _TIE :1;
 unsigned char _RIE :1;
 unsigned char _TE  :1;
 unsigned char _RE  :1;
 unsigned char _MPIE:1;
 unsigned char _TEIE:1;
 unsigned char _CKE :2;

typedef struct {
 unsigned char _TDRE:1;
 unsigned char _RDRF:1;
 unsigned char _ORER:1;
 unsigned char _FER :1;
 unsigned char _PER :1;
 unsigned char _TEND:1;
 unsigned char _MPB :1;
 unsigned char _MPBT:1;

#define SCI0_CA   (((volatile TSMR*)(SCI0_SMR))->_CA)
#define SCI0_CHR  (((volatile TSMR*)(SCI0_SMR))->_CHR)
#define SCI0_PE   (((volatile TSMR*)(SCI0_SMR))->_PE)
#define SCI0_OE   (((volatile TSMR*)(SCI0_SMR))->_OE)
#define SCI0_STOP (((volatile TSMR*)(SCI0_SMR))->_STOP)
#define SCI0_MP   (((volatile TSMR*)(SCI0_SMR))->_MP)
#define SCI0_CKS  (((volatile TSMR*)(SCI0_SMR))->_CKS)

#define SCI0_TIE  (((volatile TSCR*)(SCI0_SCR))->_TIE)
#define SCI0_RIE  (((volatile TSCR*)(SCI0_SCR))->_RIE)
#define SCI0_TE   (((volatile TSCR*)(SCI0_SCR))->_TE)
#define SCI0_RE   (((volatile TSCR*)(SCI0_SCR))->_RE)
#define SCI0_MPIE (((volatile TSCR*)(SCI0_SCR))->_MPIE)
#define SCI0_TEIE (((volatile TSCR*)(SCI0_SCR))->_TEIE)
#define SCI0_CKE  (((volatile TSCR*)(SCI0_SCR))->_CKE)

#define SCI0_TDRE (((volatile TSSR*)(SCI0_SSR))->_TDRE)
#define SCI0_RDRF (((volatile TSSR*)(SCI0_SSR))->_RDRF)
#define SCI0_ORER (((volatile TSSR*)(SCI0_SSR))->_ORER)
#define SCI0_FER  (((volatile TSSR*)(SCI0_SSR))->_FER)
#define SCI0_PER  (((volatile TSSR*)(SCI0_SSR))->_PER)
#define SCI0_TEND (((volatile TSSR*)(SCI0_SSR))->_TEND)
#define SCI0_MPB  (((volatile TSSR*)(SCI0_SSR))->_MPB)
#define SCI0_MPBT (((volatile TSSR*)(SCI0_SSR))->_MPBT)

#define SCI1_CA   (((volatile TSMR*)(SCI1_SMR))->_CA)
#define SCI1_CHR  (((volatile TSMR*)(SCI1_SMR))->_CHR)
#define SCI1_PE   (((volatile TSMR*)(SCI1_SMR))->_PE)
#define SCI1_OE   (((volatile TSMR*)(SCI1_SMR))->_OE)
#define SCI1_STOP (((volatile TSMR*)(SCI1_SMR))->_STOP)
#define SCI1_MP   (((volatile TSMR*)(SCI1_SMR))->_MP)
#define SCI1_CKS  (((volatile TSMR*)(SCI1_SMR))->_CKS)

#define SCI1_TIE  (((volatile TSCR*)(SCI1_SCR))->_TIE)
#define SCI1_RIE  (((volatile TSCR*)(SCI1_SCR))->_RIE)
#define SCI1_TE   (((volatile TSCR*)(SCI1_SCR))->_TE)
#define SCI1_RE   (((volatile TSCR*)(SCI1_SCR))->_RE)
#define SCI1_MPIE (((volatile TSCR*)(SCI1_SCR))->_MPIE)
#define SCI1_TEIE (((volatile TSCR*)(SCI1_SCR))->_TEIE)
#define SCI1_CKE  (((volatile TSCR*)(SCI1_SCR))->_CKE)

#define SCI1_TDRE (((volatile TSSR*)(SCI1_SSR))->_TDRE)
#define SCI1_RDRF (((volatile TSSR*)(SCI1_SSR))->_RDRF)
#define SCI1_ORER (((volatile TSSR*)(SCI1_SSR))->_ORER)
#define SCI1_FER  (((volatile TSSR*)(SCI1_SSR))->_FER)
#define SCI1_PER  (((volatile TSSR*)(SCI1_SSR))->_PER)
#define SCI1_TEND (((volatile TSSR*)(SCI1_SSR))->_TEND)
#define SCI1_MPB  (((volatile TSSR*)(SCI1_SSR))->_MPB)
#define SCI1_MPBT (((volatile TSSR*)(SCI1_SSR))->_MPBT)

 * Now the old style access adding '_'

#define SCI0_SMR_ (*(volatile unsigned char *)(SCI0_SMR))
#define SCI0_BRR_ (*(volatile unsigned char *)(SCI0_BRR))
#define SCI0_SCR_ (*(volatile unsigned char *)(SCI0_SCR))
#define SCI0_TDR_ (*(volatile unsigned char *)(SCI0_TDR))
#define SCI0_SSR_ (*(volatile unsigned char *)(SCI0_SSR))
#define SCI0_RDR_ (*(volatile unsigned char *)(SCI0_RDR))

#define SCI1_SMR_ (*(volatile unsigned char *)(SCI1_SMR))
#define SCI1_BRR_ (*(volatile unsigned char *)(SCI1_BRR))
#define SCI1_SCR_ (*(volatile unsigned char *)(SCI1_SCR))
#define SCI1_TDR_ (*(volatile unsigned char *)(SCI1_TDR))
#define SCI1_SSR_ (*(volatile unsigned char *)(SCI1_SSR))
#define SCI1_RDR_ (*(volatile unsigned char *)(SCI1_RDR))

---------------- END OF EXAMPLE ---------------
I have used your numerical definitions avoiding errors of

The gcc code is very optimized to profite the bitfield feature.

All the registers have been writed.


home: correo at
work: fernando.ruiz at

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