SEVERE Bug in mc68360 _ISR_Handler???
Chris Johns
cjohns at cybertec.com.au
Wed Jul 18 13:47:46 UTC 2001
Joel Sherrill wrote:
>
> Chris could you repost it to the list. Eric Norum and I wondered
> if the logic to enable it should be something like:
>
> HAS_SEPARATE_STACKS==0 && COLDFIRE==0 && 060==0
>
I also think this is the correct combination.
>
> I will then put this in the 4.5 branch, mainline, and
> in a patches directory on the ftp server.
>
Great. A big thanks to Thomas for the analysis.
--
Chris Johns, cjohns @ cybertec.com.au
-------------- next part --------------
*** rtems-4.5.0.orig/c/src/exec/score/cpu/m68k/cpu_asm.S Fri Mar 30 12:55:35 2001
--- rtems-4.5.0/c/src/exec/score/cpu/m68k/cpu_asm.S Wed Jul 18 23:44:51 2001
***************
*** 221,226 ****
--- 221,245 ----
bne exit | NOT outer level, so branch
#endif
+ /*
+ * Check the PC on the stack to see if it is _ISR_Handler. If it
+ * is we have the case of nesting interrupts without the dispatch
+ * level being incremented. The processor places the next instruction
+ * that is to be executed when the RTE instruction is executed on the
+ * stack. If we find we have nested without the dispatch level being
+ * incremented simply return from the exception to allow the outer
+ * to execute.
+ *
+ * The Coldfire and 68060 let the first instruction execute before
+ * processing a new higher priority interrupt so do not need to
+ * perform this test.
+ */
+
+ #if ( M68K_HAS_SEPARATE_STACKS == 0 && M68K_COLDFIRE_ARCH == 0 && M68K_68060_ARCH == 0 )
+ cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET)
+ beq exit
+ #endif
+
tstl SYM (_Context_Switch_necessary)
| Is thread switch necessary?
bne bframe | Yes, invoke dispatcher
***************
*** 229,235 ****
| signals sent to Run_thread
| while in interrupt handler?
beq exit | No, then exit
-
bframe: clrl SYM (_ISR_Signals_to_thread_executing)
| If sent, will be processed
--- 248,253 ----
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