MPC555 : wrong assembly instruction with GCC

[Joel Sherrill]

Sergei Organov wrote:
> 
> It's not gcc. I believe gcc knows nothing about cache.
> 
> Take a look at macro call
> 
> _CPU_Data_Cache_Block_Flush( slot );
> 
> at the end of the routine -- it's definition contains explicit asm statement
> containing 'dcbf' instruction.

In which case, RTEMS needs to wrap this with a conditional on CPU type
(or better yet move it to libcpu).

> Sergei.
> 
> SMIALEK Yan <Yan.SMIALEK at criltechnology.com> writes:
> > Hello,
> >
> > I managed to compile a program for a MPC555 with GCC and I use SingleStep
> > from WindRiver to debug it.
> >
> > But, GCC creates an illegal assembly instruction in the cpu.s file (from
> > cpu.c file), at the end of function _CPU_ISR_install_raw_handler .
> > This instruction is " dcbf "  and is about the cache memory.
> >
> > Unfortunately, the MPC555 doesn't have any instructions or data cache memory
> > !   :-(
> >
> > I suppose this problem comes from GCC (maybe the mcpu option).
> > I tried the mcpu option with powerpc, power, power2, 603, 505 .... But I
> > can't find a similar processor with no cache memory for this option.
> >
> > Does anyone has an idea for this error ?
> >
> > Thank you !
> > Yan

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Joel Sherrill, Ph.D.             Director of Research & Development
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