MPC555 : wrong assembly instruction with GCC

Tue Apr 30 12:09:45 UTC 2002

I removed the _CPU_Data_Cache_Block_Flush function from
_CPU_ISR_install_raw_handler in the cpu.c file.

I think that removing this function from cpu.c is not very good (for
portability), I'll maybe have to find an other solution for the final
version of the MPC555 BSP.

Now, I can compile and execute my program under SingleStep correctly  :-)
(But I'll have a lot of work with the console driver... )

Thank you !


-----Message d'origine-----
De: Sergei Organov [mailto:osv at]
Date: mardi 30 avril 2002 13:33
À: joel.sherrill at
Cc: Yan.SMIALEK at; 'rtems-users at'
Objet: Re: MPC555 : wrong assembly instruction with GCC

Joel Sherrill <joel.sherrill at> writes:
> Sergei Organov wrote:
> > 
> > It's not gcc. I believe gcc knows nothing about cache.
> > 
> > Take a look at macro call
> > 
> > _CPU_Data_Cache_Block_Flush( slot );
> > 
> > at the end of the routine -- it's definition contains explicit asm
> > containing 'dcbf' instruction.
> In which case, RTEMS needs to wrap this with a conditional on CPU type
> (or better yet move it to libcpu).

Yes, it seems that there are still quite a few issues to be resolved in the
"new exception processing" code...

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