MPC555 : wrong assembly instruction with GCC

[Joel Sherrill]

Sergei Organov wrote:
> 
> Joel Sherrill <joel.sherrill at OARcorp.com> writes:
> > Sergei Organov wrote:
> > >
> > > It's not gcc. I believe gcc knows nothing about cache.
> > >
> > > Take a look at macro call
> > >
> > > _CPU_Data_Cache_Block_Flush( slot );
> > >
> > > at the end of the routine -- it's definition contains explicit asm statement
> > > containing 'dcbf' instruction.
> >
> > In which case, RTEMS needs to wrap this with a conditional on CPU type
> > (or better yet move it to libcpu).
> 
> Yes, it seems that there are still quite a few issues to be resolved in the
> "new exception processing" code...

I think it is more likely that the sheer number of variations
in the PowerPC family is too blame.  No single person has a 
complete grasp on what changes or stays the same between
different PowerPC CPU models.

With help from a former Motorola Semiconductor person, I have 
been trying to get a clearer picture of the CPUs.   It turns 
out there are only a handful of CPU cores which are used 
again and again.  There is a pattern to the part number which
indicates the core.  The cache varies widely in spite of that.

Just to doublecheck my info, does the MPC555 have an FPU?
Is it essentially a 601 class CPU?  From your perspective
it may look like a 603 with peripherals.

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel at OARcorp.com                 On-Line Applications Research
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