-current gcc patches for m68k
Aaron J. Grier
aaron at frye.com
Wed Jan 9 23:34:48 UTC 2002
in a procrastinative state between device driver hacking, I've been
trying to get m68k-rtems target compiled from the -current cvs versions
of gcc and binutils on one of my NetBSD/i386 boxes. I found the
following (minor) patches necessary to get gcc to compile.
the m68k libstdc++-v3 patch for atomicity.h is untested... I have no
idea if libstdc++-v3 even works with RTEMS (but am curious to try it
out) but have to get it compiling first. ;)
I've already submitted the lisbtdc++-v3 patch, but haven't done anything
with the config.gcc parts yet.
--
Aaron J. Grier | Frye Electronics, Tigard, OR | aaron at frye.com
"In a few thousand years people will be scratching their heads
wondering how on earth the first computer was invented and
bootstrapped without a prior computer to do it with."
-- Chris Malcolm, on comp.arch
-------------- next part --------------
Index: gcc/config.gcc
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config.gcc,v
retrieving revision 1.140
diff -u -r1.140 config.gcc
--- config.gcc 2002/01/07 01:30:10 1.140
+++ config.gcc 2002/01/09 23:22:12
@@ -1972,7 +1972,7 @@
;;
m68k-*-rtemscoff*)
tmake_file="m68k/t-m68kbare t-rtems"
- tm_file=m68k/rtems.h
+ tm_file="m68k/rtems.h m68k/m68k.h"
float_format=m68k
if test x$enable_threads = xyes; then
thread_file='rtems'
@@ -1980,7 +1980,7 @@
;;
m68k-*-rtemself*|m68k-*-rtems*)
tmake_file="m68k/t-m68kbare t-rtems m68k/t-crtstuff"
- tm_file=m68k/rtemself.h
+ tm_file="m68k/rtemself.h m68k/m68k.h"
float_format=m68k
extra_parts="crtbegin.o crtend.o"
if test x$enable_threads = xyes; then
Index: gcc/config/m68k/rtemself.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68k/rtemself.h,v
retrieving revision 1.5
diff -u -r1.5 rtemself.h
--- rtemself.h 2001/08/04 01:31:35 1.5
+++ rtemself.h 2002/01/09 23:22:21
@@ -30,6 +30,9 @@
#define CPP_PREDEFINES "-Dmc68000 -Drtems -D__rtems__ -D__ELF__ \
-Asystem=rtems -Acpu=mc68000 -Acpu=m68k -Amachine=m68k"
+/* set TARGET_DEFAULT to match CPP_PREDEFINES as above, IE plain 68000 */
+#define TARGET_DEFAULT (MASK_BITFIELD)
+
/* Generate calls to memcpy, memcmp and memset. */
#ifndef TARGET_MEM_FUNCTIONS
#define TARGET_MEM_FUNCTIONS
Index: libstdc++-v3/config/cpu/m68k/bits/atomicity.h
===================================================================
RCS file: /cvs/gcc/egcs/libstdc++-v3/config/cpu/m68k/bits/atomicity.h,v
retrieving revision 1.2
diff -u -r1.2 atomicity.h
--- atomicity.h 2001/08/15 16:00:45 1.2
+++ atomicity.h 2002/01/09 23:23:32
@@ -1,6 +1,6 @@
-// Low-level functions for atomic operations: m680x0, x >= 2 version -*- C++ -*-
+// Low-level functions for atomic operations: generic M68k version -*- C++ -*-
-// Copyright (C) 2001 Free Software Foundation, Inc.
+// Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
@@ -27,17 +27,51 @@
// invalidate any other reasons why the executable file might be covered by
// the GNU General Public License.
+// there are three cases for m68k-variants I (ajg) am aware of that this
+// file needs to take care of:
+// * variants with the "cas" instruction
+// 68020/30/40/60
+// * variants with the "tas" instruction
+// cpu32, 5400
+// * variants with no atomic read/modify/write instruction at all
+// 68000/10, 5200/300
+//
+// code for cas method was pre-existing, tas method was written by
+// Aaron J. Grier <aaron at frye.com>, and interrupt disable method comes
+// from Eric Norum <eric at cls.usask.ca> and
+// Joel Sherrill <joel.sherrill at oarcorp.com>
+
#ifndef _BITS_ATOMICITY_H
#define _BITS_ATOMICITY_H 1
typedef int _Atomic_word;
+
+// atomically increment *__mem by __val and return the old *__mem
-static inline _Atomic_word
+static inline _Atomic_word
__attribute__ ((__unused__))
__exchange_and_add (volatile _Atomic_word *__mem, int __val)
{
register _Atomic_word __result = *__mem;
+
+#if defined(__mcpu32__) || defined(__mcf5400__)
+ static char __lock = 0; // needs to be a byte
+
+ // tas method
+ __asm__ __volatile__ ( "1: tas %1;"
+ " jbne 1b;"
+ " move%.l %3, %0;"
+ " add%.l %2, %3;"
+ " clrb %1;"
+ : "=d" (__result), "=m" (__lock)
+ : "d" (__val), "m" (*__mem), "0" (__result)
+ : "memory");
+#else
+#if defined(__mc68020__) || defined(__mc68030__) \
+ || defined(__mc68040__) || defined(__mc68060__)
register _Atomic_word __temp;
+
+ // cas method
__asm__ __volatile__ ("1: move%.l %0,%1;"
" add%.l %2,%1;"
" cas%.l %0,%1,%3;"
@@ -46,16 +80,52 @@
: "d" (__val), "m" (*__mem), "0" (__result)
: "memory");
return __result;
+#else
+#if defined(__rtems__) || defined(__vxWorks__) || defined(__embedded__)
+ volatile short __level;
+#if defined(__mcf5200__) || defined(__mcf5300__)
+ // coldfire v2 / v3 interrupt disable
+ unsigned int __tmpsr = 0x700;
+ __asm__ __volatile__ ( "move.w %%sr,%0;"
+ "or.l %0,%1;"
+ "move.w %1,%%sr"
+ : "=d" (__level), "=d"(__tmpsr)
+ : "1"(__tmpsr) );
+#else
+ // generic 68000 interrupt disable
+ __asm__ __volatile__ ( "move.w %%sr,%0;"
+ "or.w #0x0700,%%sr"
+ : "=d" (__level) );
+#endif
+#else
+#warning __exchange_and_add is not atomic for current target
+#endif
+ __result = *__mem;
+ *__mem += __val;
+
+#if defined(__rtems__) || defined(__vxWorks__) || defined(__embedded__)
+ __asm__ __volatile__ ( "move.w %0,%%sr " : : "d" (__level) );
+
+#endif
+#endif
+#endif
+
+ return __result;
}
+
+// atomically increment *__mem
-static inline void
+static void
__attribute__ ((__unused__))
__atomic_add (volatile _Atomic_word* __mem, int __val)
{
- __asm__ __volatile__ ("add%.l %0,%1"
- : : "id" (__val), "m" (*__mem) : "memory");
+ static unsigned char __lock;
+ _Atomic_word __tmp;
+
+ __asm__ __volatile__( "add%.l %1,(%0)"
+ :
+ : "a" (__mem), "d" (__val)
+ : "memory" );
}
#endif /* atomicity.h */
-
-
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