MSR storing - to Joel and E.Valette

[leonp]

Hello,
	Some points are still not clear for me:

Joel:
>This is the way RTEMS was spec'ed, designed, and implemented. :)
>Interrupt level is maintained per task (see rtems_task_mode()).
Yes, this is correct IMHO. But in MPC860 MSR doesn't contain the interrupt 
level, but the global interrupt enable bit only.
>Interrupt disable level and FPU enable are maintained on a per task
>basis. 
The MPC860 cpu does not have FPU. I suppose that you mean the FP context, yes?
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Eric Valette:
>Yes this will in general : the MSR status is a thread attribute that 
>shall not be lost. It contains for example the FP status (enabled 
>disabled, single stepping) that you cannot lost when switching back.
OK, now, if I want the CPU to be in single stepping, I personally definitely 
don't want to switch the contexts. The FP enabling is illegal for MPC860.

In general -  IMHO, the MSR is the MACHINE state register. I looked through 
all it bits once more and didn't find one that seems to be thread relative.

Thanks.
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leonp at plris.com