MSR storing - to Joel and E.Valette

[VALETTE Eric]

> RTEMS (the executive proper) has in general never considered interrupt
> controllers part of the per-thread context switch.  In order to properly
> support this, there would have to be general hooks for BSP specific
> support
> to do this.  I know that many PowerPC VME boards would have a terribly
> ugly time of providing a general solution.  

I agree. But I know no system requiring this as manipultaing these bits 
at thread level require to make the thread nonpreepmtible as you cannot 
guaranty that an IRQ will not occur if another task also manipulate the 
bits reenabling a non expected status due to restoring an original value...

TASK A

     	oldBits = current SIU bits
	SIU  newBits = olBits | mask

         sequence of instructions    <=== premptions occurs and other 
thread modify the SIU (e.g by putting oldBits again)

	Restore oldBits at SIU

-- 
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