Thank you - Re: Is there any Guru who knows why interrupts are disabled in ISR?

[Leon Pollak]

> On a CPU family with "good native" interrupt level support RTEMS uses
> that.
> The m68k is an example of that.  RTEMS does not disable interrupts but
> simply leaves them alone and lets higher priority interrupts be dealt
> with by the CPU.
>
> But the i386 and many PowerPC's have a single interrupt level from
> the CPU's perspective.  RTEMS does not automatically enable all
> external interrupts since a PIC would have to be touched and
> generically we don't know about it.  So it is the user's
> responsibility to deal with that PIC and "reenable" interrupts.
>
That is what I naturally wanted to know - there is no "principle"
restrictions
in RTEMS to do this. So I can do it as I want.

Many thanks for clarification.

leonp at plris.com