MIPS Cache and TLB Usage

Charles L. Nelson charles at embsyspro.com
Wed Dec 10 20:23:31 UTC 2003

I am working on a bsp variation for the AMD Alchemy Au1x00 series of MIPS32
(MIPS 4kc Core) based chips.  I would like to do some specific cache and tlb
manipulations for greater task/thread granularity and performance.  I have
been searching the source tree, but I don't see anything that directly ties
cache and tlb manipulations with the task/thread structure.

I would appreciate any pointers from anyone familiar with other bsp's, ports
or implementations of the MIPS architecture to RTEMS.


Charles L. Nelson

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