MIPS questions

Joel Sherrill joel.sherrill at OARcorp.com
Sat Oct 25 14:13:56 UTC 2003

Jay Monkman wrote:

>On Fri, Oct 24, 2003 at 05:57:16PM -0400, gregory.menke at gsfc.nasa.gov wrote:
>>The 2 byte offset seems a common optimization to put the ip header on
>>a paragraph boundary- Linux people do it in drivers sometimes.  gcc is
>><supposed> to be handling alignment, but whatever the mbuff stuff is
>>doing might be sneaking around it.  Could you give an example line #
>>so I can look at it directly?
>REASS_MBUF is defined on line 236 in tcp_var.h
>   #define REASS_MBUF(ti) (*(struct mbuf **)&((ti)->ti_t))
>In tcp_input.c, around line 207, is 
>   REASS_MBUF(ti) = m; 
>and around line 232, is
>   m = REASS_MBUF((struct tcpiphdr *)q->ti_prev);
>Since there's a lot of pointer manipulation going on, gcc has no way
>to ensure alignment, unless you want to make it check every pointer
>access, which would cause awful performance. I believe that if you can
>guarantee 4 byte alignment on the IP packet, this won't be a
>problem. However if the IP packet is not 4 byte aligned, this is a
>problem, unless there's some MIPS magic to handle misaligned accesses.
>I can make this go away by using the same fix that was used on ARM,
>but if the other MIPS BSPs don't have this problem, I'd like to use
>their method. Are the other MIPS network drivers able to ensure the IP
>packet is aligned?
There are so many MIPS variants with odd restrictions and differences 
that it would surprise
me if ALL MIPS CPU models had alignment restrictions.

Sometimes I ask Eric Cristopher (MIPS gcc and binutils person) when it 
comes to the
odd things like this.  He has a very broad view of the MIPS family.

>>This is R4000 code, which is in a lightly tested state right now.  You
>>should pay particular attention to anything interrupt-enabled, all the
>>interrupt level set/get functions for example.
>Without the extra parentheses, I fail the SP14 regression test, since
>it messes up CP0's status register. (It works fine on the jmr3904
>simulator, but that uses different code). When I add the parens, SP14
As Greg posted later, the testing has largely been on R3000 class CPUs.  
The reorganization
from the old mips64orion port was done to accomodate all MIPS models 
from one code
base.  But it was tested on the R3000 and may need fixes on the R4000.


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