BSP for MIPS32 4KC

[gregory.menke at gsfc.nasa.gov]

Michael Kelly writes:
 > 
 > Aaah, there in lies the rub.  MIPS has done a very poor
 > job of policing it's instruction set architectures (ISA).  Many
 > of the licensees have taken, well, license, to pick features from
 > MIPS I, II, III and IV.  For example, we had to compile the
 > assembly portion of our boot monitor for the Au1500 with
 > the -mips2 flag by itself, but the C portions with -mips2
 > and -mcpu=r4600.  As AMD describes it, the Au1 core is
 > MIPS32 with enhancements.  AFAIK, the enhancements
 > are mostly in the area of caching, but that's a pretty important
 > area!

I think the issue with MIPS32 is principally what register width and
instruction set it uses.  Cache issues are resolved by the bsp, so
aren't important here.  From looking at mikeci's patch, it appears the
context switch management changes are a wash, basically MIPS32 is
acting like an R4000, but for some reason (and I REALLY wish someone
would explain why), __mips == 3 isn't appropriate.

btw; I think there may be some floating point coprocessor issues to
resolve, presumably by enhancing cpu.h or potentially with a bsp
#define.  Some MIPS have mathco's, some don't, and I think its
probably going to be only the bsp that knows.

Gregm


 > 
 > Michael
 > 
 > At 12:41 PM 9/10/2003, gregory.menke at gsfc.nasa.gov wrote:
 > 
 > >mikeci at acm.org writes:
 > > > > Ivica,
 > > > >
 > > > > I am about to start a BSP for the AMD Au1500 which is MIPS32
 > > > > and I wonder if you have any specific details on the context
 > > > > and interrupt handling changes.  If not, what makes you feel this
 > > > > will be the case?
 > > > >
 > > > > Thanks,
 > > > > Michael
 > > > >
 > > > Michael,
 > > > 
 > > > Take look in $RTEMS_HOME/cpukit/score/cpu/mips. There you have cpu.c and
 > > > cpu_asm.S. Edit cpu_asm.S and search for function _ISR_Handler. You will
 > > > see that this function returns with:
 > > > 
 > > >      j         k1
 > > >      rfe
 > > >         NOP
 > > > 
 > > >        .set    reorder
 > > > ENDFRAME(_ISR_Handler)
 > > > 
 > > > This is incorrect for MIP32. rfe instruction is reserved for R3000 and not
 > > > for MIP32.
 > >
 > >Could you please define what MIPS32 is, very explicitely?  By that I
 > >mean what register width, what cpu family, etc...  
 > >
 > >I still don't know what MIPS32 is other than as a #define!  If its
 > >R4000 with 32 bit registers, that should be supported right now via
 > >_mips3.
 > >
 > >The j k1, rfe formulation is for R3000, R4000 has its own protocol-
 > >which is already supported by the cpukit (context switches, etc..).
 > >At present the R4000 context employs 64 bit registers, but the MIPS
 > >bsp's are all 32 bits, so I think at present, all MIPS support could
 > >be shifted to that.
 > >
 > >Gregm
 > 
 > Michael J. Kelly
 > VP Engineering/Marketing
 > Cogent Computer Systems, Inc.
 > 1130 Ten Rod Road
 > Suite A-201
 > North Kingstown, RI 02852
 > tel:401-295-6505 fax:401-295-6507
 > www.cogcomp.com
 > alternate email: mkelly6505 at hotmail.com
 > 
 > 
 >